drv_adc.c 5.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208
  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2021-08-20 breo.com first version
  9. */
  10. #include <board.h>
  11. #include "drv_adc.h"
  12. #if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3)
  13. #define DRV_DEBUG
  14. #define LOG_TAG "drv.adc"
  15. #include <drv_log.h>
  16. struct n32_adc
  17. {
  18. struct rt_adc_device n32_adc_device;
  19. ADC_Module *ADC_Handler;
  20. char *name;
  21. };
  22. static struct n32_adc n32_adc_obj[] =
  23. {
  24. #ifdef BSP_USING_ADC1
  25. ADC1_CONFIG,
  26. #endif
  27. #ifdef BSP_USING_ADC2
  28. ADC2_CONFIG,
  29. #endif
  30. #ifdef BSP_USING_ADC3
  31. ADC3_CONFIG,
  32. #endif
  33. };
  34. static rt_uint32_t n32_adc_get_channel(rt_uint32_t channel)
  35. {
  36. rt_uint32_t n32_channel = 0;
  37. switch (channel)
  38. {
  39. case 0:
  40. n32_channel = ADC_CH_0;
  41. break;
  42. case 1:
  43. n32_channel = ADC_CH_1;
  44. break;
  45. case 2:
  46. n32_channel = ADC_CH_2;
  47. break;
  48. case 3:
  49. n32_channel = ADC_CH_3;
  50. break;
  51. case 4:
  52. n32_channel = ADC_CH_4;
  53. break;
  54. case 5:
  55. n32_channel = ADC_CH_5;
  56. break;
  57. case 6:
  58. n32_channel = ADC_CH_6;
  59. break;
  60. case 7:
  61. n32_channel = ADC_CH_7;
  62. break;
  63. case 8:
  64. n32_channel = ADC_CH_8;
  65. break;
  66. case 9:
  67. n32_channel = ADC_CH_9;
  68. break;
  69. case 10:
  70. n32_channel = ADC_CH_10;
  71. break;
  72. case 11:
  73. n32_channel = ADC_CH_11;
  74. break;
  75. case 12:
  76. n32_channel = ADC_CH_12;
  77. break;
  78. case 13:
  79. n32_channel = ADC_CH_13;
  80. break;
  81. case 14:
  82. n32_channel = ADC_CH_14;
  83. break;
  84. case 15:
  85. n32_channel = ADC_CH_15;
  86. break;
  87. case 16:
  88. n32_channel = ADC_CH_16;
  89. break;
  90. case 17:
  91. n32_channel = ADC_CH_17;
  92. break;
  93. }
  94. return n32_channel;
  95. }
  96. static rt_err_t n32_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
  97. {
  98. ADC_Module *n32_adc_handler;
  99. ADC_InitType ADC_InitStructure;
  100. RT_ASSERT(device != RT_NULL);
  101. n32_adc_handler = device->parent.user_data;
  102. n32_msp_adc_init(n32_adc_handler);
  103. /* ADCx configuration ------------------------------------------------------*/
  104. ADC_InitStruct(&ADC_InitStructure);
  105. ADC_InitStructure.WorkMode = ADC_WORKMODE_INDEPENDENT;
  106. ADC_InitStructure.MultiChEn = DISABLE;
  107. ADC_InitStructure.ContinueConvEn = DISABLE;
  108. ADC_InitStructure.ExtTrigSelect = ADC_EXT_TRIGCONV_NONE;
  109. ADC_InitStructure.DatAlign = ADC_DAT_ALIGN_R;
  110. ADC_InitStructure.ChsNumber = 1;
  111. ADC_Init(n32_adc_handler, &ADC_InitStructure);
  112. /* ADCx regular channels configuration */
  113. ADC_ConfigRegularChannel(n32_adc_handler, n32_adc_get_channel(channel), 1, ADC_SAMP_TIME_28CYCLES5);
  114. /* Enable ADCx */
  115. ADC_Enable(n32_adc_handler, ENABLE);
  116. // /* Enable ADCx reset calibration register */
  117. // ADC_RstCalibration(n32_adc_handler);
  118. // /* Check the end of ADCx reset calibration register */
  119. // while(ADC_GetResetCalibrationStatus(n32_adc_handler));
  120. /* Start ADCx calibration */
  121. ADC_StartCalibration(n32_adc_handler);
  122. /* Check the end of ADCx calibration */
  123. while(ADC_GetCalibrationStatus(n32_adc_handler));
  124. if (enabled)
  125. {
  126. /* Enable ADC1 */
  127. ADC_Enable(n32_adc_handler, ENABLE);
  128. }
  129. else
  130. {
  131. /* Enable ADCx */
  132. ADC_Enable(n32_adc_handler, DISABLE);
  133. }
  134. return RT_EOK;
  135. }
  136. static rt_err_t n32_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
  137. {
  138. ADC_Module *n32_adc_handler;
  139. RT_ASSERT(device != RT_NULL);
  140. RT_ASSERT(value != RT_NULL);
  141. n32_adc_handler = device->parent.user_data;
  142. /* Start ADCx Software Conversion */
  143. ADC_EnableSoftwareStartConv(n32_adc_handler, ENABLE);
  144. /* Wait for the ADC to convert */
  145. while(ADC_GetFlagStatus(n32_adc_handler, ADC_FLAG_ENDC) == RESET);
  146. /* get ADC value */
  147. *value = ADC_GetDat(n32_adc_handler);
  148. return RT_EOK;
  149. }
  150. static const struct rt_adc_ops at_adc_ops =
  151. {
  152. .enabled = n32_adc_enabled,
  153. .convert = n32_get_adc_value,
  154. };
  155. static int rt_hw_adc_init(void)
  156. {
  157. int result = RT_EOK;
  158. int i = 0;
  159. for (i = 0; i < sizeof(n32_adc_obj) / sizeof(n32_adc_obj[0]); i++)
  160. {
  161. /* register ADC device */
  162. if (rt_hw_adc_register(&n32_adc_obj[i].n32_adc_device,
  163. n32_adc_obj[i].name, &at_adc_ops,
  164. n32_adc_obj[i].ADC_Handler) == RT_EOK)
  165. {
  166. LOG_D("%s register success", n32_adc_obj[i].name);
  167. }
  168. else
  169. {
  170. LOG_E("%s register failed", n32_adc_obj[i].name);
  171. result = -RT_ERROR;
  172. }
  173. }
  174. return result;
  175. }
  176. INIT_BOARD_EXPORT(rt_hw_adc_init);
  177. #endif /* BSP_USING_ADC */