board.c 4.7 KB

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  1. /*
  2. * Copyright (c) 2006-2019, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2019-07-29 zdzn first version
  9. */
  10. #include <rthw.h>
  11. #include <rtthread.h>
  12. #include "board.h"
  13. #include "drv_uart.h"
  14. #include "drv_timer.h"
  15. #include "cp15.h"
  16. #include "mmu.h"
  17. #include "raspi.h"
  18. #ifdef BSP_USING_CORETIMER
  19. static rt_uint64_t timerStep;
  20. #define CORE0_TIMER_IRQ_CTRL HWREG32(0x40000040)
  21. int rt_hw_get_gtimer_frq(void);
  22. void rt_hw_set_gtimer_val(rt_uint64_t value);
  23. int rt_hw_get_gtimer_val(void);
  24. int rt_hw_get_cntpct_val(void);
  25. void rt_hw_gtimer_enable(void);
  26. void core0_timer_enable_interrupt_controller()
  27. {
  28. CORE0_TIMER_IRQ_CTRL |= NON_SECURE_TIMER_IRQ;
  29. }
  30. #endif
  31. #ifdef RT_USING_SMP
  32. extern void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler);
  33. void ipi_handler(){
  34. rt_scheduler_ipi_handler(0,RT_NULL);
  35. }
  36. #endif
  37. void rt_hw_timer_isr(int vector, void *parameter)
  38. {
  39. #ifdef BSP_USING_CORETIMER
  40. rt_hw_set_gtimer_val(timerStep);
  41. #else
  42. ARM_TIMER_IRQCLR = 0;
  43. #endif
  44. rt_tick_increase();
  45. }
  46. void rt_hw_timer_init(void)
  47. {
  48. rt_hw_interrupt_install(IRQ_ARM_TIMER, rt_hw_timer_isr, RT_NULL, "tick");
  49. rt_hw_interrupt_umask(IRQ_ARM_TIMER);
  50. #ifdef BSP_USING_CORETIMER
  51. __ISB();
  52. timerStep = rt_hw_get_gtimer_frq();
  53. __DSB();
  54. timerStep /= RT_TICK_PER_SECOND;
  55. rt_hw_gtimer_enable();
  56. rt_hw_set_gtimer_val(timerStep);
  57. core0_timer_enable_interrupt_controller();
  58. #else
  59. __DSB();
  60. /* timer_clock = apb_clock/(pre_divider + 1) */
  61. ARM_TIMER_PREDIV = (250 - 1);
  62. ARM_TIMER_RELOAD = 0;
  63. ARM_TIMER_LOAD = 0;
  64. ARM_TIMER_IRQCLR = 0;
  65. ARM_TIMER_CTRL = 0;
  66. ARM_TIMER_RELOAD = 10000;
  67. ARM_TIMER_LOAD = 10000;
  68. /* 23-bit counter, enable interrupt, enable timer */
  69. ARM_TIMER_CTRL = (1 << 1) | (1 << 5) | (1 << 7);
  70. #endif
  71. }
  72. void idle_wfi(void)
  73. {
  74. asm volatile ("wfi");
  75. }
  76. /**
  77. * Initialize the Hardware related stuffs. Called from rtthread_startup()
  78. * after interrupt disabled.
  79. */
  80. void rt_hw_board_init(void)
  81. {
  82. mmu_init();
  83. armv8_map(0, 0, 0x6400000, MEM_ATTR_MEMORY);
  84. armv8_map(0x3f000000, 0x3f000000, 0x200000, MEM_ATTR_IO);//timer
  85. armv8_map(0x3f200000, 0x3f200000, 0x16000, MEM_ATTR_IO);//uart
  86. armv8_map(0x40000000, 0x40000000, 0x1000, MEM_ATTR_IO);//core timer
  87. armv8_map(0x3F300000, 0x3F300000, 0x1000, MEM_ATTR_IO);//sdio
  88. armv8_map(0xc00000, 0xc00000, 0x1000, MEM_ATTR_IO);//mbox
  89. armv8_map(0x3f804000, 0x3f804000, 0x1000, MEM_ATTR_IO);//i2c0
  90. armv8_map(0x3f205000, 0x3f205000, 0x1000, MEM_ATTR_IO);//i2c1
  91. mmu_enable();
  92. /* initialize hardware interrupt */
  93. rt_hw_interrupt_init(); // in libcpu/interrupt.c. Set some data structures, no operation on device
  94. rt_hw_vector_init(); // in libcpu/interrupt.c. == rt_cpu_vector_set_base((rt_ubase_t)&system_vectors);
  95. /* initialize uart */
  96. rt_hw_uart_init(); // driver/drv_uart.c
  97. /* initialize timer for os tick */
  98. rt_hw_timer_init();
  99. rt_thread_idle_sethook(idle_wfi);
  100. #ifdef RT_USING_CONSOLE
  101. /* set console device */
  102. rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
  103. #endif /* RT_USING_CONSOLE */
  104. #ifdef RT_USING_HEAP
  105. /* initialize memory system */
  106. rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
  107. rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
  108. #endif
  109. #ifdef RT_USING_COMPONENTS_INIT
  110. rt_components_board_init();
  111. #endif
  112. }
  113. #ifdef RT_USING_SMP
  114. void _reset(void);
  115. void secondary_cpu_start(void);
  116. void rt_hw_secondary_cpu_up(void)
  117. {
  118. int i;
  119. int retry,val;
  120. rt_cpu_dcache_clean_flush();
  121. rt_cpu_icache_flush();
  122. /*TODO maybe, there is some bug */
  123. for(i=RT_CPUS_NR-1; i>0; i-- )
  124. {
  125. rt_kprintf("boot cpu:%d\n", i);
  126. setup_bootstrap_addr(i, (int)_reset);
  127. __SEV();
  128. __DSB();
  129. __ISB();
  130. retry = 10;
  131. rt_thread_delay(RT_TICK_PER_SECOND/1000);
  132. do
  133. {
  134. val = CORE_MAILBOX3_CLEAR(i);
  135. if (val == 0)
  136. {
  137. rt_kprintf("start OK: CPU %d \n",i);
  138. break;
  139. }
  140. rt_thread_delay(RT_TICK_PER_SECOND);
  141. retry --;
  142. if (retry <= 0)
  143. {
  144. rt_kprintf("can't start for CPU %d \n",i);
  145. break;
  146. }
  147. }while (1);
  148. }
  149. __DSB();
  150. __SEV();
  151. }
  152. void secondary_cpu_c_start(void)
  153. {
  154. uint32_t id;
  155. id = rt_hw_cpu_id();
  156. rt_kprintf("cpu = 0x%08x\n",id);
  157. rt_hw_timer_init();
  158. rt_kprintf("cpu %d startup.\n",id);
  159. rt_hw_vector_init();
  160. enable_cpu_ipi_intr(id);
  161. rt_hw_spin_lock(&_cpus_lock);
  162. rt_system_scheduler_start();
  163. }
  164. void rt_hw_secondary_cpu_idle_exec(void)
  165. {
  166. __WFE();
  167. }
  168. #endif