drv_usart.c 30 KB

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  1. /*
  2. * Copyright (c) 2006-2018, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-10-30 SummerGift first version
  9. * 2020-03-16 SummerGift add device close feature
  10. * 2020-03-20 SummerGift fix bug caused by ORE
  11. */
  12. #include "board.h"
  13. #include "drv_usart.h"
  14. #include "drv_config.h"
  15. #ifdef RT_USING_SERIAL
  16. //#define DRV_DEBUG
  17. #define LOG_TAG "drv.usart"
  18. #include <drv_log.h>
  19. #if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && \
  20. !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && \
  21. !defined(BSP_USING_UART7) && !defined(BSP_USING_UART8) && !defined(BSP_USING_LPUART1)
  22. #error "Please define at least one BSP_USING_UARTx"
  23. /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
  24. #endif
  25. #ifdef RT_SERIAL_USING_DMA
  26. static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag);
  27. #endif
  28. enum
  29. {
  30. #ifdef BSP_USING_UART1
  31. UART1_INDEX,
  32. #endif
  33. #ifdef BSP_USING_UART2
  34. UART2_INDEX,
  35. #endif
  36. #ifdef BSP_USING_UART3
  37. UART3_INDEX,
  38. #endif
  39. #ifdef BSP_USING_UART4
  40. UART4_INDEX,
  41. #endif
  42. #ifdef BSP_USING_UART5
  43. UART5_INDEX,
  44. #endif
  45. #ifdef BSP_USING_UART6
  46. UART6_INDEX,
  47. #endif
  48. #ifdef BSP_USING_UART7
  49. UART7_INDEX,
  50. #endif
  51. #ifdef BSP_USING_UART8
  52. UART8_INDEX,
  53. #endif
  54. #ifdef BSP_USING_LPUART1
  55. LPUART1_INDEX,
  56. #endif
  57. };
  58. static struct stm32_uart_config uart_config[] =
  59. {
  60. #ifdef BSP_USING_UART1
  61. UART1_CONFIG,
  62. #endif
  63. #ifdef BSP_USING_UART2
  64. UART2_CONFIG,
  65. #endif
  66. #ifdef BSP_USING_UART3
  67. UART3_CONFIG,
  68. #endif
  69. #ifdef BSP_USING_UART4
  70. UART4_CONFIG,
  71. #endif
  72. #ifdef BSP_USING_UART5
  73. UART5_CONFIG,
  74. #endif
  75. #ifdef BSP_USING_UART6
  76. UART6_CONFIG,
  77. #endif
  78. #ifdef BSP_USING_UART7
  79. UART7_CONFIG,
  80. #endif
  81. #ifdef BSP_USING_UART8
  82. UART8_CONFIG,
  83. #endif
  84. #ifdef BSP_USING_LPUART1
  85. LPUART1_CONFIG,
  86. #endif
  87. };
  88. static struct stm32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
  89. static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
  90. {
  91. struct stm32_uart *uart;
  92. RT_ASSERT(serial != RT_NULL);
  93. RT_ASSERT(cfg != RT_NULL);
  94. uart = rt_container_of(serial, struct stm32_uart, serial);
  95. uart->handle.Instance = uart->config->Instance;
  96. uart->handle.Init.BaudRate = cfg->baud_rate;
  97. uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
  98. uart->handle.Init.Mode = UART_MODE_TX_RX;
  99. uart->handle.Init.OverSampling = UART_OVERSAMPLING_16;
  100. switch (cfg->data_bits)
  101. {
  102. case DATA_BITS_8:
  103. uart->handle.Init.WordLength = UART_WORDLENGTH_8B;
  104. break;
  105. case DATA_BITS_9:
  106. uart->handle.Init.WordLength = UART_WORDLENGTH_9B;
  107. break;
  108. default:
  109. uart->handle.Init.WordLength = UART_WORDLENGTH_8B;
  110. break;
  111. }
  112. switch (cfg->stop_bits)
  113. {
  114. case STOP_BITS_1:
  115. uart->handle.Init.StopBits = UART_STOPBITS_1;
  116. break;
  117. case STOP_BITS_2:
  118. uart->handle.Init.StopBits = UART_STOPBITS_2;
  119. break;
  120. default:
  121. uart->handle.Init.StopBits = UART_STOPBITS_1;
  122. break;
  123. }
  124. switch (cfg->parity)
  125. {
  126. case PARITY_NONE:
  127. uart->handle.Init.Parity = UART_PARITY_NONE;
  128. break;
  129. case PARITY_ODD:
  130. uart->handle.Init.Parity = UART_PARITY_ODD;
  131. break;
  132. case PARITY_EVEN:
  133. uart->handle.Init.Parity = UART_PARITY_EVEN;
  134. break;
  135. default:
  136. uart->handle.Init.Parity = UART_PARITY_NONE;
  137. break;
  138. }
  139. #ifdef RT_SERIAL_USING_DMA
  140. uart->dma_rx.last_index = 0;
  141. #endif
  142. if (HAL_UART_Init(&uart->handle) != HAL_OK)
  143. {
  144. return -RT_ERROR;
  145. }
  146. return RT_EOK;
  147. }
  148. static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *arg)
  149. {
  150. struct stm32_uart *uart;
  151. #ifdef RT_SERIAL_USING_DMA
  152. rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
  153. #endif
  154. RT_ASSERT(serial != RT_NULL);
  155. uart = rt_container_of(serial, struct stm32_uart, serial);
  156. switch (cmd)
  157. {
  158. /* disable interrupt */
  159. case RT_DEVICE_CTRL_CLR_INT:
  160. /* disable rx irq */
  161. NVIC_DisableIRQ(uart->config->irq_type);
  162. /* disable interrupt */
  163. __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_RXNE);
  164. #ifdef RT_SERIAL_USING_DMA
  165. /* disable DMA */
  166. if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX)
  167. {
  168. HAL_NVIC_DisableIRQ(uart->config->dma_rx->dma_irq);
  169. if (HAL_DMA_Abort(&(uart->dma_rx.handle)) != HAL_OK)
  170. {
  171. RT_ASSERT(0);
  172. }
  173. if (HAL_DMA_DeInit(&(uart->dma_rx.handle)) != HAL_OK)
  174. {
  175. RT_ASSERT(0);
  176. }
  177. }
  178. else if(ctrl_arg == RT_DEVICE_FLAG_DMA_TX)
  179. {
  180. HAL_NVIC_DisableIRQ(uart->config->dma_tx->dma_irq);
  181. if (HAL_DMA_DeInit(&(uart->dma_tx.handle)) != HAL_OK)
  182. {
  183. RT_ASSERT(0);
  184. }
  185. }
  186. #endif
  187. break;
  188. /* enable interrupt */
  189. case RT_DEVICE_CTRL_SET_INT:
  190. /* enable rx irq */
  191. NVIC_EnableIRQ(uart->config->irq_type);
  192. /* enable interrupt */
  193. __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_RXNE);
  194. break;
  195. #ifdef RT_SERIAL_USING_DMA
  196. case RT_DEVICE_CTRL_CONFIG:
  197. stm32_dma_config(serial, ctrl_arg);
  198. break;
  199. #endif
  200. case RT_DEVICE_CTRL_CLOSE:
  201. if (HAL_UART_DeInit(&(uart->handle)) != HAL_OK )
  202. {
  203. RT_ASSERT(0)
  204. }
  205. break;
  206. }
  207. return RT_EOK;
  208. }
  209. static int stm32_putc(struct rt_serial_device *serial, char c)
  210. {
  211. struct stm32_uart *uart;
  212. RT_ASSERT(serial != RT_NULL);
  213. uart = rt_container_of(serial, struct stm32_uart, serial);
  214. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
  215. #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
  216. || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) \
  217. || defined(SOC_SERIES_STM32G4)
  218. uart->handle.Instance->TDR = c;
  219. #else
  220. uart->handle.Instance->DR = c;
  221. #endif
  222. while (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) == RESET);
  223. return 1;
  224. }
  225. static int stm32_getc(struct rt_serial_device *serial)
  226. {
  227. int ch;
  228. struct stm32_uart *uart;
  229. RT_ASSERT(serial != RT_NULL);
  230. uart = rt_container_of(serial, struct stm32_uart, serial);
  231. ch = -1;
  232. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET)
  233. {
  234. #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
  235. || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) \
  236. || defined(SOC_SERIES_STM32G4)
  237. ch = uart->handle.Instance->RDR & 0xff;
  238. #else
  239. ch = uart->handle.Instance->DR & 0xff;
  240. #endif
  241. }
  242. return ch;
  243. }
  244. static rt_size_t stm32_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
  245. {
  246. struct stm32_uart *uart;
  247. RT_ASSERT(serial != RT_NULL);
  248. RT_ASSERT(buf != RT_NULL);
  249. uart = rt_container_of(serial, struct stm32_uart, serial);
  250. if (size == 0)
  251. {
  252. return 0;
  253. }
  254. if (RT_SERIAL_DMA_TX == direction)
  255. {
  256. if (HAL_UART_Transmit_DMA(&uart->handle, buf, size) == HAL_OK)
  257. {
  258. return size;
  259. }
  260. else
  261. {
  262. return 0;
  263. }
  264. }
  265. return 0;
  266. }
  267. /**
  268. * Uart common interrupt process. This need add to uart ISR.
  269. *
  270. * @param serial serial device
  271. */
  272. static void uart_isr(struct rt_serial_device *serial)
  273. {
  274. struct stm32_uart *uart;
  275. #ifdef RT_SERIAL_USING_DMA
  276. rt_size_t recv_total_index, recv_len;
  277. rt_base_t level;
  278. #endif
  279. RT_ASSERT(serial != RT_NULL);
  280. uart = rt_container_of(serial, struct stm32_uart, serial);
  281. /* UART in mode Receiver -------------------------------------------------*/
  282. if ((__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET) &&
  283. (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_RXNE) != RESET))
  284. {
  285. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
  286. }
  287. #ifdef RT_SERIAL_USING_DMA
  288. else if ((uart->uart_dma_flag) && (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_IDLE) != RESET)
  289. && (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_IDLE) != RESET))
  290. {
  291. level = rt_hw_interrupt_disable();
  292. recv_total_index = serial->config.bufsz - __HAL_DMA_GET_COUNTER(&(uart->dma_rx.handle));
  293. recv_len = recv_total_index - uart->dma_rx.last_index;
  294. uart->dma_rx.last_index = recv_total_index;
  295. rt_hw_interrupt_enable(level);
  296. if (recv_len)
  297. {
  298. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
  299. }
  300. __HAL_UART_CLEAR_IDLEFLAG(&uart->handle);
  301. }
  302. else if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) &&
  303. (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_TC) != RESET))
  304. {
  305. if ((serial->parent.open_flag & RT_DEVICE_FLAG_DMA_TX) != 0)
  306. {
  307. HAL_UART_IRQHandler(&(uart->handle));
  308. }
  309. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
  310. }
  311. #endif
  312. else
  313. {
  314. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_ORE) != RESET)
  315. {
  316. __HAL_UART_CLEAR_OREFLAG(&uart->handle);
  317. }
  318. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_NE) != RESET)
  319. {
  320. __HAL_UART_CLEAR_NEFLAG(&uart->handle);
  321. }
  322. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_FE) != RESET)
  323. {
  324. __HAL_UART_CLEAR_FEFLAG(&uart->handle);
  325. }
  326. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_PE) != RESET)
  327. {
  328. __HAL_UART_CLEAR_PEFLAG(&uart->handle);
  329. }
  330. #if !defined(SOC_SERIES_STM32L4) && !defined(SOC_SERIES_STM32F7) && !defined(SOC_SERIES_STM32F0) \
  331. && !defined(SOC_SERIES_STM32L0) && !defined(SOC_SERIES_STM32G0) && !defined(SOC_SERIES_STM32H7) \
  332. && !defined(SOC_SERIES_STM32G4)
  333. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBD) != RESET)
  334. {
  335. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_LBD);
  336. }
  337. #endif
  338. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_CTS) != RESET)
  339. {
  340. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_CTS);
  341. }
  342. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TXE) != RESET)
  343. {
  344. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TXE);
  345. }
  346. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) != RESET)
  347. {
  348. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
  349. }
  350. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET)
  351. {
  352. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_RXNE);
  353. }
  354. }
  355. }
  356. #ifdef RT_SERIAL_USING_DMA
  357. static void dma_isr(struct rt_serial_device *serial)
  358. {
  359. struct stm32_uart *uart;
  360. rt_size_t recv_total_index, recv_len;
  361. rt_base_t level;
  362. RT_ASSERT(serial != RT_NULL);
  363. uart = rt_container_of(serial, struct stm32_uart, serial);
  364. if ((__HAL_DMA_GET_IT_SOURCE(&(uart->dma_rx.handle), DMA_IT_TC) != RESET) ||
  365. (__HAL_DMA_GET_IT_SOURCE(&(uart->dma_rx.handle), DMA_IT_HT) != RESET))
  366. {
  367. level = rt_hw_interrupt_disable();
  368. recv_total_index = serial->config.bufsz - __HAL_DMA_GET_COUNTER(&(uart->dma_rx.handle));
  369. if (recv_total_index == 0)
  370. {
  371. recv_len = serial->config.bufsz - uart->dma_rx.last_index;
  372. }
  373. else
  374. {
  375. recv_len = recv_total_index - uart->dma_rx.last_index;
  376. }
  377. uart->dma_rx.last_index = recv_total_index;
  378. rt_hw_interrupt_enable(level);
  379. if (recv_len)
  380. {
  381. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
  382. }
  383. }
  384. }
  385. #endif
  386. #if defined(BSP_USING_UART1)
  387. void USART1_IRQHandler(void)
  388. {
  389. /* enter interrupt */
  390. rt_interrupt_enter();
  391. uart_isr(&(uart_obj[UART1_INDEX].serial));
  392. /* leave interrupt */
  393. rt_interrupt_leave();
  394. }
  395. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA)
  396. void UART1_DMA_RX_IRQHandler(void)
  397. {
  398. /* enter interrupt */
  399. rt_interrupt_enter();
  400. HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_rx.handle);
  401. /* leave interrupt */
  402. rt_interrupt_leave();
  403. }
  404. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) */
  405. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA)
  406. void UART1_DMA_TX_IRQHandler(void)
  407. {
  408. /* enter interrupt */
  409. rt_interrupt_enter();
  410. HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_tx.handle);
  411. /* leave interrupt */
  412. rt_interrupt_leave();
  413. }
  414. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA) */
  415. #endif /* BSP_USING_UART1 */
  416. #if defined(BSP_USING_UART2)
  417. void USART2_IRQHandler(void)
  418. {
  419. /* enter interrupt */
  420. rt_interrupt_enter();
  421. uart_isr(&(uart_obj[UART2_INDEX].serial));
  422. /* leave interrupt */
  423. rt_interrupt_leave();
  424. }
  425. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA)
  426. void UART2_DMA_RX_IRQHandler(void)
  427. {
  428. /* enter interrupt */
  429. rt_interrupt_enter();
  430. HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma_rx.handle);
  431. /* leave interrupt */
  432. rt_interrupt_leave();
  433. }
  434. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) */
  435. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA)
  436. void UART2_DMA_TX_IRQHandler(void)
  437. {
  438. /* enter interrupt */
  439. rt_interrupt_enter();
  440. HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma_tx.handle);
  441. /* leave interrupt */
  442. rt_interrupt_leave();
  443. }
  444. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA) */
  445. #endif /* BSP_USING_UART2 */
  446. #if defined(BSP_USING_UART3)
  447. void USART3_IRQHandler(void)
  448. {
  449. /* enter interrupt */
  450. rt_interrupt_enter();
  451. uart_isr(&(uart_obj[UART3_INDEX].serial));
  452. /* leave interrupt */
  453. rt_interrupt_leave();
  454. }
  455. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_RX_USING_DMA)
  456. void UART3_DMA_RX_IRQHandler(void)
  457. {
  458. /* enter interrupt */
  459. rt_interrupt_enter();
  460. HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma_rx.handle);
  461. /* leave interrupt */
  462. rt_interrupt_leave();
  463. }
  464. #endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART3_RX_USING_DMA) */
  465. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_TX_USING_DMA)
  466. void UART3_DMA_TX_IRQHandler(void)
  467. {
  468. /* enter interrupt */
  469. rt_interrupt_enter();
  470. HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma_tx.handle);
  471. /* leave interrupt */
  472. rt_interrupt_leave();
  473. }
  474. #endif /* defined(BSP_UART_USING_DMA_TX) && defined(BSP_UART3_TX_USING_DMA) */
  475. #endif /* BSP_USING_UART3*/
  476. #if defined(BSP_USING_UART4)
  477. void UART4_IRQHandler(void)
  478. {
  479. /* enter interrupt */
  480. rt_interrupt_enter();
  481. uart_isr(&(uart_obj[UART4_INDEX].serial));
  482. /* leave interrupt */
  483. rt_interrupt_leave();
  484. }
  485. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_RX_USING_DMA)
  486. void UART4_DMA_RX_IRQHandler(void)
  487. {
  488. /* enter interrupt */
  489. rt_interrupt_enter();
  490. HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma_rx.handle);
  491. /* leave interrupt */
  492. rt_interrupt_leave();
  493. }
  494. #endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART4_RX_USING_DMA) */
  495. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_TX_USING_DMA)
  496. void UART4_DMA_TX_IRQHandler(void)
  497. {
  498. /* enter interrupt */
  499. rt_interrupt_enter();
  500. HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma_tx.handle);
  501. /* leave interrupt */
  502. rt_interrupt_leave();
  503. }
  504. #endif /* defined(BSP_UART_USING_DMA_TX) && defined(BSP_UART4_TX_USING_DMA) */
  505. #endif /* BSP_USING_UART4*/
  506. #if defined(BSP_USING_UART5)
  507. void UART5_IRQHandler(void)
  508. {
  509. /* enter interrupt */
  510. rt_interrupt_enter();
  511. uart_isr(&(uart_obj[UART5_INDEX].serial));
  512. /* leave interrupt */
  513. rt_interrupt_leave();
  514. }
  515. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA)
  516. void UART5_DMA_RX_IRQHandler(void)
  517. {
  518. /* enter interrupt */
  519. rt_interrupt_enter();
  520. HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma_rx.handle);
  521. /* leave interrupt */
  522. rt_interrupt_leave();
  523. }
  524. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA) */
  525. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA)
  526. void UART5_DMA_TX_IRQHandler(void)
  527. {
  528. /* enter interrupt */
  529. rt_interrupt_enter();
  530. HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma_tx.handle);
  531. /* leave interrupt */
  532. rt_interrupt_leave();
  533. }
  534. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA) */
  535. #endif /* BSP_USING_UART5*/
  536. #if defined(BSP_USING_UART6)
  537. void USART6_IRQHandler(void)
  538. {
  539. /* enter interrupt */
  540. rt_interrupt_enter();
  541. uart_isr(&(uart_obj[UART6_INDEX].serial));
  542. /* leave interrupt */
  543. rt_interrupt_leave();
  544. }
  545. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA)
  546. void UART6_DMA_RX_IRQHandler(void)
  547. {
  548. /* enter interrupt */
  549. rt_interrupt_enter();
  550. HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma_rx.handle);
  551. /* leave interrupt */
  552. rt_interrupt_leave();
  553. }
  554. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA) */
  555. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA)
  556. void UART6_DMA_TX_IRQHandler(void)
  557. {
  558. /* enter interrupt */
  559. rt_interrupt_enter();
  560. HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma_tx.handle);
  561. /* leave interrupt */
  562. rt_interrupt_leave();
  563. }
  564. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA) */
  565. #endif /* BSP_USING_UART6*/
  566. #if defined(BSP_USING_UART7)
  567. void UART7_IRQHandler(void)
  568. {
  569. /* enter interrupt */
  570. rt_interrupt_enter();
  571. uart_isr(&(uart_obj[UART7_INDEX].serial));
  572. /* leave interrupt */
  573. rt_interrupt_leave();
  574. }
  575. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA)
  576. void UART7_DMA_RX_IRQHandler(void)
  577. {
  578. /* enter interrupt */
  579. rt_interrupt_enter();
  580. HAL_DMA_IRQHandler(&uart_obj[UART7_INDEX].dma_rx.handle);
  581. /* leave interrupt */
  582. rt_interrupt_leave();
  583. }
  584. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA) */
  585. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA)
  586. void UART7_DMA_TX_IRQHandler(void)
  587. {
  588. /* enter interrupt */
  589. rt_interrupt_enter();
  590. HAL_DMA_IRQHandler(&uart_obj[UART7_INDEX].dma_tx.handle);
  591. /* leave interrupt */
  592. rt_interrupt_leave();
  593. }
  594. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA) */
  595. #endif /* BSP_USING_UART7*/
  596. #if defined(BSP_USING_UART8)
  597. void UART8_IRQHandler(void)
  598. {
  599. /* enter interrupt */
  600. rt_interrupt_enter();
  601. uart_isr(&(uart_obj[UART8_INDEX].serial));
  602. /* leave interrupt */
  603. rt_interrupt_leave();
  604. }
  605. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA)
  606. void UART8_DMA_RX_IRQHandler(void)
  607. {
  608. /* enter interrupt */
  609. rt_interrupt_enter();
  610. HAL_DMA_IRQHandler(&uart_obj[UART8_INDEX].dma_rx.handle);
  611. /* leave interrupt */
  612. rt_interrupt_leave();
  613. }
  614. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA) */
  615. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA)
  616. void UART8_DMA_TX_IRQHandler(void)
  617. {
  618. /* enter interrupt */
  619. rt_interrupt_enter();
  620. HAL_DMA_IRQHandler(&uart_obj[UART8_INDEX].dma_tx.handle);
  621. /* leave interrupt */
  622. rt_interrupt_leave();
  623. }
  624. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA) */
  625. #endif /* BSP_USING_UART8*/
  626. #if defined(BSP_USING_LPUART1)
  627. void LPUART1_IRQHandler(void)
  628. {
  629. /* enter interrupt */
  630. rt_interrupt_enter();
  631. uart_isr(&(uart_obj[LPUART1_INDEX].serial));
  632. /* leave interrupt */
  633. rt_interrupt_leave();
  634. }
  635. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA)
  636. void LPUART1_DMA_RX_IRQHandler(void)
  637. {
  638. /* enter interrupt */
  639. rt_interrupt_enter();
  640. HAL_DMA_IRQHandler(&uart_obj[LPUART1_INDEX].dma_rx.handle);
  641. /* leave interrupt */
  642. rt_interrupt_leave();
  643. }
  644. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA) */
  645. #endif /* BSP_USING_LPUART1*/
  646. static void stm32_uart_get_dma_config(void)
  647. {
  648. #ifdef BSP_USING_UART1
  649. uart_obj[UART1_INDEX].uart_dma_flag = 0;
  650. #ifdef BSP_UART1_RX_USING_DMA
  651. uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  652. static struct dma_config uart1_dma_rx = UART1_DMA_RX_CONFIG;
  653. uart_config[UART1_INDEX].dma_rx = &uart1_dma_rx;
  654. #endif
  655. #ifdef BSP_UART1_TX_USING_DMA
  656. uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  657. static struct dma_config uart1_dma_tx = UART1_DMA_TX_CONFIG;
  658. uart_config[UART1_INDEX].dma_tx = &uart1_dma_tx;
  659. #endif
  660. #endif
  661. #ifdef BSP_USING_UART2
  662. uart_obj[UART2_INDEX].uart_dma_flag = 0;
  663. #ifdef BSP_UART2_RX_USING_DMA
  664. uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  665. static struct dma_config uart2_dma_rx = UART2_DMA_RX_CONFIG;
  666. uart_config[UART2_INDEX].dma_rx = &uart2_dma_rx;
  667. #endif
  668. #ifdef BSP_UART2_TX_USING_DMA
  669. uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  670. static struct dma_config uart2_dma_tx = UART2_DMA_TX_CONFIG;
  671. uart_config[UART2_INDEX].dma_tx = &uart2_dma_tx;
  672. #endif
  673. #endif
  674. #ifdef BSP_USING_UART3
  675. uart_obj[UART3_INDEX].uart_dma_flag = 0;
  676. #ifdef BSP_UART3_RX_USING_DMA
  677. uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  678. static struct dma_config uart3_dma_rx = UART3_DMA_RX_CONFIG;
  679. uart_config[UART3_INDEX].dma_rx = &uart3_dma_rx;
  680. #endif
  681. #ifdef BSP_UART3_TX_USING_DMA
  682. uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  683. static struct dma_config uart3_dma_tx = UART3_DMA_TX_CONFIG;
  684. uart_config[UART3_INDEX].dma_tx = &uart3_dma_tx;
  685. #endif
  686. #endif
  687. #ifdef BSP_USING_UART4
  688. uart_obj[UART4_INDEX].uart_dma_flag = 0;
  689. #ifdef BSP_UART4_RX_USING_DMA
  690. uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  691. static struct dma_config uart4_dma_rx = UART4_DMA_RX_CONFIG;
  692. uart_config[UART4_INDEX].dma_rx = &uart4_dma_rx;
  693. #endif
  694. #ifdef BSP_UART4_TX_USING_DMA
  695. uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  696. static struct dma_config uart4_dma_tx = UART4_DMA_TX_CONFIG;
  697. uart_config[UART4_INDEX].dma_tx = &uart4_dma_tx;
  698. #endif
  699. #endif
  700. #ifdef BSP_USING_UART5
  701. uart_obj[UART5_INDEX].uart_dma_flag = 0;
  702. #ifdef BSP_UART5_RX_USING_DMA
  703. uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  704. static struct dma_config uart5_dma_rx = UART5_DMA_RX_CONFIG;
  705. uart_config[UART5_INDEX].dma_rx = &uart5_dma_rx;
  706. #endif
  707. #ifdef BSP_UART5_TX_USING_DMA
  708. uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  709. static struct dma_config uart5_dma_tx = UART5_DMA_TX_CONFIG;
  710. uart_config[UART5_INDEX].dma_tx = &uart5_dma_tx;
  711. #endif
  712. #endif
  713. #ifdef BSP_USING_UART6
  714. uart_obj[UART6_INDEX].uart_dma_flag = 0;
  715. #ifdef BSP_UART6_RX_USING_DMA
  716. uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  717. static struct dma_config uart6_dma_rx = UART6_DMA_RX_CONFIG;
  718. uart_config[UART6_INDEX].dma_rx = &uart6_dma_rx;
  719. #endif
  720. #ifdef BSP_UART6_TX_USING_DMA
  721. uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  722. static struct dma_config uart6_dma_tx = UART6_DMA_TX_CONFIG;
  723. uart_config[UART6_INDEX].dma_tx = &uart6_dma_tx;
  724. #endif
  725. #endif
  726. }
  727. #ifdef RT_SERIAL_USING_DMA
  728. static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
  729. {
  730. struct rt_serial_rx_fifo *rx_fifo;
  731. DMA_HandleTypeDef *DMA_Handle;
  732. struct dma_config *dma_config;
  733. struct stm32_uart *uart;
  734. RT_ASSERT(serial != RT_NULL);
  735. uart = rt_container_of(serial, struct stm32_uart, serial);
  736. if (RT_DEVICE_FLAG_DMA_RX == flag)
  737. {
  738. DMA_Handle = &uart->dma_rx.handle;
  739. dma_config = uart->config->dma_rx;
  740. }
  741. else if (RT_DEVICE_FLAG_DMA_TX == flag)
  742. {
  743. DMA_Handle = &uart->dma_tx.handle;
  744. dma_config = uart->config->dma_tx;
  745. }
  746. LOG_D("%s dma config start", uart->config->name);
  747. {
  748. rt_uint32_t tmpreg = 0x00U;
  749. #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) \
  750. || defined(SOC_SERIES_STM32L0)
  751. /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
  752. SET_BIT(RCC->AHBENR, dma_config->dma_rcc);
  753. tmpreg = READ_BIT(RCC->AHBENR, dma_config->dma_rcc);
  754. #elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) \
  755. || defined(SOC_SERIES_STM32G4)
  756. /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
  757. SET_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
  758. tmpreg = READ_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
  759. #if (defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G4)) && defined(DMAMUX1)
  760. /* enable DMAMUX clock for L4+ and G4 */
  761. __HAL_RCC_DMAMUX1_CLK_ENABLE();
  762. #endif
  763. #endif
  764. UNUSED(tmpreg); /* To avoid compiler warnings */
  765. }
  766. if (RT_DEVICE_FLAG_DMA_RX == flag)
  767. {
  768. __HAL_LINKDMA(&(uart->handle), hdmarx, uart->dma_rx.handle);
  769. }
  770. else if (RT_DEVICE_FLAG_DMA_TX == flag)
  771. {
  772. __HAL_LINKDMA(&(uart->handle), hdmatx, uart->dma_tx.handle);
  773. }
  774. #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32L0)
  775. DMA_Handle->Instance = dma_config->Instance;
  776. #elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
  777. DMA_Handle->Instance = dma_config->Instance;
  778. DMA_Handle->Init.Channel = dma_config->channel;
  779. #elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)
  780. DMA_Handle->Instance = dma_config->Instance;
  781. DMA_Handle->Init.Request = dma_config->request;
  782. #endif
  783. DMA_Handle->Init.PeriphInc = DMA_PINC_DISABLE;
  784. DMA_Handle->Init.MemInc = DMA_MINC_ENABLE;
  785. DMA_Handle->Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
  786. DMA_Handle->Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
  787. if (RT_DEVICE_FLAG_DMA_RX == flag)
  788. {
  789. DMA_Handle->Init.Direction = DMA_PERIPH_TO_MEMORY;
  790. DMA_Handle->Init.Mode = DMA_CIRCULAR;
  791. }
  792. else if (RT_DEVICE_FLAG_DMA_TX == flag)
  793. {
  794. DMA_Handle->Init.Direction = DMA_MEMORY_TO_PERIPH;
  795. DMA_Handle->Init.Mode = DMA_NORMAL;
  796. }
  797. DMA_Handle->Init.Priority = DMA_PRIORITY_MEDIUM;
  798. #if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
  799. DMA_Handle->Init.FIFOMode = DMA_FIFOMODE_DISABLE;
  800. #endif
  801. if (HAL_DMA_DeInit(DMA_Handle) != HAL_OK)
  802. {
  803. RT_ASSERT(0);
  804. }
  805. if (HAL_DMA_Init(DMA_Handle) != HAL_OK)
  806. {
  807. RT_ASSERT(0);
  808. }
  809. /* enable interrupt */
  810. if (flag == RT_DEVICE_FLAG_DMA_RX)
  811. {
  812. rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
  813. /* Start DMA transfer */
  814. if (HAL_UART_Receive_DMA(&(uart->handle), rx_fifo->buffer, serial->config.bufsz) != HAL_OK)
  815. {
  816. /* Transfer error in reception process */
  817. RT_ASSERT(0);
  818. }
  819. CLEAR_BIT(uart->handle.Instance->CR3, USART_CR3_EIE);
  820. __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_IDLE);
  821. }
  822. /* DMA irq should set in DMA TX mode, or HAL_UART_TxCpltCallback function will not be called */
  823. HAL_NVIC_SetPriority(dma_config->dma_irq, 0, 0);
  824. HAL_NVIC_EnableIRQ(dma_config->dma_irq);
  825. HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0);
  826. HAL_NVIC_EnableIRQ(uart->config->irq_type);
  827. LOG_D("%s dma %s instance: %x", uart->config->name, flag == RT_DEVICE_FLAG_DMA_RX ? "RX" : "TX", DMA_Handle->Instance);
  828. LOG_D("%s dma config done", uart->config->name);
  829. }
  830. /**
  831. * @brief UART error callbacks
  832. * @param huart: UART handle
  833. * @note This example shows a simple way to report transfer error, and you can
  834. * add your own implementation.
  835. * @retval None
  836. */
  837. void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
  838. {
  839. RT_ASSERT(huart != NULL);
  840. struct stm32_uart *uart = (struct stm32_uart *)huart;
  841. LOG_D("%s: %s %d\n", __FUNCTION__, uart->config->name, huart->ErrorCode);
  842. UNUSED(uart);
  843. }
  844. /**
  845. * @brief Rx Transfer completed callback
  846. * @param huart: UART handle
  847. * @note This example shows a simple way to report end of DMA Rx transfer, and
  848. * you can add your own implementation.
  849. * @retval None
  850. */
  851. void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
  852. {
  853. struct stm32_uart *uart;
  854. RT_ASSERT(huart != NULL);
  855. uart = (struct stm32_uart *)huart;
  856. dma_isr(&uart->serial);
  857. }
  858. /**
  859. * @brief Rx Half transfer completed callback
  860. * @param huart: UART handle
  861. * @note This example shows a simple way to report end of DMA Rx Half transfer,
  862. * and you can add your own implementation.
  863. * @retval None
  864. */
  865. void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
  866. {
  867. struct stm32_uart *uart;
  868. RT_ASSERT(huart != NULL);
  869. uart = (struct stm32_uart *)huart;
  870. dma_isr(&uart->serial);
  871. }
  872. static void _dma_tx_complete(struct rt_serial_device *serial)
  873. {
  874. struct stm32_uart *uart;
  875. rt_size_t trans_total_index;
  876. rt_base_t level;
  877. RT_ASSERT(serial != RT_NULL);
  878. uart = rt_container_of(serial, struct stm32_uart, serial);
  879. level = rt_hw_interrupt_disable();
  880. trans_total_index = __HAL_DMA_GET_COUNTER(&(uart->dma_tx.handle));
  881. rt_hw_interrupt_enable(level);
  882. if (trans_total_index == 0)
  883. {
  884. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DMADONE);
  885. }
  886. }
  887. /**
  888. * @brief HAL_UART_TxCpltCallback
  889. * @param huart: UART handle
  890. * @note This callback can be called by two functions, first in UART_EndTransmit_IT when
  891. * UART Tx complete and second in UART_DMATransmitCplt function in DMA Circular mode.
  892. * @retval None
  893. */
  894. void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
  895. {
  896. struct stm32_uart *uart;
  897. RT_ASSERT(huart != NULL);
  898. uart = (struct stm32_uart *)huart;
  899. _dma_tx_complete(&uart->serial);
  900. }
  901. #endif /* RT_SERIAL_USING_DMA */
  902. static const struct rt_uart_ops stm32_uart_ops =
  903. {
  904. .configure = stm32_configure,
  905. .control = stm32_control,
  906. .putc = stm32_putc,
  907. .getc = stm32_getc,
  908. .dma_transmit = stm32_dma_transmit
  909. };
  910. int rt_hw_usart_init(void)
  911. {
  912. rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct stm32_uart);
  913. struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
  914. rt_err_t result = 0;
  915. stm32_uart_get_dma_config();
  916. for (int i = 0; i < obj_num; i++)
  917. {
  918. /* init UART object */
  919. uart_obj[i].config = &uart_config[i];
  920. uart_obj[i].serial.ops = &stm32_uart_ops;
  921. uart_obj[i].serial.config = config;
  922. /* register UART device */
  923. result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name,
  924. RT_DEVICE_FLAG_RDWR
  925. | RT_DEVICE_FLAG_INT_RX
  926. | RT_DEVICE_FLAG_INT_TX
  927. | uart_obj[i].uart_dma_flag
  928. , NULL);
  929. RT_ASSERT(result == RT_EOK);
  930. }
  931. return result;
  932. }
  933. #endif /* RT_USING_SERIAL */