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libcpu
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aarch64
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common
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gic
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gic_pl400.h

gic_pl400.h 2.7 KB
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  1. /*
    2. 

  2.  * Copyright (c) 2006-2018, RT-Thread Development Team
    3. 

  3.  *
    4. 

  4.  * SPDX-License-Identifier: Apache-2.0
    5. 

  5.  *
    6. 

  6.  * Change Logs:
    7. 

  7.  * Date           Author       Notes
    8. 

  8.  * 2013-07-20     Bernard      first version
    9. 

  9.  */
    10. 

  10. 

  11. #ifndef __GIC_PL400_H__
    12. 

  12. #define __GIC_PL400_H__
    13. 

  13. 

  14. #include <rthw.h>
    15. 

  15. #include <board.h>
    16. 

  16. 

  17. #define __REG32(x) (*((volatile unsigned int*)((rt_uint64_t)x)))
    18. 

  18. 

  19. #define GIC_CPU_CTRL(hw_base)               __REG32((hw_base) + 0x00)
    20. 

  20. #define GIC_CPU_PRIMASK(hw_base)            __REG32((hw_base) + 0x04)
    21. 

  21. #define GIC_CPU_BINPOINT(hw_base)           __REG32((hw_base) + 0x08)
    22. 

  22. #define GIC_CPU_INTACK(hw_base)             __REG32((hw_base) + 0x0c)
    23. 

  23. #define GIC_CPU_EOI(hw_base)                __REG32((hw_base) + 0x10)
    24. 

  24. #define GIC_CPU_RUNNINGPRI(hw_base)         __REG32((hw_base) + 0x14)
    25. 

  25. #define GIC_CPU_HIGHPRI(hw_base)            __REG32((hw_base) + 0x18)
    26. 

  26. 

  27. #define GIC_DIST_CTRL(hw_base)              __REG32((hw_base) + 0x000)
    28. 

  28. #define GIC_DIST_TYPE(hw_base)              __REG32((hw_base) + 0x004)
    29. 

  29. #define GIC_DIST_IGROUP(hw_base, n)         __REG32((hw_base) + 0x080 + ((n)/32) * 4)
    30. 

  30. #define GIC_DIST_ENABLE_SET(hw_base, n)     __REG32((hw_base) + 0x100 + ((n)/32) * 4)
    31. 

  31. #define GIC_DIST_ENABLE_CLEAR(hw_base, n)   __REG32((hw_base) + 0x180 + ((n)/32) * 4)
    32. 

  32. #define GIC_DIST_PENDING_SET(hw_base, n)    __REG32((hw_base) + 0x200 + ((n)/32) * 4)
    33. 

  33. #define GIC_DIST_PENDING_CLEAR(hw_base, n)  __REG32((hw_base) + 0x280 + ((n)/32) * 4)
    34. 

  34. #define GIC_DIST_ACTIVE_SET(hw_base, n)     __REG32((hw_base) + 0x300 + ((n)/32) * 4)
    35. 

  35. #define GIC_DIST_ACTIVE_CLEAR(hw_base, n)   __REG32((hw_base) + 0x380 + ((n)/32) * 4)
    36. 

  36. #define GIC_DIST_PRI(hw_base, n)            __REG32((hw_base) + 0x400 +  ((n)/4) * 4)
    37. 

  37. #define GIC_DIST_TARGET(hw_base, n)         __REG32((hw_base) + 0x800 +  ((n)/4) * 4)
    38. 

  38. #define GIC_DIST_CONFIG(hw_base, n)         __REG32((hw_base) + 0xc00 + ((n)/16) * 4)
    39. 

  39. #define GIC_DIST_SOFTINT(hw_base)           __REG32((hw_base) + 0xf00)
    40. 

  40. #define GIC_DIST_CPENDSGI(hw_base, n)       __REG32((hw_base) + 0xf10 + ((n)/4) * 4)
    41. 

  41. #define GIC_DIST_ICPIDR2(hw_base)           __REG32((hw_base) + 0xfe8)
    42. 

  42. 

  43. int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start);
    44. 

  44. int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base);
    45. 

  45. 

  46. void arm_gic_mask(rt_uint32_t index, int irq);
    47. 

  47. void arm_gic_umask(rt_uint32_t index, int irq);
    48. 

  48. void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask);
    49. 

  49. void arm_gic_set_group(rt_uint32_t index, int vector, int group);
    50. 

  50. 

  51. int arm_gic_get_active_irq(rt_uint32_t index);
    52. 

  52. void arm_gic_ack(rt_uint32_t index, int irq);
    53. 

  53. 

  54. void arm_gic_clear_active(rt_uint32_t index, int irq);
    55. 

  55. void arm_gic_clear_pending(rt_uint32_t index, int irq);
    56. 

  56. 

  57. void arm_gic_dump_type(rt_uint32_t index);
    58. 

  58. void arm_gic_dump(rt_uint32_t index);
    59. 

  59. 

  60. #endif
    61. 

  61.