s3cmci.c 6.7 KB

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  1. /*
  2. * Copyright (c) 2006-2018, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2020-04-15 Jonne first version for s3c2440 mmc controller
  9. */
  10. #include <rthw.h>
  11. #include <rtthread.h>
  12. #include <rtdevice.h>
  13. #include <drivers/mmcsd_core.h>
  14. #include <s3c24x0.h>
  15. #define S3C_PCLK 50000000
  16. static void s3c_mmc_set_clk(struct rt_mmcsd_host *host, rt_uint32_t clock)
  17. {
  18. rt_uint32_t prescale;
  19. rt_uint32_t realClk;
  20. for(prescale = 0; prescale < 256; ++prescale)
  21. {
  22. realClk = S3C_PCLK / (1 + prescale);
  23. if(realClk <= clock)
  24. {
  25. break;
  26. }
  27. }
  28. SDIPRE = prescale;
  29. host->io_cfg.clock = realClk;
  30. }
  31. static rt_uint32_t s3c_mmc_send_cmd(struct rt_mmcsd_host *host, struct rt_mmcsd_cmd *cmd)
  32. {
  33. rt_uint32_t ccon;
  34. rt_uint32_t cmdSta;
  35. SDICARG = cmd->arg;
  36. ccon = cmd->cmd_code & 0x3f;
  37. ccon |= (0 << 7) | (1 << 6); /* two start bits*/
  38. ccon |= (1 << 8);/* command start*/
  39. if(cmd->flags & 0xF)
  40. {
  41. // Need response
  42. ccon |= (1 << 9);
  43. }
  44. if((cmd->flags & 0xF) == RESP_R2)
  45. {
  46. // R2 need 136bit response
  47. ccon |= (1 << 10);
  48. }
  49. SDICCON = ccon; /* start cmd */
  50. if(cmd->flags & 0xF)
  51. {
  52. cmdSta = SDICSTA;
  53. while((cmdSta & 0x200) != 0x200 && (cmdSta & 0x400) != 0x400)
  54. {
  55. cmdSta = SDICSTA;
  56. }
  57. if((cmdSta & 0x1000) == 0x1000 && (cmd->flags & 0xF) != RESP_R3 && (cmd->flags & 0xF) != RESP_R4)
  58. {
  59. // crc error, but R3 R4 ignore it
  60. SDICSTA = cmdSta;
  61. return -RT_ERROR;
  62. }
  63. if((cmdSta & 0xF00) != 0xa00)
  64. {
  65. SDICSTA = cmdSta;
  66. return -RT_ERROR;
  67. }
  68. cmd->resp[0] = SDIRSP0;
  69. if((cmd->flags & 0xF) == RESP_R2)
  70. {
  71. cmd->resp[1] = SDIRSP1;
  72. cmd->resp[2] = SDIRSP2;
  73. cmd->resp[3] = SDIRSP3;
  74. }
  75. }
  76. else
  77. {
  78. cmdSta = SDICSTA;
  79. while((cmdSta & 0x800) != 0x800)
  80. {
  81. cmdSta = SDICSTA;
  82. }
  83. }
  84. SDICSTA = cmdSta; // clear current status
  85. return RT_EOK;
  86. }
  87. static rt_uint32_t s3c_mmc_xfer_data(struct rt_mmcsd_data *data)
  88. {
  89. rt_uint32_t status;
  90. rt_uint32_t xfer_size;
  91. rt_uint32_t handled_size = 0;
  92. rt_uint32_t *pBuf = RT_NULL;
  93. if(data == RT_NULL)
  94. {
  95. return -RT_ERROR;
  96. }
  97. xfer_size = data->blks * data->blksize;
  98. pBuf = data->buf;
  99. if(data->flags & DATA_DIR_READ)
  100. {
  101. while(handled_size < xfer_size)
  102. {
  103. if ((SDIDSTA & 0x20) == 0x20)
  104. {
  105. SDIDSTA = (0x1 << 0x5);
  106. break;
  107. }
  108. status = SDIFSTA;
  109. if ((status & 0x1000) == 0x1000)
  110. {
  111. *pBuf++ = SDIDAT;
  112. handled_size += 4;
  113. }
  114. }
  115. }
  116. else
  117. {
  118. while(handled_size < xfer_size)
  119. {
  120. status = SDIFSTA;
  121. if ((status & 0x2000) == 0x2000)
  122. {
  123. SDIDAT = *pBuf++;
  124. handled_size += 4;
  125. }
  126. }
  127. }
  128. // wait for end
  129. status = SDIDSTA;
  130. while((status & 0x30) == 0)
  131. {
  132. status = SDIDSTA;
  133. }
  134. SDIDSTA = status;
  135. if ((status & 0xfc) != 0x10)
  136. {
  137. return -RT_ERROR;
  138. }
  139. SDIDCON = SDIDCON & ~(7<<12);
  140. SDIFSTA = SDIFSTA & 0x200;
  141. SDIDSTA = 0x10;
  142. return RT_EOK;
  143. }
  144. static void mmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
  145. {
  146. rt_uint32_t ret;
  147. struct rt_mmcsd_cmd *cmd;
  148. struct rt_mmcsd_data *data;
  149. rt_uint32_t val;
  150. rt_uint32_t tryCnt = 0;
  151. if(req->cmd == RT_NULL)
  152. {
  153. goto out;
  154. }
  155. cmd = req->cmd;
  156. /* prepare for data transfer*/
  157. if(req->data != RT_NULL)
  158. {
  159. SDIFSTA = SDIFSTA | (1<<16); // reset fifo
  160. while(SDIDSTA & 0x03)
  161. {
  162. if(tryCnt++ > 500)
  163. {
  164. break;
  165. SDIDSTA = SDIDSTA;
  166. }
  167. }
  168. data = req->data;
  169. if((data->blksize & 0x3) != 0)
  170. {
  171. goto out;
  172. }
  173. val = (2 << 22) //word transfer
  174. | (1 << 20) // transmet after response
  175. | (1 << 19) // reciveve after command sent
  176. | (1 << 17) // block data transfer
  177. | (1 << 14); // data start
  178. if(host->io_cfg.bus_width == MMCSD_BUS_WIDTH_4)
  179. {
  180. val |= (1 << 16); // wide bus mode(4bit data)
  181. }
  182. if(data->flags & DATA_DIR_READ)
  183. {
  184. // for data read
  185. val |= (2 << 12);
  186. }
  187. else
  188. {
  189. val |= (3 << 12);
  190. }
  191. val |= (data->blks & 0xFFF);
  192. SDIDCON = val;
  193. SDIBSIZE = data->blksize;
  194. SDIDTIMER = 0x7fffff;
  195. }
  196. ret = s3c_mmc_send_cmd(host,req->cmd);
  197. if(ret != RT_EOK) {
  198. cmd->err = ret;
  199. goto out;
  200. }
  201. if(req->data != RT_NULL)
  202. {
  203. /*do transfer data*/
  204. ret = s3c_mmc_xfer_data(data);
  205. if(ret != RT_EOK)
  206. {
  207. data->err = ret;
  208. goto out;
  209. }
  210. }
  211. out:
  212. mmcsd_req_complete(host);
  213. }
  214. static void mmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
  215. {
  216. switch (io_cfg->power_mode) {
  217. case MMCSD_POWER_ON:
  218. case MMCSD_POWER_UP:
  219. /* Enable PCLK into SDI Block */
  220. CLKCON |= 1 << 9;
  221. /* Setup GPIO as SD and SDCMD, SDDAT[3:0] Pull up En */
  222. GPEUP = GPEUP & (~(0x3f << 5)) | (0x01 << 5);
  223. GPECON = GPECON & (~(0xfff << 10)) | (0xaaa << 10);
  224. break;
  225. case MMCSD_POWER_OFF:
  226. default:
  227. break;
  228. }
  229. s3c_mmc_set_clk(host, io_cfg->clock);
  230. SDICON = 1;
  231. }
  232. static rt_int32_t mmc_get_card_status(struct rt_mmcsd_host *host)
  233. {
  234. return RT_EOK;
  235. }
  236. static void mmc_enable_sdio_irq(struct rt_mmcsd_host *host, rt_int32_t en)
  237. {
  238. }
  239. static const struct rt_mmcsd_host_ops ops =
  240. {
  241. mmc_request,
  242. mmc_set_iocfg,
  243. mmc_get_card_status,
  244. mmc_enable_sdio_irq
  245. };
  246. int s3c_sdio_init(void)
  247. {
  248. struct rt_mmcsd_host * host = RT_NULL;
  249. host = mmcsd_alloc_host();
  250. if (!host)
  251. {
  252. goto err;
  253. }
  254. host->ops = &ops;
  255. host->freq_min = 300000;
  256. host->freq_max = 50000000;
  257. host->valid_ocr = VDD_32_33 | VDD_33_34;
  258. host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ | MMCSD_BUSWIDTH_4;
  259. host->max_seg_size = 2048;
  260. host->max_dma_segs = 10;
  261. host->max_blk_size = 512;
  262. host->max_blk_count = 4096;
  263. mmcsd_change(host);
  264. return RT_EOK;
  265. err:
  266. if(host) rt_free(host);
  267. return -RT_EIO;
  268. }
  269. INIT_DEVICE_EXPORT(s3c_sdio_init);