drv_cache.c 1.2 KB

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  1. /*
  2. * Copyright (c) 2006-2018, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-04-02 tanek first implementation
  9. */
  10. #include <rtthread.h>
  11. #include <rthw.h>
  12. #include <fsl_cache.h>
  13. void rt_hw_cpu_icache_enable(void)
  14. {
  15. SCB_EnableICache();
  16. }
  17. void rt_hw_cpu_icache_disable(void)
  18. {
  19. SCB_DisableICache();
  20. }
  21. rt_base_t rt_hw_cpu_icache_status(void)
  22. {
  23. return 0;
  24. }
  25. void rt_hw_cpu_icache_ops(int ops, void* addr, int size)
  26. {
  27. if (ops & RT_HW_CACHE_INVALIDATE)
  28. {
  29. ICACHE_InvalidateByRange((uint32_t)addr, size);
  30. }
  31. }
  32. void rt_hw_cpu_dcache_enable(void)
  33. {
  34. SCB_EnableDCache();
  35. }
  36. void rt_hw_cpu_dcache_disable(void)
  37. {
  38. SCB_DisableDCache();
  39. }
  40. rt_base_t rt_hw_cpu_dcache_status(void)
  41. {
  42. return 0;
  43. }
  44. void rt_hw_cpu_dcache_ops(int ops, void* addr, int size)
  45. {
  46. if (ops & (RT_HW_CACHE_FLUSH | RT_HW_CACHE_INVALIDATE))
  47. {
  48. DCACHE_CleanInvalidateByRange((uint32_t)addr, size);
  49. }
  50. else if (ops & RT_HW_CACHE_FLUSH)
  51. {
  52. DCACHE_CleanByRange((uint32_t)addr, size);
  53. }
  54. else if (ops & RT_HW_CACHE_INVALIDATE)
  55. {
  56. DCACHE_InvalidateByRange((uint32_t)addr, size);
  57. }
  58. else
  59. {
  60. RT_ASSERT(0);
  61. }
  62. }