drv_pin.c 21 KB

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  1. /*
  2. * Copyright (c) 2006-2018, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-03-13 Liuguang the first version.
  9. * 2018-03-19 Liuguang add GPIO interrupt mode support.
  10. */
  11. #include "drv_pin.h"
  12. #include "fsl_common.h"
  13. #include "fsl_iomuxc.h"
  14. #include "fsl_gpio.h"
  15. #ifdef RT_USING_PIN
  16. #if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL
  17. #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!"
  18. #endif
  19. struct rt1052_pin
  20. {
  21. rt_uint16_t pin;
  22. GPIO_Type *gpio;
  23. rt_uint32_t gpio_pin;
  24. };
  25. struct rt1052_irq
  26. {
  27. rt_uint16_t enable;
  28. struct rt_pin_irq_hdr irq_info;
  29. };
  30. #define __ARRAY_LEN(array) (sizeof(array)/sizeof(array[0]))
  31. #define __RT1052_PIN_DEFAULT {0, 0, 0}
  32. #define __RT1052_PIN(INDEX, PORT, PIN) {INDEX, PORT, PIN}
  33. static struct rt_pin_ops rt1052_pin_ops;
  34. static struct rt1052_pin rt1052_pin_map[] =
  35. {
  36. __RT1052_PIN_DEFAULT,
  37. /* GPIO4 */
  38. __RT1052_PIN( 1, GPIO4, 0), /* GPIO_EMC_00 */
  39. __RT1052_PIN( 2, GPIO4, 1), /* GPIO_EMC_01 */
  40. __RT1052_PIN( 3, GPIO4, 2), /* GPIO_EMC_02 */
  41. __RT1052_PIN( 4, GPIO4, 3), /* GPIO_EMC_03 */
  42. __RT1052_PIN( 5, GPIO4, 4), /* GPIO_EMC_04 */
  43. __RT1052_PIN( 6, GPIO4, 5), /* GPIO_EMC_05 */
  44. __RT1052_PIN( 7, GPIO4, 6), /* GPIO_EMC_06 */
  45. __RT1052_PIN( 8, GPIO4, 7), /* GPIO_EMC_07 */
  46. __RT1052_PIN( 9, GPIO4, 8), /* GPIO_EMC_08 */
  47. __RT1052_PIN(10, GPIO4, 9), /* GPIO_EMC_09 */
  48. __RT1052_PIN(11, GPIO4, 10), /* GPIO_EMC_10 */
  49. __RT1052_PIN(12, GPIO4, 11), /* GPIO_EMC_11 */
  50. __RT1052_PIN(13, GPIO4, 12), /* GPIO_EMC_12 */
  51. __RT1052_PIN(14, GPIO4, 13), /* GPIO_EMC_13 */
  52. __RT1052_PIN(15, GPIO4, 14), /* GPIO_EMC_14 */
  53. __RT1052_PIN(16, GPIO4, 15), /* GPIO_EMC_15 */
  54. __RT1052_PIN(17, GPIO4, 16), /* GPIO_EMC_16 */
  55. __RT1052_PIN(18, GPIO4, 17), /* GPIO_EMC_17 */
  56. __RT1052_PIN(19, GPIO4, 18), /* GPIO_EMC_18 */
  57. __RT1052_PIN(20, GPIO4, 19), /* GPIO_EMC_19 */
  58. __RT1052_PIN(21, GPIO4, 20), /* GPIO_EMC_20 */
  59. __RT1052_PIN(22, GPIO4, 21), /* GPIO_EMC_21 */
  60. __RT1052_PIN(23, GPIO4, 22), /* GPIO_EMC_22 */
  61. __RT1052_PIN(24, GPIO4, 23), /* GPIO_EMC_23 */
  62. __RT1052_PIN(25, GPIO4, 24), /* GPIO_EMC_24 */
  63. __RT1052_PIN(26, GPIO4, 25), /* GPIO_EMC_25 */
  64. __RT1052_PIN(27, GPIO4, 26), /* GPIO_EMC_26 */
  65. __RT1052_PIN(28, GPIO4, 27), /* GPIO_EMC_27 */
  66. __RT1052_PIN(29, GPIO4, 28), /* GPIO_EMC_28 */
  67. __RT1052_PIN(30, GPIO4, 29), /* GPIO_EMC_29 */
  68. __RT1052_PIN(31, GPIO4, 30), /* GPIO_EMC_30 */
  69. __RT1052_PIN(32, GPIO4, 31), /* GPIO_EMC_31 */
  70. __RT1052_PIN(33, GPIO3, 18), /* GPIO_EMC_32 */
  71. __RT1052_PIN(34, GPIO3, 19), /* GPIO_EMC_33 */
  72. __RT1052_PIN(35, GPIO3, 20), /* GPIO_EMC_34 */
  73. __RT1052_PIN(36, GPIO3, 21), /* GPIO_EMC_35 */
  74. __RT1052_PIN(37, GPIO3, 22), /* GPIO_EMC_36 */
  75. __RT1052_PIN(38, GPIO3, 23), /* GPIO_EMC_37 */
  76. __RT1052_PIN(39, GPIO3, 24), /* GPIO_EMC_38 */
  77. __RT1052_PIN(40, GPIO3, 25), /* GPIO_EMC_39 */
  78. __RT1052_PIN(41, GPIO3, 26), /* GPIO_EMC_40 */
  79. __RT1052_PIN(42, GPIO3, 27), /* GPIO_EMC_41 */
  80. /* GPIO1 */
  81. __RT1052_PIN(43, GPIO1, 0), /* GPIO_AD_B0_00 */
  82. __RT1052_PIN(44, GPIO1, 1), /* GPIO_AD_B0_01 */
  83. __RT1052_PIN(45, GPIO1, 2), /* GPIO_AD_B0_02 */
  84. __RT1052_PIN(46, GPIO1, 3), /* GPIO_AD_B0_03 */
  85. __RT1052_PIN(47, GPIO1, 4), /* GPIO_AD_B0_04 */
  86. __RT1052_PIN(48, GPIO1, 5), /* GPIO_AD_B0_05 */
  87. __RT1052_PIN(49, GPIO1, 6), /* GPIO_AD_B0_06 */
  88. __RT1052_PIN(50, GPIO1, 7), /* GPIO_AD_B0_07 */
  89. __RT1052_PIN(51, GPIO1, 8), /* GPIO_AD_B0_08 */
  90. __RT1052_PIN(52, GPIO1, 9), /* GPIO_AD_B0_09 */
  91. __RT1052_PIN(53, GPIO1, 10), /* GPIO_AD_B0_10 */
  92. __RT1052_PIN(54, GPIO1, 11), /* GPIO_AD_B0_11 */
  93. __RT1052_PIN(55, GPIO1, 12), /* GPIO_AD_B0_12 */
  94. __RT1052_PIN(56, GPIO1, 13), /* GPIO_AD_B0_13 */
  95. __RT1052_PIN(57, GPIO1, 14), /* GPIO_AD_B0_14 */
  96. __RT1052_PIN(58, GPIO1, 15), /* GPIO_AD_B0_15 */
  97. __RT1052_PIN(59, GPIO1, 16), /* GPIO_AD_B1_00 */
  98. __RT1052_PIN(60, GPIO1, 17), /* GPIO_AD_B1_01 */
  99. __RT1052_PIN(61, GPIO1, 18), /* GPIO_AD_B1_02 */
  100. __RT1052_PIN(62, GPIO1, 19), /* GPIO_AD_B1_03 */
  101. __RT1052_PIN(63, GPIO1, 20), /* GPIO_AD_B1_04 */
  102. __RT1052_PIN(64, GPIO1, 21), /* GPIO_AD_B1_05 */
  103. __RT1052_PIN(65, GPIO1, 22), /* GPIO_AD_B1_06 */
  104. __RT1052_PIN(66, GPIO1, 23), /* GPIO_AD_B1_07 */
  105. __RT1052_PIN(67, GPIO1, 24), /* GPIO_AD_B1_08 */
  106. __RT1052_PIN(68, GPIO1, 25), /* GPIO_AD_B1_09 */
  107. __RT1052_PIN(69, GPIO1, 26), /* GPIO_AD_B1_10 */
  108. __RT1052_PIN(70, GPIO1, 27), /* GPIO_AD_B1_11 */
  109. __RT1052_PIN(71, GPIO1, 28), /* GPIO_AD_B1_12 */
  110. __RT1052_PIN(72, GPIO1, 29), /* GPIO_AD_B1_13 */
  111. __RT1052_PIN(73, GPIO1, 30), /* GPIO_AD_B1_14 */
  112. __RT1052_PIN(74, GPIO1, 31), /* GPIO_AD_B1_15 */
  113. /* GPIO2 */
  114. __RT1052_PIN( 75, GPIO2, 0), /* GPIO_B0_00 */
  115. __RT1052_PIN( 76, GPIO2, 1), /* GPIO_B0_01 */
  116. __RT1052_PIN( 77, GPIO2, 2), /* GPIO_B0_02 */
  117. __RT1052_PIN( 78, GPIO2, 3), /* GPIO_B0_03 */
  118. __RT1052_PIN( 79, GPIO2, 4), /* GPIO_B0_04 */
  119. __RT1052_PIN( 80, GPIO2, 5), /* GPIO_B0_05 */
  120. __RT1052_PIN( 81, GPIO2, 6), /* GPIO_B0_06 */
  121. __RT1052_PIN( 82, GPIO2, 7), /* GPIO_B0_07 */
  122. __RT1052_PIN( 83, GPIO2, 8), /* GPIO_B0_08 */
  123. __RT1052_PIN( 84, GPIO2, 9), /* GPIO_B0_09 */
  124. __RT1052_PIN( 85, GPIO2, 10), /* GPIO_B0_10 */
  125. __RT1052_PIN( 86, GPIO2, 11), /* GPIO_B0_11 */
  126. __RT1052_PIN( 87, GPIO2, 12), /* GPIO_B0_12 */
  127. __RT1052_PIN( 88, GPIO2, 13), /* GPIO_B0_13 */
  128. __RT1052_PIN( 89, GPIO2, 14), /* GPIO_B0_14 */
  129. __RT1052_PIN( 90, GPIO2, 15), /* GPIO_B0_15 */
  130. __RT1052_PIN( 91, GPIO2, 16), /* GPIO_B1_00 */
  131. __RT1052_PIN( 92, GPIO2, 17), /* GPIO_B1_01 */
  132. __RT1052_PIN( 93, GPIO2, 18), /* GPIO_B1_02 */
  133. __RT1052_PIN( 94, GPIO2, 19), /* GPIO_B1_03 */
  134. __RT1052_PIN( 95, GPIO2, 20), /* GPIO_B1_04 */
  135. __RT1052_PIN( 96, GPIO2, 21), /* GPIO_B1_05 */
  136. __RT1052_PIN( 97, GPIO2, 22), /* GPIO_B1_06 */
  137. __RT1052_PIN( 98, GPIO2, 23), /* GPIO_B1_07 */
  138. __RT1052_PIN( 99, GPIO2, 24), /* GPIO_B1_08 */
  139. __RT1052_PIN(100, GPIO2, 25), /* GPIO_B1_09 */
  140. __RT1052_PIN(101, GPIO2, 26), /* GPIO_B1_10 */
  141. __RT1052_PIN(102, GPIO2, 27), /* GPIO_B1_11 */
  142. __RT1052_PIN(103, GPIO2, 28), /* GPIO_B1_12 */
  143. __RT1052_PIN(104, GPIO2, 29), /* GPIO_B1_13 */
  144. __RT1052_PIN(105, GPIO2, 30), /* GPIO_B1_14 */
  145. __RT1052_PIN(106, GPIO2, 31), /* GPIO_B1_15 */
  146. /* GPIO3 */
  147. __RT1052_PIN(107, GPIO3, 0), /* GPIO_SD_B1_00 */
  148. __RT1052_PIN(108, GPIO3, 1), /* GPIO_SD_B1_01 */
  149. __RT1052_PIN(109, GPIO3, 2), /* GPIO_SD_B1_02 */
  150. __RT1052_PIN(110, GPIO3, 3), /* GPIO_SD_B1_03 */
  151. __RT1052_PIN(111, GPIO3, 4), /* GPIO_SD_B1_04 */
  152. __RT1052_PIN(112, GPIO3, 5), /* GPIO_SD_B1_05 */
  153. __RT1052_PIN(113, GPIO3, 6), /* GPIO_SD_B1_06 */
  154. __RT1052_PIN(114, GPIO3, 7), /* GPIO_SD_B1_07 */
  155. __RT1052_PIN(115, GPIO3, 8), /* GPIO_SD_B1_08 */
  156. __RT1052_PIN(116, GPIO3, 9), /* GPIO_SD_B1_09 */
  157. __RT1052_PIN(117, GPIO3, 10), /* GPIO_SD_B1_10 */
  158. __RT1052_PIN(118, GPIO3, 11), /* GPIO_SD_B1_11 */
  159. __RT1052_PIN(119, GPIO3, 12), /* GPIO_SD_B0_00 */
  160. __RT1052_PIN(120, GPIO3, 13), /* GPIO_SD_B0_01 */
  161. __RT1052_PIN(121, GPIO3, 14), /* GPIO_SD_B0_02 */
  162. __RT1052_PIN(122, GPIO3, 15), /* GPIO_SD_B0_03 */
  163. __RT1052_PIN(123, GPIO3, 16), /* GPIO_SD_B0_04 */
  164. __RT1052_PIN(124, GPIO3, 17), /* GPIO_SD_B0_05 */
  165. /* GPIO5 */
  166. __RT1052_PIN(125, GPIO5, 0), /* WAKEUP */
  167. __RT1052_PIN(126, GPIO5, 1), /* PMIC_ON_REQ */
  168. __RT1052_PIN(127, GPIO5, 2) /* PMIC_STBY_REQ */
  169. };
  170. static struct rt1052_irq rt1052_irq_map[] =
  171. {
  172. {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
  173. {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
  174. {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
  175. {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
  176. {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
  177. {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
  178. {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
  179. {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
  180. {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
  181. {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
  182. {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
  183. {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
  184. {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
  185. {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
  186. {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
  187. {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
  188. {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
  189. {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
  190. {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
  191. {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
  192. {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
  193. {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
  194. {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
  195. {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
  196. {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
  197. {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
  198. {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
  199. {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
  200. {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
  201. {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
  202. {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
  203. {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }
  204. };
  205. void gpio_isr(GPIO_Type* base, rt_uint32_t gpio_pin)
  206. {
  207. if((GPIO_PortGetInterruptFlags(base) & (1 << gpio_pin)) != 0)
  208. {
  209. GPIO_PortClearInterruptFlags(base, gpio_pin);
  210. if(rt1052_irq_map[gpio_pin].irq_info.hdr != RT_NULL)
  211. {
  212. rt1052_irq_map[gpio_pin].irq_info.hdr(rt1052_irq_map[gpio_pin].irq_info.args);
  213. }
  214. }
  215. }
  216. void GPIO1_Combined_0_15_IRQHandler(void)
  217. {
  218. rt_uint8_t gpio_pin;
  219. rt_interrupt_enter();
  220. for(gpio_pin = 0; gpio_pin <= 15; gpio_pin++)
  221. {
  222. gpio_isr(GPIO1, gpio_pin);
  223. }
  224. rt_interrupt_leave();
  225. }
  226. void GPIO1_Combined_16_31_IRQHandler(void)
  227. {
  228. rt_uint8_t gpio_pin;
  229. rt_interrupt_enter();
  230. for(gpio_pin = 16; gpio_pin <= 31; gpio_pin++)
  231. {
  232. gpio_isr(GPIO1, gpio_pin);
  233. }
  234. rt_interrupt_leave();
  235. }
  236. void GPIO2_Combined_0_15_IRQHandler(void)
  237. {
  238. rt_uint8_t gpio_pin;
  239. rt_interrupt_enter();
  240. for(gpio_pin = 0; gpio_pin <= 15; gpio_pin++)
  241. {
  242. gpio_isr(GPIO2, gpio_pin);
  243. }
  244. rt_interrupt_leave();
  245. }
  246. void GPIO2_Combined_16_31_IRQHandler(void)
  247. {
  248. rt_uint8_t gpio_pin;
  249. rt_interrupt_enter();
  250. for(gpio_pin = 16; gpio_pin <= 31; gpio_pin++)
  251. {
  252. gpio_isr(GPIO2, gpio_pin);
  253. }
  254. rt_interrupt_leave();
  255. }
  256. void GPIO3_Combined_0_15_IRQHandler(void)
  257. {
  258. rt_uint8_t gpio_pin;
  259. rt_interrupt_enter();
  260. for(gpio_pin = 0; gpio_pin <= 15; gpio_pin++)
  261. {
  262. gpio_isr(GPIO3, gpio_pin);
  263. }
  264. rt_interrupt_leave();
  265. }
  266. void GPIO3_Combined_16_31_IRQHandler(void)
  267. {
  268. rt_uint8_t gpio_pin;
  269. rt_interrupt_enter();
  270. for(gpio_pin = 16; gpio_pin <= 31; gpio_pin++)
  271. {
  272. gpio_isr(GPIO3, gpio_pin);
  273. }
  274. rt_interrupt_leave();
  275. }
  276. void GPIO4_Combined_0_15_IRQHandler(void)
  277. {
  278. rt_uint8_t gpio_pin;
  279. rt_interrupt_enter();
  280. for(gpio_pin = 0; gpio_pin <= 15; gpio_pin++)
  281. {
  282. gpio_isr(GPIO4, gpio_pin);
  283. }
  284. rt_interrupt_leave();
  285. }
  286. void GPIO4_Combined_16_31_IRQHandler(void)
  287. {
  288. rt_uint8_t gpio_pin;
  289. rt_interrupt_enter();
  290. for(gpio_pin = 16; gpio_pin <= 31; gpio_pin++)
  291. {
  292. gpio_isr(GPIO4, gpio_pin);
  293. }
  294. rt_interrupt_leave();
  295. }
  296. void GPIO5_Combined_0_15_IRQHandler(void)
  297. {
  298. rt_uint8_t gpio_pin;
  299. rt_interrupt_enter();
  300. for(gpio_pin = 0; gpio_pin <= 2; gpio_pin++)
  301. {
  302. gpio_isr(GPIO5, gpio_pin);
  303. }
  304. rt_interrupt_leave();
  305. }
  306. static IRQn_Type rt1052_get_irqnum(GPIO_Type *gpio, rt_uint32_t gpio_pin)
  307. {
  308. IRQn_Type irq_num = NotAvail_IRQn; /* Invalid interrupt number */
  309. if(gpio == GPIO1)
  310. {
  311. if(gpio_pin <= 15)
  312. {
  313. irq_num = GPIO1_Combined_0_15_IRQn;
  314. }
  315. else
  316. {
  317. irq_num = GPIO1_Combined_16_31_IRQn;
  318. }
  319. }
  320. else if(gpio == GPIO2)
  321. {
  322. if(gpio_pin <= 15)
  323. {
  324. irq_num = GPIO2_Combined_0_15_IRQn;
  325. }
  326. else
  327. {
  328. irq_num = GPIO2_Combined_16_31_IRQn;
  329. }
  330. }
  331. else if(gpio == GPIO3)
  332. {
  333. if(gpio_pin <= 15)
  334. {
  335. irq_num = GPIO3_Combined_0_15_IRQn;
  336. }
  337. else
  338. {
  339. irq_num = GPIO3_Combined_16_31_IRQn;
  340. }
  341. }
  342. else if(gpio == GPIO4)
  343. {
  344. if(gpio_pin <= 15)
  345. {
  346. irq_num = GPIO4_Combined_0_15_IRQn;
  347. }
  348. else
  349. {
  350. irq_num = GPIO4_Combined_16_31_IRQn;
  351. }
  352. }
  353. else if(gpio == GPIO5)
  354. {
  355. if(gpio_pin <= 15)
  356. {
  357. irq_num = GPIO5_Combined_0_15_IRQn;
  358. }
  359. else
  360. {
  361. irq_num = GPIO5_Combined_16_31_IRQn;
  362. }
  363. }
  364. return irq_num;
  365. }
  366. static void rt1052_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
  367. {
  368. gpio_pin_config_t gpio;
  369. rt_uint32_t config_value = 0;
  370. if((pin > __ARRAY_LEN(rt1052_pin_map)) || (pin == 0))
  371. {
  372. return;
  373. }
  374. if(rt1052_pin_map[pin].gpio != GPIO5)
  375. {
  376. CLOCK_EnableClock(kCLOCK_Iomuxc);
  377. IOMUXC_SetPinMux(0x401F8010U + pin*4, 0x5U, 0, 0, 0, 1);
  378. }
  379. else
  380. {
  381. CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
  382. IOMUXC_SetPinMux(0x400A8000U + (pin-125)*4, 0x5U, 0, 0, 0, 1);
  383. }
  384. gpio.outputLogic = 0;
  385. gpio.interruptMode = kGPIO_NoIntmode;
  386. switch(mode)
  387. {
  388. case PIN_MODE_OUTPUT:
  389. {
  390. config_value = 0x1030U;
  391. gpio.direction = kGPIO_DigitalOutput;
  392. }
  393. break;
  394. case PIN_MODE_INPUT:
  395. {
  396. config_value = 0x1030U;
  397. gpio.direction = kGPIO_DigitalInput;
  398. }
  399. break;
  400. case PIN_MODE_INPUT_PULLDOWN:
  401. {
  402. config_value = 0x1030U;
  403. gpio.direction = kGPIO_DigitalInput;
  404. }
  405. break;
  406. case PIN_MODE_INPUT_PULLUP:
  407. {
  408. config_value = 0x5030U;
  409. gpio.direction = kGPIO_DigitalInput;
  410. }
  411. break;
  412. case PIN_MODE_OUTPUT_OD:
  413. {
  414. config_value = 0x1830U;
  415. gpio.direction = kGPIO_DigitalOutput;
  416. }
  417. break;
  418. }
  419. if(rt1052_pin_map[pin].gpio != GPIO5)
  420. {
  421. IOMUXC_SetPinConfig(0, 0, 0, 0, 0x401F8200U + pin*4, config_value);
  422. }
  423. else
  424. {
  425. IOMUXC_SetPinConfig(0, 0, 0, 0, 0x400A8018U + (pin-125)*4, config_value);
  426. }
  427. GPIO_PinInit(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin, &gpio);
  428. }
  429. static int rt1052_pin_read(rt_device_t dev, rt_base_t pin)
  430. {
  431. return GPIO_PinReadPadStatus(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin);
  432. }
  433. static void rt1052_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
  434. {
  435. GPIO_PinWrite(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin, value);
  436. }
  437. static rt_err_t rt1052_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
  438. rt_uint32_t mode, void (*hdr)(void *args), void *args)
  439. {
  440. struct rt1052_pin* pin_map = RT_NULL;
  441. struct rt1052_irq* irq_map = RT_NULL;
  442. pin_map = &rt1052_pin_map[pin];
  443. irq_map = &rt1052_irq_map[rt1052_pin_map[pin].gpio_pin];
  444. if(pin_map == RT_NULL || irq_map == RT_NULL)
  445. {
  446. return RT_ENOSYS;
  447. }
  448. if(irq_map->enable == PIN_IRQ_ENABLE)
  449. {
  450. return RT_EBUSY;
  451. }
  452. irq_map->irq_info.pin = pin;
  453. irq_map->irq_info.hdr = hdr;
  454. irq_map->irq_info.mode = mode;
  455. irq_map->irq_info.args = args;
  456. return RT_EOK;
  457. }
  458. static rt_err_t rt1052_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
  459. {
  460. struct rt1052_pin* pin_map = RT_NULL;
  461. struct rt1052_irq* irq_map = RT_NULL;
  462. pin_map = &rt1052_pin_map[pin];
  463. irq_map = &rt1052_irq_map[rt1052_pin_map[pin].gpio_pin];
  464. if(pin_map == RT_NULL || irq_map == RT_NULL)
  465. {
  466. return RT_ENOSYS;
  467. }
  468. if(irq_map->enable == PIN_IRQ_DISABLE)
  469. {
  470. return RT_EOK;
  471. }
  472. irq_map->irq_info.pin = PIN_IRQ_PIN_NONE;
  473. irq_map->irq_info.hdr = RT_NULL;
  474. irq_map->irq_info.mode = PIN_IRQ_MODE_RISING;
  475. irq_map->irq_info.args = RT_NULL;
  476. return RT_EOK;
  477. }
  478. static rt_err_t rt1052_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
  479. {
  480. gpio_pin_config_t gpio;
  481. IRQn_Type irq_num;
  482. rt_uint32_t config_value = 0x1b0a0;
  483. struct rt1052_pin* pin_map = RT_NULL;
  484. struct rt1052_irq* irq_map = RT_NULL;
  485. pin_map = &rt1052_pin_map[pin];
  486. irq_map = &rt1052_irq_map[rt1052_pin_map[pin].gpio_pin];
  487. if(pin_map == RT_NULL || irq_map == RT_NULL)
  488. {
  489. return RT_ENOSYS;
  490. }
  491. if(enabled == PIN_IRQ_ENABLE)
  492. {
  493. if(irq_map->enable == PIN_IRQ_ENABLE)
  494. {
  495. return RT_EBUSY;
  496. }
  497. if(irq_map->irq_info.pin != pin)
  498. {
  499. return RT_EIO;
  500. }
  501. irq_map->enable = PIN_IRQ_ENABLE;
  502. if(rt1052_pin_map[pin].gpio != GPIO5)
  503. {
  504. CLOCK_EnableClock(kCLOCK_Iomuxc);
  505. IOMUXC_SetPinMux(0x401F8010U + pin*4, 0x5U, 0, 0, 0, 0);
  506. }
  507. else
  508. {
  509. CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
  510. IOMUXC_SetPinMux(0x400A8000U + (pin-125)*4, 0x5U, 0, 0, 0, 0);
  511. }
  512. gpio.direction = kGPIO_DigitalInput;
  513. gpio.outputLogic = 0;
  514. switch(irq_map->irq_info.mode)
  515. {
  516. case PIN_IRQ_MODE_RISING:
  517. {
  518. gpio.interruptMode = kGPIO_IntRisingEdge;
  519. }
  520. break;
  521. case PIN_IRQ_MODE_FALLING:
  522. {
  523. gpio.interruptMode = kGPIO_IntFallingEdge;
  524. }
  525. break;
  526. case PIN_IRQ_MODE_RISING_FALLING:
  527. {
  528. gpio.interruptMode = kGPIO_IntRisingOrFallingEdge;
  529. }
  530. break;
  531. case PIN_IRQ_MODE_HIGH_LEVEL:
  532. {
  533. gpio.interruptMode = kGPIO_IntHighLevel;
  534. }
  535. break;
  536. case PIN_IRQ_MODE_LOW_LEVEL:
  537. {
  538. gpio.interruptMode = kGPIO_IntLowLevel;
  539. }
  540. break;
  541. }
  542. if(rt1052_pin_map[pin].gpio != GPIO5)
  543. {
  544. IOMUXC_SetPinConfig(0, 0, 0, 0, 0x401F8200U + pin*4, config_value);
  545. }
  546. else
  547. {
  548. IOMUXC_SetPinConfig(0, 0, 0, 0, 0x400A8018U + (pin-125)*4, config_value);
  549. }
  550. irq_num = rt1052_get_irqnum(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin);
  551. NVIC_SetPriority(irq_num, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0));
  552. EnableIRQ(irq_num);
  553. GPIO_PinInit(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin, &gpio);
  554. GPIO_PortEnableInterrupts(rt1052_pin_map[pin].gpio, 1U << rt1052_pin_map[pin].gpio_pin);
  555. }
  556. else if(enabled == PIN_IRQ_DISABLE)
  557. {
  558. if(irq_map->enable == PIN_IRQ_DISABLE)
  559. {
  560. return RT_EOK;
  561. }
  562. irq_map->enable = PIN_IRQ_DISABLE;
  563. irq_num = rt1052_get_irqnum(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin);
  564. NVIC_DisableIRQ(irq_num);
  565. }
  566. else
  567. {
  568. return RT_EINVAL;
  569. }
  570. return RT_EOK;
  571. }
  572. int rt_hw_pin_init(void)
  573. {
  574. int ret = RT_EOK;
  575. rt1052_pin_ops.pin_mode = rt1052_pin_mode;
  576. rt1052_pin_ops.pin_read = rt1052_pin_read;
  577. rt1052_pin_ops.pin_write = rt1052_pin_write;
  578. rt1052_pin_ops.pin_attach_irq = rt1052_pin_attach_irq;
  579. rt1052_pin_ops.pin_detach_irq = rt1052_pin_detach_irq;
  580. rt1052_pin_ops.pin_irq_enable = rt1052_pin_irq_enable;
  581. ret = rt_device_pin_register("pin", &rt1052_pin_ops, RT_NULL);
  582. return ret;
  583. }
  584. INIT_BOARD_EXPORT(rt_hw_pin_init);
  585. #endif /*RT_USING_PIN */