interrupt.h 1.4 KB

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  1. /*
  2. * Copyright (c) 2006-2018, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2021-09-09 WCH the first version
  9. * 2023-01-04 WangShun Remove redundant files
  10. */
  11. #if defined (SOC_RISCV_SERIES_CH32V1)
  12. #include "ch32v10x.h"
  13. #elif defined (SOC_RISCV_SERIES_CH32V2)
  14. #include "ch32v20x.h"
  15. #elif defined (SOC_RISCV_SERIES_CH32V3)
  16. #include "ch32v30x.h"
  17. #else
  18. #error "CH32 architecture doesn't support!"
  19. #endif
  20. /*
  21. * trigger soft interrupt
  22. */
  23. void sw_setpend(void)
  24. {
  25. /*CH32V103 does not support systick software interrupt*/
  26. #if defined(SOC_RISCV_SERIES_CH32V1)
  27. NVIC_SetPendingIRQ(Software_IRQn);
  28. #else
  29. SysTick->CTLR |= (1 << 31);
  30. #endif
  31. }
  32. /*
  33. * clear soft interrupt
  34. */
  35. void sw_clearpend(void)
  36. {
  37. /*CH32V103 does not support systick software interrupt*/
  38. #if defined(SOC_RISCV_SERIES_CH32V1)
  39. NVIC_ClearPendingIRQ(Software_IRQn);
  40. #else
  41. SysTick->CTLR &= ~(1 << 31);
  42. #endif
  43. }
  44. /*
  45. * disable interrupt and save mstatus
  46. */
  47. rt_weak rt_base_t rt_hw_interrupt_disable(void)
  48. {
  49. rt_base_t value=0;
  50. #if defined(SOC_RISCV_SERIES_CH32V3)
  51. asm("csrrw %0, mstatus, %1":"=r"(value):"r"(0x7800));
  52. #else
  53. asm("csrrw %0, mstatus, %1":"=r"(value):"r"(0x1800));
  54. #endif
  55. return value;
  56. }
  57. /*
  58. * enable interrupt and resume mstatus
  59. */
  60. rt_weak void rt_hw_interrupt_enable(rt_base_t level)
  61. {
  62. asm("csrw mstatus, %0": :"r"(level));
  63. }