drv_spi.c 5.9 KB

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  1. /*
  2. * Copyright (c) 2006-2024 RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2024-08-1 hywing The first version for MCXA
  9. */
  10. #include "rtdevice.h"
  11. #include "drv_spi.h"
  12. #include "fsl_lpspi.h"
  13. #include "fsl_lpspi_edma.h"
  14. #define DMA_MAX_TRANSFER_SIZE (32767)
  15. enum
  16. {
  17. #ifdef BSP_USING_SPI0
  18. SPI0_INDEX,
  19. #endif
  20. #ifdef BSP_USING_SPI1
  21. SPI1_INDEX,
  22. #endif
  23. };
  24. struct lpc_spi
  25. {
  26. struct rt_spi_bus parent;
  27. LPSPI_Type *LPSPIx;
  28. clock_attach_id_t clock_attach_id;
  29. clock_div_name_t clock_div_name;
  30. clock_name_t clock_name;
  31. DMA_Type *DMAx;
  32. uint8_t tx_dma_chl;
  33. uint8_t rx_dma_chl;
  34. edma_handle_t dma_tx_handle;
  35. edma_handle_t dma_rx_handle;
  36. dma_request_source_t tx_dma_request;
  37. dma_request_source_t rx_dma_request;
  38. lpspi_master_edma_handle_t spi_dma_handle;
  39. rt_sem_t sem;
  40. char *name;
  41. };
  42. static struct lpc_spi lpc_obj[] =
  43. {
  44. #ifdef BSP_USING_SPI0
  45. {
  46. .LPSPIx = LPSPI0,
  47. .clock_attach_id = kFRO12M_to_LPSPI0,
  48. .clock_div_name = kCLOCK_DivLPSPI0,
  49. .clock_name = kCLOCK_Fro12M,
  50. .tx_dma_request = kDma0RequestLPSPI0Tx,
  51. .rx_dma_request = kDma0RequestLPSPI0Rx,
  52. .DMAx = DMA0,
  53. .tx_dma_chl = 0,
  54. .rx_dma_chl = 1,
  55. .name = "spi0",
  56. },
  57. #endif
  58. #ifdef BSP_USING_SPI1
  59. {
  60. .LPSPIx = LPSPI1,
  61. .clock_attach_id = kFRO12M_to_LPSPI1,
  62. .clock_div_name = kCLOCK_DivLPSPI1,
  63. .clock_name = kCLOCK_Fro12M,
  64. .tx_dma_request = kDma0RequestLPSPI1Tx,
  65. .rx_dma_request = kDma0RequestLPSPI1Rx,
  66. .DMAx = DMA0,
  67. .tx_dma_chl = 0,
  68. .rx_dma_chl = 1,
  69. .name = "spi1",
  70. },
  71. #endif
  72. };
  73. rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_uint32_t pin)
  74. {
  75. struct rt_spi_device *spi_device = rt_malloc(sizeof(struct rt_spi_device));
  76. if (!spi_device)
  77. {
  78. return -RT_ENOMEM;
  79. }
  80. return rt_spi_bus_attach_device_cspin(spi_device, device_name, bus_name, pin, NULL);
  81. }
  82. static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg)
  83. {
  84. return RT_EOK;
  85. }
  86. static void LPSPI_MasterUserCallback(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, status_t status, void *userData)
  87. {
  88. struct lpc_spi *spi = (struct lpc_spi *)userData;
  89. rt_sem_release(spi->sem);
  90. }
  91. static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
  92. {
  93. int i;
  94. lpspi_transfer_t transfer = {0};
  95. RT_ASSERT(device != RT_NULL);
  96. RT_ASSERT(device->bus != RT_NULL);
  97. RT_ASSERT(device->bus->parent.user_data != RT_NULL);
  98. struct lpc_spi *spi = device->bus->parent.user_data;
  99. if (message->cs_take)
  100. {
  101. rt_pin_write(device->cs_pin, PIN_LOW);
  102. }
  103. transfer.dataSize = message->length;
  104. transfer.rxData = (uint8_t *)(message->recv_buf);
  105. transfer.txData = (uint8_t *)(message->send_buf);
  106. /* if(message->length < MAX_DMA_TRANSFER_SIZE)*/
  107. uint32_t block, remain;
  108. block = message->length / DMA_MAX_TRANSFER_SIZE;
  109. remain = message->length % DMA_MAX_TRANSFER_SIZE;
  110. for (i = 0; i < block; i++)
  111. {
  112. transfer.dataSize = DMA_MAX_TRANSFER_SIZE;
  113. if (message->recv_buf) transfer.rxData = (uint8_t *)(message->recv_buf + i *DMA_MAX_TRANSFER_SIZE);
  114. if (message->send_buf) transfer.txData = (uint8_t *)(message->send_buf + i *DMA_MAX_TRANSFER_SIZE);
  115. LPSPI_MasterTransferEDMA(spi->LPSPIx, &spi->spi_dma_handle, &transfer);
  116. rt_sem_take(spi->sem, RT_WAITING_FOREVER);
  117. }
  118. if (remain)
  119. {
  120. transfer.dataSize = remain;
  121. if (message->recv_buf) transfer.rxData = (uint8_t *)(message->recv_buf + i *DMA_MAX_TRANSFER_SIZE);
  122. if (message->send_buf) transfer.txData = (uint8_t *)(message->send_buf + i *DMA_MAX_TRANSFER_SIZE);
  123. LPSPI_MasterTransferEDMA(spi->LPSPIx, &spi->spi_dma_handle, &transfer);
  124. rt_sem_take(spi->sem, RT_WAITING_FOREVER);
  125. }
  126. if (message->cs_release)
  127. {
  128. rt_pin_write(device->cs_pin, PIN_HIGH);
  129. }
  130. return message->length;
  131. }
  132. static struct rt_spi_ops lpc_spi_ops =
  133. {
  134. .configure = spi_configure,
  135. .xfer = spixfer
  136. };
  137. int rt_hw_spi_init(void)
  138. {
  139. int i;
  140. for (i = 0; i < ARRAY_SIZE(lpc_obj); i++)
  141. {
  142. CLOCK_SetClockDiv(lpc_obj[i].clock_div_name, 1u);
  143. CLOCK_AttachClk(lpc_obj[i].clock_attach_id);
  144. lpc_obj[i].parent.parent.user_data = &lpc_obj[i];
  145. lpc_obj[i].sem = rt_sem_create("sem_spi", 0, RT_IPC_FLAG_FIFO);
  146. lpspi_master_config_t masterConfig;
  147. LPSPI_MasterGetDefaultConfig(&masterConfig);
  148. masterConfig.baudRate = 1 * 1000 * 1000;
  149. masterConfig.pcsToSckDelayInNanoSec = 1000000000U / masterConfig.baudRate * 1U;
  150. masterConfig.lastSckToPcsDelayInNanoSec = 1000000000U / masterConfig.baudRate * 1U;
  151. masterConfig.betweenTransferDelayInNanoSec = 1000000000U / masterConfig.baudRate * 1U;
  152. LPSPI_MasterInit(lpc_obj[i].LPSPIx, &masterConfig, CLOCK_GetFreq(lpc_obj[i].clock_name));
  153. EDMA_CreateHandle(&lpc_obj[i].dma_tx_handle, lpc_obj[i].DMAx, lpc_obj[i].tx_dma_chl);
  154. EDMA_CreateHandle(&lpc_obj[i].dma_rx_handle, lpc_obj[i].DMAx, lpc_obj[i].rx_dma_chl);
  155. EDMA_SetChannelMux(lpc_obj[i].DMAx, lpc_obj[i].tx_dma_chl, lpc_obj[i].tx_dma_request);
  156. EDMA_SetChannelMux(lpc_obj[i].DMAx, lpc_obj[i].rx_dma_chl, lpc_obj[i].rx_dma_request);
  157. LPSPI_MasterTransferCreateHandleEDMA(lpc_obj[i].LPSPIx, &lpc_obj[i].spi_dma_handle, LPSPI_MasterUserCallback, &lpc_obj[i], &lpc_obj[i].dma_rx_handle, &lpc_obj[i].dma_tx_handle);
  158. rt_spi_bus_register(&lpc_obj[i].parent, lpc_obj[i].name, &lpc_spi_ops);
  159. }
  160. return RT_EOK;
  161. }
  162. INIT_DEVICE_EXPORT(rt_hw_spi_init);