drv_pwm.c 16 KB

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  1. /*
  2. * Copyright (c) 2006-2023, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-12-13 zylx first version
  9. * 2021-01-23 thread-liu Fix the timer clock frequency doubling problem
  10. */
  11. #include <board.h>
  12. #ifdef BSP_USING_PWM
  13. #include "drv_config.h"
  14. #include "drv_tim.h"
  15. #include <drivers/rt_drv_pwm.h>
  16. //#define DRV_DEBUG
  17. #define LOG_TAG "drv.pwm"
  18. #include <drv_log.h>
  19. #define MAX_PERIOD 65535
  20. #define MIN_PERIOD 3
  21. #define MIN_PULSE 2
  22. enum
  23. {
  24. #ifdef BSP_USING_PWM1
  25. PWM1_INDEX,
  26. #endif
  27. #ifdef BSP_USING_PWM2
  28. PWM2_INDEX,
  29. #endif
  30. #ifdef BSP_USING_PWM3
  31. PWM3_INDEX,
  32. #endif
  33. #ifdef BSP_USING_PWM4
  34. PWM4_INDEX,
  35. #endif
  36. #ifdef BSP_USING_PWM5
  37. PWM5_INDEX,
  38. #endif
  39. #ifdef BSP_USING_PWM6
  40. PWM6_INDEX,
  41. #endif
  42. #ifdef BSP_USING_PWM7
  43. PWM7_INDEX,
  44. #endif
  45. #ifdef BSP_USING_PWM8
  46. PWM8_INDEX,
  47. #endif
  48. #ifdef BSP_USING_PWM9
  49. PWM9_INDEX,
  50. #endif
  51. #ifdef BSP_USING_PWM10
  52. PWM10_INDEX,
  53. #endif
  54. #ifdef BSP_USING_PWM11
  55. PWM11_INDEX,
  56. #endif
  57. #ifdef BSP_USING_PWM12
  58. PWM12_INDEX,
  59. #endif
  60. #ifdef BSP_USING_PWM13
  61. PWM13_INDEX,
  62. #endif
  63. #ifdef BSP_USING_PWM14
  64. PWM14_INDEX,
  65. #endif
  66. #ifdef BSP_USING_PWM15
  67. PWM15_INDEX,
  68. #endif
  69. #ifdef BSP_USING_PWM16
  70. PWM16_INDEX,
  71. #endif
  72. #ifdef BSP_USING_PWM17
  73. PWM17_INDEX,
  74. #endif
  75. };
  76. struct stm32_pwm
  77. {
  78. struct rt_device_pwm pwm_device;
  79. TIM_HandleTypeDef tim_handle;
  80. rt_uint8_t channel;
  81. char *name;
  82. };
  83. static struct stm32_pwm stm32_pwm_obj[] =
  84. {
  85. #ifdef BSP_USING_PWM1
  86. PWM1_CONFIG,
  87. #endif
  88. #ifdef BSP_USING_PWM2
  89. PWM2_CONFIG,
  90. #endif
  91. #ifdef BSP_USING_PWM3
  92. PWM3_CONFIG,
  93. #endif
  94. #ifdef BSP_USING_PWM4
  95. PWM4_CONFIG,
  96. #endif
  97. #ifdef BSP_USING_PWM5
  98. PWM5_CONFIG,
  99. #endif
  100. #ifdef BSP_USING_PWM6
  101. PWM6_CONFIG,
  102. #endif
  103. #ifdef BSP_USING_PWM7
  104. PWM7_CONFIG,
  105. #endif
  106. #ifdef BSP_USING_PWM8
  107. PWM8_CONFIG,
  108. #endif
  109. #ifdef BSP_USING_PWM9
  110. PWM9_CONFIG,
  111. #endif
  112. #ifdef BSP_USING_PWM10
  113. PWM10_CONFIG,
  114. #endif
  115. #ifdef BSP_USING_PWM11
  116. PWM11_CONFIG,
  117. #endif
  118. #ifdef BSP_USING_PWM12
  119. PWM12_CONFIG,
  120. #endif
  121. #ifdef BSP_USING_PWM13
  122. PWM13_CONFIG,
  123. #endif
  124. #ifdef BSP_USING_PWM14
  125. PWM14_CONFIG,
  126. #endif
  127. #ifdef BSP_USING_PWM15
  128. PWM15_CONFIG,
  129. #endif
  130. #ifdef BSP_USING_PWM16
  131. PWM16_CONFIG,
  132. #endif
  133. #ifdef BSP_USING_PWM17
  134. PWM17_CONFIG,
  135. #endif
  136. };
  137. static rt_uint64_t tim_clock_get(TIM_HandleTypeDef *htim)
  138. {
  139. rt_uint32_t pclk1_doubler, pclk2_doubler;
  140. rt_uint64_t tim_clock;
  141. stm32_tim_pclkx_doubler_get(&pclk1_doubler, &pclk2_doubler);
  142. /* Some series may only have APBPERIPH_BASE, don't have HAL_RCC_GetPCLK2Freq */
  143. #if defined(APBPERIPH_BASE)
  144. tim_clock = (rt_uint32_t)(HAL_RCC_GetPCLK1Freq() * pclk1_doubler);
  145. #elif defined(APB1PERIPH_BASE) || defined(APB2PERIPH_BASE)
  146. if ((rt_uint32_t)htim->Instance >= APB2PERIPH_BASE)
  147. {
  148. tim_clock = (rt_uint32_t)(HAL_RCC_GetPCLK2Freq() * pclk2_doubler);
  149. }
  150. else
  151. {
  152. tim_clock = (rt_uint32_t)(HAL_RCC_GetPCLK1Freq() * pclk1_doubler);
  153. }
  154. #endif
  155. return tim_clock;
  156. }
  157. static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg);
  158. static struct rt_pwm_ops drv_ops =
  159. {
  160. drv_pwm_control
  161. };
  162. static rt_err_t drv_pwm_enable(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration, rt_bool_t enable)
  163. {
  164. /* Converts the channel number to the channel number of Hal library */
  165. rt_uint32_t channel = 0x04 * (configuration->channel - 1);
  166. if (!configuration->complementary)
  167. {
  168. if (!enable)
  169. {
  170. HAL_TIM_PWM_Stop(htim, channel);
  171. }
  172. else
  173. {
  174. HAL_TIM_PWM_Start(htim, channel);
  175. }
  176. }
  177. else if (configuration->complementary)
  178. {
  179. if (!enable)
  180. {
  181. HAL_TIMEx_PWMN_Stop(htim, channel);
  182. }
  183. else
  184. {
  185. HAL_TIMEx_PWMN_Start(htim, channel);
  186. }
  187. }
  188. return RT_EOK;
  189. }
  190. static rt_err_t drv_pwm_get(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration)
  191. {
  192. /* Converts the channel number to the channel number of Hal library */
  193. rt_uint32_t channel = 0x04 * (configuration->channel - 1);
  194. rt_uint64_t tim_clock;
  195. tim_clock = tim_clock_get(htim);
  196. if (__HAL_TIM_GET_CLOCKDIVISION(htim) == TIM_CLOCKDIVISION_DIV2)
  197. {
  198. tim_clock = tim_clock / 2;
  199. }
  200. else if (__HAL_TIM_GET_CLOCKDIVISION(htim) == TIM_CLOCKDIVISION_DIV4)
  201. {
  202. tim_clock = tim_clock / 4;
  203. }
  204. /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
  205. tim_clock /= 1000000UL;
  206. configuration->period = (__HAL_TIM_GET_AUTORELOAD(htim) + 1) * (htim->Instance->PSC + 1) * 1000UL / tim_clock;
  207. configuration->pulse = (__HAL_TIM_GET_COMPARE(htim, channel) + 1) * (htim->Instance->PSC + 1) * 1000UL / tim_clock;
  208. return RT_EOK;
  209. }
  210. static rt_err_t drv_pwm_set(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration)
  211. {
  212. rt_uint32_t period, pulse;
  213. rt_uint64_t tim_clock, psc;
  214. /* Converts the channel number to the channel number of Hal library */
  215. rt_uint32_t channel = 0x04 * (configuration->channel - 1);
  216. tim_clock = tim_clock_get(htim);
  217. /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
  218. tim_clock /= 1000000UL;
  219. period = (rt_uint64_t)configuration->period * tim_clock / 1000ULL ;
  220. psc = period / MAX_PERIOD + 1;
  221. period = period / psc;
  222. __HAL_TIM_SET_PRESCALER(htim, psc - 1);
  223. if (period < MIN_PERIOD)
  224. {
  225. period = MIN_PERIOD;
  226. }
  227. __HAL_TIM_SET_AUTORELOAD(htim, period - 1);
  228. pulse = (rt_uint64_t)configuration->pulse * tim_clock / psc / 1000ULL;
  229. if (pulse < MIN_PULSE)
  230. {
  231. pulse = MIN_PULSE;
  232. }
  233. /*To determine user input, output high level is required*/
  234. else if (pulse >= period)
  235. {
  236. pulse = period + 1;
  237. }
  238. __HAL_TIM_SET_COMPARE(htim, channel, pulse - 1);
  239. /* If you want the PWM setting to take effect immediately,
  240. please uncommon the following code, but it will cause the last PWM cycle not complete. */
  241. //__HAL_TIM_SET_COUNTER(htim, 0);
  242. //HAL_TIM_GenerateEvent(htim, TIM_EVENTSOURCE_UPDATE); /* Update frequency value */
  243. return RT_EOK;
  244. }
  245. static rt_err_t drv_pwm_set_period(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration)
  246. {
  247. rt_uint32_t period;
  248. rt_uint64_t tim_clock, psc;
  249. tim_clock = tim_clock_get(htim);
  250. /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
  251. tim_clock /= 1000000UL;
  252. period = (rt_uint64_t)configuration->period * tim_clock / 1000ULL ;
  253. psc = period / MAX_PERIOD + 1;
  254. period = period / psc;
  255. __HAL_TIM_SET_PRESCALER(htim, psc - 1);
  256. if (period < MIN_PERIOD)
  257. {
  258. period = MIN_PERIOD;
  259. }
  260. __HAL_TIM_SET_AUTORELOAD(htim, period - 1);
  261. return RT_EOK;
  262. }
  263. static rt_err_t drv_pwm_set_pulse(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration)
  264. {
  265. rt_uint32_t period, pulse;
  266. rt_uint64_t tim_clock;
  267. /* Converts the channel number to the channel number of Hal library */
  268. rt_uint32_t channel = 0x04 * (configuration->channel - 1);
  269. tim_clock = tim_clock_get(htim);
  270. /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
  271. tim_clock /= 1000000UL;
  272. period = (__HAL_TIM_GET_AUTORELOAD(htim) + 1) * (htim->Instance->PSC + 1) * 1000UL / tim_clock;
  273. pulse = (rt_uint64_t)configuration->pulse * (__HAL_TIM_GET_AUTORELOAD(htim) + 1) / period;
  274. if (pulse < MIN_PULSE)
  275. {
  276. pulse = MIN_PULSE;
  277. }
  278. else if (pulse > period)
  279. {
  280. pulse = period;
  281. }
  282. __HAL_TIM_SET_COMPARE(htim, channel, pulse - 1);
  283. return RT_EOK;
  284. }
  285. static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
  286. {
  287. struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
  288. TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)device->parent.user_data;
  289. switch (cmd)
  290. {
  291. case PWM_CMD_ENABLE:
  292. return drv_pwm_enable(htim, configuration, RT_TRUE);
  293. case PWM_CMD_DISABLE:
  294. return drv_pwm_enable(htim, configuration, RT_FALSE);
  295. case PWM_CMD_SET:
  296. return drv_pwm_set(htim, configuration);
  297. case PWM_CMD_SET_PERIOD:
  298. return drv_pwm_set_period(htim, configuration);
  299. case PWM_CMD_SET_PULSE:
  300. return drv_pwm_set_pulse(htim, configuration);
  301. case PWM_CMD_GET:
  302. return drv_pwm_get(htim, configuration);
  303. default:
  304. return -RT_EINVAL;
  305. }
  306. }
  307. static rt_err_t stm32_hw_pwm_init(struct stm32_pwm *device)
  308. {
  309. rt_err_t result = RT_EOK;
  310. TIM_HandleTypeDef *tim = RT_NULL;
  311. TIM_OC_InitTypeDef oc_config = {0};
  312. TIM_MasterConfigTypeDef master_config = {0};
  313. TIM_ClockConfigTypeDef clock_config = {0};
  314. RT_ASSERT(device != RT_NULL);
  315. tim = (TIM_HandleTypeDef *)&device->tim_handle;
  316. /* configure the timer to pwm mode */
  317. tim->Init.Prescaler = 0;
  318. tim->Init.CounterMode = TIM_COUNTERMODE_UP;
  319. tim->Init.Period = 0;
  320. tim->Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
  321. #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4)
  322. tim->Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
  323. #endif
  324. if (HAL_TIM_Base_Init(tim) != HAL_OK)
  325. {
  326. LOG_E("%s pwm init failed", device->name);
  327. result = -RT_ERROR;
  328. goto __exit;
  329. }
  330. stm32_tim_enable_clock(tim);
  331. clock_config.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
  332. if (HAL_TIM_ConfigClockSource(tim, &clock_config) != HAL_OK)
  333. {
  334. LOG_E("%s clock init failed", device->name);
  335. result = -RT_ERROR;
  336. goto __exit;
  337. }
  338. if (HAL_TIM_PWM_Init(tim) != HAL_OK)
  339. {
  340. LOG_E("%s pwm init failed", device->name);
  341. result = -RT_ERROR;
  342. goto __exit;
  343. }
  344. if(IS_TIM_MASTER_INSTANCE(tim->Instance))
  345. {
  346. master_config.MasterOutputTrigger = TIM_TRGO_RESET;
  347. master_config.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
  348. if (HAL_TIMEx_MasterConfigSynchronization(tim, &master_config) != HAL_OK)
  349. {
  350. LOG_E("%s master config failed", device->name);
  351. result = -RT_ERROR;
  352. goto __exit;
  353. }
  354. }
  355. oc_config.OCMode = TIM_OCMODE_PWM1;
  356. oc_config.Pulse = 0;
  357. oc_config.OCPolarity = TIM_OCPOLARITY_HIGH;
  358. oc_config.OCFastMode = TIM_OCFAST_DISABLE;
  359. oc_config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
  360. oc_config.OCIdleState = TIM_OCIDLESTATE_RESET;
  361. /* config pwm channel */
  362. if (device->channel & 0x01)
  363. {
  364. if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_1) != HAL_OK)
  365. {
  366. LOG_E("%s channel1 config failed", device->name);
  367. result = -RT_ERROR;
  368. goto __exit;
  369. }
  370. }
  371. if (device->channel & 0x02)
  372. {
  373. if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_2) != HAL_OK)
  374. {
  375. LOG_E("%s channel2 config failed", device->name);
  376. result = -RT_ERROR;
  377. goto __exit;
  378. }
  379. }
  380. if (device->channel & 0x04)
  381. {
  382. if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_3) != HAL_OK)
  383. {
  384. LOG_E("%s channel3 config failed", device->name);
  385. result = -RT_ERROR;
  386. goto __exit;
  387. }
  388. }
  389. if (device->channel & 0x08)
  390. {
  391. if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_4) != HAL_OK)
  392. {
  393. LOG_E("%s channel4 config failed", device->name);
  394. result = -RT_ERROR;
  395. goto __exit;
  396. }
  397. }
  398. /* pwm pin configuration */
  399. void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
  400. HAL_TIM_MspPostInit(tim);
  401. /* enable update request source */
  402. __HAL_TIM_URS_ENABLE(tim);
  403. __exit:
  404. return result;
  405. }
  406. static void stm32_pwm_get_channel(void)
  407. {
  408. #ifdef BSP_USING_PWM1_CH1
  409. stm32_pwm_obj[PWM1_INDEX].channel |= 1 << 0;
  410. #endif
  411. #ifdef BSP_USING_PWM1_CH2
  412. stm32_pwm_obj[PWM1_INDEX].channel |= 1 << 1;
  413. #endif
  414. #ifdef BSP_USING_PWM1_CH3
  415. stm32_pwm_obj[PWM1_INDEX].channel |= 1 << 2;
  416. #endif
  417. #ifdef BSP_USING_PWM1_CH4
  418. stm32_pwm_obj[PWM1_INDEX].channel |= 1 << 3;
  419. #endif
  420. #ifdef BSP_USING_PWM2_CH1
  421. stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 0;
  422. #endif
  423. #ifdef BSP_USING_PWM2_CH2
  424. stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 1;
  425. #endif
  426. #ifdef BSP_USING_PWM2_CH3
  427. stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 2;
  428. #endif
  429. #ifdef BSP_USING_PWM2_CH4
  430. stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 3;
  431. #endif
  432. #ifdef BSP_USING_PWM3_CH1
  433. stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 0;
  434. #endif
  435. #ifdef BSP_USING_PWM3_CH2
  436. stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 1;
  437. #endif
  438. #ifdef BSP_USING_PWM3_CH3
  439. stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 2;
  440. #endif
  441. #ifdef BSP_USING_PWM3_CH4
  442. stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 3;
  443. #endif
  444. #ifdef BSP_USING_PWM4_CH1
  445. stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 0;
  446. #endif
  447. #ifdef BSP_USING_PWM4_CH2
  448. stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 1;
  449. #endif
  450. #ifdef BSP_USING_PWM4_CH3
  451. stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 2;
  452. #endif
  453. #ifdef BSP_USING_PWM4_CH4
  454. stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 3;
  455. #endif
  456. #ifdef BSP_USING_PWM5_CH1
  457. stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 0;
  458. #endif
  459. #ifdef BSP_USING_PWM5_CH2
  460. stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 1;
  461. #endif
  462. #ifdef BSP_USING_PWM5_CH3
  463. stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 2;
  464. #endif
  465. #ifdef BSP_USING_PWM5_CH4
  466. stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 3;
  467. #endif
  468. #ifdef BSP_USING_PWM6_CH1
  469. stm32_pwm_obj[PWM6_INDEX].channel |= 1 << 0;
  470. #endif
  471. #ifdef BSP_USING_PWM6_CH2
  472. stm32_pwm_obj[PWM6_INDEX].channel |= 1 << 1;
  473. #endif
  474. #ifdef BSP_USING_PWM6_CH3
  475. stm32_pwm_obj[PWM6_INDEX].channel |= 1 << 2;
  476. #endif
  477. #ifdef BSP_USING_PWM6_CH4
  478. stm32_pwm_obj[PWM6_INDEX].channel |= 1 << 3;
  479. #endif
  480. #ifdef BSP_USING_PWM7_CH1
  481. stm32_pwm_obj[PWM7_INDEX].channel |= 1 << 0;
  482. #endif
  483. #ifdef BSP_USING_PWM7_CH2
  484. stm32_pwm_obj[PWM7_INDEX].channel |= 1 << 1;
  485. #endif
  486. #ifdef BSP_USING_PWM7_CH3
  487. stm32_pwm_obj[PWM7_INDEX].channel |= 1 << 2;
  488. #endif
  489. #ifdef BSP_USING_PWM7_CH4
  490. stm32_pwm_obj[PWM7_INDEX].channel |= 1 << 3;
  491. #endif
  492. #ifdef BSP_USING_PWM8_CH1
  493. stm32_pwm_obj[PWM8_INDEX].channel |= 1 << 0;
  494. #endif
  495. #ifdef BSP_USING_PWM8_CH2
  496. stm32_pwm_obj[PWM8_INDEX].channel |= 1 << 1;
  497. #endif
  498. #ifdef BSP_USING_PWM8_CH3
  499. stm32_pwm_obj[PWM8_INDEX].channel |= 1 << 2;
  500. #endif
  501. #ifdef BSP_USING_PWM8_CH4
  502. stm32_pwm_obj[PWM8_INDEX].channel |= 1 << 3;
  503. #endif
  504. #ifdef BSP_USING_PWM9_CH1
  505. stm32_pwm_obj[PWM9_INDEX].channel |= 1 << 0;
  506. #endif
  507. #ifdef BSP_USING_PWM9_CH2
  508. stm32_pwm_obj[PWM9_INDEX].channel |= 1 << 1;
  509. #endif
  510. #ifdef BSP_USING_PWM9_CH3
  511. stm32_pwm_obj[PWM9_INDEX].channel |= 1 << 2;
  512. #endif
  513. #ifdef BSP_USING_PWM9_CH4
  514. stm32_pwm_obj[PWM9_INDEX].channel |= 1 << 3;
  515. #endif
  516. #ifdef BSP_USING_PWM10_CH1
  517. stm32_pwm_obj[PWM10_INDEX].channel |= 1 << 0;
  518. #endif
  519. #ifdef BSP_USING_PWM11_CH1
  520. stm32_pwm_obj[PWM11_INDEX].channel |= 1 << 0;
  521. #endif
  522. #ifdef BSP_USING_PWM12_CH1
  523. stm32_pwm_obj[PWM12_INDEX].channel |= 1 << 0;
  524. #endif
  525. #ifdef BSP_USING_PWM12_CH2
  526. stm32_pwm_obj[PWM12_INDEX].channel |= 1 << 1;
  527. #endif
  528. #ifdef BSP_USING_PWM13_CH1
  529. stm32_pwm_obj[PWM13_INDEX].channel |= 1 << 0;
  530. #endif
  531. #ifdef BSP_USING_PWM14_CH1
  532. stm32_pwm_obj[PWM14_INDEX].channel |= 1 << 0;
  533. #endif
  534. #ifdef BSP_USING_PWM15_CH1
  535. stm32_pwm_obj[PWM15_INDEX].channel |= 1 << 0;
  536. #endif
  537. #ifdef BSP_USING_PWM16_CH1
  538. stm32_pwm_obj[PWM16_INDEX].channel |= 1 << 0;
  539. #endif
  540. #ifdef BSP_USING_PWM17_CH1
  541. stm32_pwm_obj[PWM17_INDEX].channel |= 1 << 0;
  542. #endif
  543. }
  544. static int stm32_pwm_init(void)
  545. {
  546. int i = 0;
  547. int result = RT_EOK;
  548. stm32_pwm_get_channel();
  549. for (i = 0; i < sizeof(stm32_pwm_obj) / sizeof(stm32_pwm_obj[0]); i++)
  550. {
  551. /* pwm init */
  552. if (stm32_hw_pwm_init(&stm32_pwm_obj[i]) != RT_EOK)
  553. {
  554. LOG_E("%s init failed", stm32_pwm_obj[i].name);
  555. result = -RT_ERROR;
  556. goto __exit;
  557. }
  558. else
  559. {
  560. LOG_D("%s init success", stm32_pwm_obj[i].name);
  561. /* register pwm device */
  562. if (rt_device_pwm_register(&stm32_pwm_obj[i].pwm_device, stm32_pwm_obj[i].name, &drv_ops, &stm32_pwm_obj[i].tim_handle) == RT_EOK)
  563. {
  564. LOG_D("%s register success", stm32_pwm_obj[i].name);
  565. }
  566. else
  567. {
  568. LOG_E("%s register failed", stm32_pwm_obj[i].name);
  569. result = -RT_ERROR;
  570. }
  571. }
  572. }
  573. __exit:
  574. return result;
  575. }
  576. INIT_DEVICE_EXPORT(stm32_pwm_init);
  577. #endif /* BSP_USING_PWM */