drv_i2c.c 9.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381
  1. /*
  2. * Copyright (c) 2006-2019, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2017-06-05 tanek first implementation.
  9. * 2018-04-19 misonyo Porting for gd32f30x
  10. * 2019-03-31 xuzhuoyi Porting for gd32e230
  11. */
  12. #include "drv_i2c.h"
  13. #include <rtthread.h>
  14. #include "gd32e230.h"
  15. #ifdef RT_USING_I2C
  16. #include <rtdevice.h>
  17. #ifdef RT_USING_I2C_BITOPS
  18. /*user can change this*/
  19. #define I2C_BUS_NAME "i2c2"
  20. /*user should change this to adapt specific board*/
  21. #define I2C_SCL_PIN GPIO_PIN_4
  22. #define I2C_SCL_PORT GPIOE
  23. #define I2C_SCL_CLK RCU_GPIOE
  24. #define I2C_SDA_PIN GPIO_PIN_5
  25. #define I2C_SDA_PORT GPIOE
  26. #define I2C_SDA_CLK RCU_GPIOE
  27. struct gd32_i2c_bit_data
  28. {
  29. struct
  30. {
  31. rcu_periph_enum clk;
  32. rt_uint32_t port;
  33. rt_uint32_t pin;
  34. }scl, sda;
  35. };
  36. static void gpio_set_sda(void *data, rt_int32_t state)
  37. {
  38. struct gd32_i2c_bit_data* bd = data;
  39. if (state)
  40. {
  41. gpio_bit_set(bd->sda.port, bd->sda.pin);
  42. }
  43. else
  44. {
  45. gpio_bit_reset(bd->sda.port, bd->sda.pin);
  46. }
  47. }
  48. static void gpio_set_scl(void *data, rt_int32_t state)
  49. {
  50. struct gd32_i2c_bit_data* bd = data;
  51. if (state)
  52. {
  53. gpio_bit_set(bd->scl.port, bd->scl.pin);
  54. }
  55. else
  56. {
  57. gpio_bit_reset(bd->scl.port, bd->scl.pin);
  58. }
  59. }
  60. static rt_int32_t gpio_get_sda(void *data)
  61. {
  62. struct gd32_i2c_bit_data* bd = data;
  63. return gpio_input_bit_get(bd->sda.port, bd->sda.pin);
  64. }
  65. static rt_int32_t gpio_get_scl(void *data)
  66. {
  67. struct gd32_i2c_bit_data* bd = data;
  68. return gpio_input_bit_get(bd->scl.port, bd->scl.pin);
  69. }
  70. static void gpio_udelay(rt_uint32_t us)
  71. {
  72. int i = ( rcu_clock_freq_get(CK_SYS) / 4000000 * us);
  73. while(i)
  74. {
  75. i--;
  76. }
  77. }
  78. static void drv_i2c_gpio_init(const struct gd32_i2c_bit_data* bd)
  79. {
  80. rcu_periph_clock_enable(bd->sda.clk);
  81. rcu_periph_clock_enable(bd->scl.clk);
  82. gpio_init(bd->sda.port, GPIO_MODE_OUT_OD, GPIO_OSPEED_10MHZ, bd->sda.pin);
  83. gpio_init(bd->scl.port, GPIO_MODE_OUT_OD, GPIO_OSPEED_10MHZ, bd->scl.pin);
  84. gpio_bit_set(bd->sda.port, bd->sda.pin);
  85. gpio_bit_set(bd->scl.port, bd->scl.pin);
  86. }
  87. #else /* use hardware i2c */
  88. struct gd32_i2c_bus
  89. {
  90. struct rt_i2c_bus_device parent;
  91. rt_uint32_t i2c_periph;
  92. };
  93. static int gd32_i2c_read(rt_uint32_t i2c_periph, rt_uint16_t slave_address, rt_uint8_t* p_buffer, rt_uint16_t data_byte)
  94. {
  95. /* wait until I2C bus is idle */
  96. while(i2c_flag_get(i2c_periph, I2C_FLAG_I2CBSY));
  97. /* send a start condition to I2C bus */
  98. i2c_start_on_bus(i2c_periph);
  99. /* wait until SBSEND bit is set */
  100. while(!i2c_flag_get(i2c_periph, I2C_FLAG_SBSEND));
  101. /* send slave address to I2C bus */
  102. i2c_master_addressing(i2c_periph, slave_address<<1, I2C_RECEIVER);
  103. /* wait until ADDSEND bit is set */
  104. while(!i2c_flag_get(i2c_periph, I2C_FLAG_ADDSEND));
  105. /* clear the ADDSEND bit */
  106. i2c_flag_clear(i2c_periph,I2C_FLAG_ADDSEND);
  107. if(1 == data_byte){
  108. /* disable acknowledge */
  109. i2c_ack_config(i2c_periph,I2C_ACK_DISABLE);
  110. /* send a stop condition to I2C bus */
  111. i2c_stop_on_bus(i2c_periph);
  112. }
  113. /* while there is data to be read */
  114. while(data_byte)
  115. {
  116. /* wait until the RBNE bit is set and clear it */
  117. if(i2c_flag_get(i2c_periph, I2C_FLAG_RBNE))
  118. {
  119. /* read a byte from the EEPROM */
  120. *p_buffer = i2c_data_receive(i2c_periph);
  121. /* point to the next location where the byte read will be saved */
  122. p_buffer++;
  123. /* decrement the read bytes counter */
  124. data_byte--;
  125. if(1 == data_byte)
  126. {
  127. /* disable acknowledge */
  128. i2c_ack_config(i2c_periph,I2C_ACK_DISABLE);
  129. /* send a stop condition to I2C bus */
  130. i2c_stop_on_bus(i2c_periph);
  131. }
  132. }
  133. }
  134. /* wait until the stop condition is finished */
  135. while(I2C_CTL0(i2c_periph)&0x0200);
  136. /* enable acknowledge */
  137. i2c_ack_config(i2c_periph,I2C_ACK_ENABLE);
  138. i2c_ackpos_config(i2c_periph,I2C_ACKPOS_CURRENT);
  139. return 0;
  140. }
  141. static int gd32_i2c_write(rt_uint32_t i2c_periph, uint16_t slave_address, uint8_t* p_buffer, uint16_t data_byte)
  142. {
  143. /* wait until I2C bus is idle */
  144. while(i2c_flag_get(i2c_periph, I2C_FLAG_I2CBSY));
  145. /* send a start condition to I2C bus */
  146. i2c_start_on_bus(i2c_periph);
  147. /* wait until SBSEND bit is set */
  148. while(!i2c_flag_get(i2c_periph, I2C_FLAG_SBSEND));
  149. /* send slave address to I2C bus */
  150. i2c_master_addressing(i2c_periph, slave_address<<1, I2C_TRANSMITTER);
  151. /* wait until ADDSEND bit is set */
  152. while(!i2c_flag_get(i2c_periph, I2C_FLAG_ADDSEND));
  153. /* clear the ADDSEND bit */
  154. i2c_flag_clear(i2c_periph,I2C_FLAG_ADDSEND);
  155. /* wait until the transmit data buffer is empty */
  156. while(SET != i2c_flag_get( i2c_periph , I2C_FLAG_TBE));
  157. /* while there is data to be read */
  158. while(data_byte)
  159. {
  160. i2c_data_transmit(i2c_periph, *p_buffer);
  161. /* point to the next byte to be written */
  162. p_buffer++;
  163. /* decrement the write bytes counter */
  164. data_byte --;
  165. /* wait until BTC bit is set */
  166. while(!i2c_flag_get(i2c_periph, I2C_FLAG_BTC));
  167. }
  168. /* send a stop condition to I2C bus */
  169. i2c_stop_on_bus(i2c_periph);
  170. /* wait until the stop condition is finished */
  171. while(I2C_CTL0(i2c_periph)&0x0200);
  172. return 0;
  173. }
  174. static rt_size_t gd32_i2c_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num)
  175. {
  176. struct rt_i2c_msg *msg;
  177. rt_uint32_t i;
  178. rt_err_t ret = RT_ERROR;
  179. struct gd32_i2c_bus *gd32_i2c = (struct gd32_i2c_bus *)bus;
  180. for (i = 0; i < num; i++)
  181. {
  182. msg = &msgs[i];
  183. if (msg->flags & RT_I2C_ADDR_10BIT)
  184. {
  185. i2c_mode_addr_config(gd32_i2c->i2c_periph,I2C_I2CMODE_ENABLE,I2C_ADDFORMAT_10BITS,0);
  186. }
  187. else
  188. {
  189. i2c_mode_addr_config(gd32_i2c->i2c_periph,I2C_I2CMODE_ENABLE,I2C_ADDFORMAT_7BITS,0);
  190. }
  191. if (msg->flags & RT_I2C_RD)
  192. {
  193. if (gd32_i2c_read(gd32_i2c->i2c_periph, msg->addr, msg->buf, msg->len) != 0)
  194. {
  195. i2c_dbg("i2c bus write failed,i2c bus stop!\n");
  196. goto out;
  197. }
  198. }
  199. else
  200. {
  201. if (gd32_i2c_write(gd32_i2c->i2c_periph, msg->addr, msg->buf, msg->len) != 0)
  202. {
  203. i2c_dbg("i2c bus write failed,i2c bus stop!\n");
  204. goto out;
  205. }
  206. }
  207. }
  208. ret = i;
  209. out:
  210. i2c_dbg("send stop condition\n");
  211. return ret;
  212. }
  213. static const struct rt_i2c_bus_device_ops i2c_ops =
  214. {
  215. gd32_i2c_xfer,
  216. RT_NULL,
  217. RT_NULL
  218. };
  219. #endif /* RT_USING_I2C_BITOPS */
  220. int rt_hw_i2c_init(void)
  221. {
  222. #ifdef RT_USING_I2C_BITOPS
  223. {
  224. static struct rt_i2c_bus_device i2c_device;
  225. static const struct gd32_i2c_bit_data _i2c_bdata =
  226. {
  227. /* SCL */
  228. { I2C_SCL_CLK, I2C_SCL_PORT, I2C_SCL_PIN},
  229. /* SDA */
  230. { I2C_SDA_CLK, I2C_SDA_PORT, I2C_SDA_PIN},
  231. };
  232. static const struct rt_i2c_bit_ops _i2c_bit_ops =
  233. {
  234. (void*)&_i2c_bdata,
  235. gpio_set_sda,
  236. gpio_set_scl,
  237. gpio_get_sda,
  238. gpio_get_scl,
  239. gpio_udelay,
  240. 1,
  241. 100
  242. };
  243. drv_i2c_gpio_init(&_i2c_bdata);
  244. i2c_device.priv = (void *)&_i2c_bit_ops;
  245. rt_i2c_bit_add_bus(&i2c_device, I2C_BUS_NAME);
  246. }
  247. #else /* register hardware I2C */
  248. #ifdef RT_USING_I2C0
  249. #define I2C0_SPEED 100000
  250. static struct gd32_i2c_bus gd32_i2c0;
  251. /* enable GPIOB clock */
  252. rcu_periph_clock_enable(RCU_GPIOB);
  253. /* connect PB6 to I2C0_SCL */
  254. gpio_af_set(GPIOB, GPIO_AF_1, GPIO_PIN_6);
  255. /* connect PB7 to I2C0_SDA */
  256. gpio_af_set(GPIOB, GPIO_AF_1, GPIO_PIN_7);
  257. /* configure GPIO pins of I2C0 */
  258. gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_PULLUP,GPIO_PIN_6);
  259. gpio_output_options_set(GPIOB, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ,GPIO_PIN_6);
  260. gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_PULLUP,GPIO_PIN_7);
  261. gpio_output_options_set(GPIOB, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ,GPIO_PIN_7);
  262. /* enable I2C clock */
  263. rcu_periph_clock_enable(RCU_I2C0);
  264. /* configure I2C clock */
  265. i2c_clock_config(I2C0,I2C0_SPEED,I2C_DTCY_2);
  266. i2c_enable(I2C0);
  267. /* enable acknowledge */
  268. i2c_ack_config(I2C0,I2C_ACK_ENABLE);
  269. rt_memset((void *)&gd32_i2c0, 0, sizeof(struct gd32_i2c_bus));
  270. gd32_i2c0.parent.ops = &i2c_ops;
  271. gd32_i2c0.i2c_periph = I2C0;
  272. rt_i2c_bus_device_register(&gd32_i2c0.parent, "i2c0");
  273. #endif
  274. #ifdef RT_USING_I2C1
  275. #define I2C1_SPEED 100000
  276. static struct gd32_i2c_bus gd32_i2c1;
  277. /* enable GPIOB clock */
  278. rcu_periph_clock_enable(RCU_GPIOB);
  279. /* connect PB10 to I2C1_SCL */
  280. gpio_af_set(GPIOB, GPIO_AF_1, GPIO_PIN_10);
  281. /* connect PB11 to I2C1_SDA */
  282. gpio_af_set(GPIOB, GPIO_AF_1, GPIO_PIN_11);
  283. /* configure GPIO pins of I2C1 */
  284. gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_PULLUP,GPIO_PIN_10);
  285. gpio_output_options_set(GPIOB, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ,GPIO_PIN_10);
  286. gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_PULLUP,GPIO_PIN_11);
  287. gpio_output_options_set(GPIOB, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ,GPIO_PIN_11);
  288. /* enable I2C clock */
  289. rcu_periph_clock_enable(RCU_I2C1);
  290. /* configure I2C clock */
  291. i2c_clock_config(I2C1,I2C1_SPEED,I2C_DTCY_2);
  292. i2c_enable(I2C1);
  293. /* enable acknowledge */
  294. i2c_ack_config(I2C1,I2C_ACK_ENABLE);
  295. rt_memset((void *)&gd32_i2c1, 0, sizeof(struct gd32_i2c_bus));
  296. gd32_i2c1.parent.ops = &i2c_ops;
  297. gd32_i2c1.i2c_periph = I2C1;
  298. rt_i2c_bus_device_register(&gd32_i2c1.parent, "i2c1");
  299. #endif
  300. #endif /* RT_USING_I2C_BITOPS */
  301. return 0;
  302. }
  303. INIT_DEVICE_EXPORT(rt_hw_i2c_init);
  304. #endif
  305. /* end of i2c driver */