serial.c 8.6 KB

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  1. /*
  2. * Copyright (c) 2006-2018, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2006-08-23 Bernard first version
  9. */
  10. #include <rthw.h>
  11. #include <rtthread.h>
  12. #include "lpc214x.h"
  13. #include "board.h"
  14. /* serial hardware register */
  15. #define REG8(d) (*((volatile unsigned char *)(d)))
  16. #define REG32(d) (*((volatile unsigned long *)(d)))
  17. #define UART_RBR(base) REG8(base + 0x00)
  18. #define UART_THR(base) REG8(base + 0x00)
  19. #define UART_IER(base) REG32(base + 0x04)
  20. #define UART_IIR(base) REG32(base + 0x08)
  21. #define UART_FCR(base) REG8(base + 0x08)
  22. #define UART_LCR(base) REG8(base + 0x0C)
  23. #define UART_MCR(base) REG8(base + 0x10)
  24. #define UART_LSR(base) REG8(base + 0x14)
  25. #define UART_MSR(base) REG8(base + 0x18)
  26. #define UART_SCR(base) REG8(base + 0x1C)
  27. #define UART_DLL(base) REG8(base + 0x00)
  28. #define UART_DLM(base) REG8(base + 0x04)
  29. #define UART_ACR(base) REG32(base + 0x20)
  30. #define UART_FDR(base) REG32(base + 0x28)
  31. #define UART_TER(base) REG8(base + 0x30)
  32. /* LPC serial device */
  33. struct rt_lpcserial
  34. {
  35. /* inherit from device */
  36. struct rt_device parent;
  37. rt_uint32_t hw_base;
  38. rt_uint32_t irqno;
  39. rt_uint32_t baudrate;
  40. /* reception field */
  41. rt_uint16_t save_index, read_index;
  42. rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
  43. };
  44. #ifdef RT_USING_UART1
  45. struct rt_lpcserial serial1;
  46. #endif
  47. #ifdef RT_USING_UART2
  48. struct rt_lpcserial serial2;
  49. #endif
  50. void rt_hw_serial_init(void);
  51. #define U0PINS 0x00000005
  52. void rt_hw_uart_isr(struct rt_lpcserial* lpc_serial)
  53. {
  54. RT_UNUSED rt_uint32_t iir;
  55. RT_ASSERT(lpc_serial != RT_NULL)
  56. if (UART_LSR(lpc_serial->hw_base) & 0x01)
  57. {
  58. rt_base_t level;
  59. while (UART_LSR(lpc_serial->hw_base) & 0x01)
  60. {
  61. /* disable interrupt */
  62. level = rt_hw_interrupt_disable();
  63. /* read character */
  64. lpc_serial->rx_buffer[lpc_serial->save_index] =
  65. UART_RBR(lpc_serial->hw_base);
  66. lpc_serial->save_index ++;
  67. if (lpc_serial->save_index >= RT_UART_RX_BUFFER_SIZE)
  68. lpc_serial->save_index = 0;
  69. /* if the next position is read index, discard this 'read char' */
  70. if (lpc_serial->save_index == lpc_serial->read_index)
  71. {
  72. lpc_serial->read_index ++;
  73. if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE)
  74. lpc_serial->read_index = 0;
  75. }
  76. /* enable interrupt */
  77. rt_hw_interrupt_enable(level);
  78. }
  79. /* invoke callback */
  80. if(lpc_serial->parent.rx_indicate != RT_NULL)
  81. {
  82. lpc_serial->parent.rx_indicate(&lpc_serial->parent, 1);
  83. }
  84. }
  85. /* clear interrupt source */
  86. iir = UART_IIR(lpc_serial->hw_base);
  87. /* acknowledge Interrupt */
  88. VICVectAddr = 0;
  89. }
  90. #ifdef RT_USING_UART1
  91. void rt_hw_uart_isr_1(int irqno, void *param)
  92. {
  93. /* get lpc serial device */
  94. rt_hw_uart_isr(&serial1);
  95. }
  96. #endif
  97. #ifdef RT_USING_UART2
  98. void rt_hw_uart_isr_2(int irqno, void *param)
  99. {
  100. /* get lpc serial device */
  101. rt_hw_uart_isr(&serial2);
  102. }
  103. #endif
  104. /**
  105. * @addtogroup LPC214x
  106. */
  107. /*@{*/
  108. static rt_err_t rt_serial_init (rt_device_t dev)
  109. {
  110. return RT_EOK;
  111. }
  112. static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
  113. {
  114. struct rt_lpcserial* lpc_serial;
  115. lpc_serial = (struct rt_lpcserial*) dev;
  116. RT_ASSERT(lpc_serial != RT_NULL);
  117. if (dev->flag & RT_DEVICE_FLAG_INT_RX)
  118. {
  119. /* init UART rx interrupt */
  120. UART_IER(lpc_serial->hw_base) = 0x01;
  121. /* install ISR */
  122. if (lpc_serial->irqno == UART0_INT)
  123. {
  124. #ifdef RT_USING_UART1
  125. rt_hw_interrupt_install(lpc_serial->irqno,
  126. rt_hw_uart_isr_1, &serial1, "UART1");
  127. #endif
  128. }
  129. else
  130. {
  131. #ifdef RT_USING_UART2
  132. rt_hw_interrupt_install(lpc_serial->irqno,
  133. rt_hw_uart_isr_2, &serial2, "UART2");
  134. #endif
  135. }
  136. rt_hw_interrupt_umask(lpc_serial->irqno);
  137. }
  138. return RT_EOK;
  139. }
  140. static rt_err_t rt_serial_close(rt_device_t dev)
  141. {
  142. struct rt_lpcserial* lpc_serial;
  143. lpc_serial = (struct rt_lpcserial*) dev;
  144. RT_ASSERT(lpc_serial != RT_NULL);
  145. if (dev->flag & RT_DEVICE_FLAG_INT_RX)
  146. {
  147. /* disable UART rx interrupt */
  148. UART_IER(lpc_serial->hw_base) = 0x00;
  149. }
  150. return RT_EOK;
  151. }
  152. static rt_err_t rt_serial_control(rt_device_t dev, int cmd, void *args)
  153. {
  154. return RT_EOK;
  155. }
  156. static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
  157. {
  158. rt_uint8_t* ptr;
  159. struct rt_lpcserial *lpc_serial = (struct rt_lpcserial*)dev;
  160. RT_ASSERT(lpc_serial != RT_NULL);
  161. /* point to buffer */
  162. ptr = (rt_uint8_t*) buffer;
  163. if (dev->flag & RT_DEVICE_FLAG_INT_RX)
  164. {
  165. while (size)
  166. {
  167. /* interrupt receive */
  168. rt_base_t level;
  169. /* disable interrupt */
  170. level = rt_hw_interrupt_disable();
  171. if (lpc_serial->read_index != lpc_serial->save_index)
  172. {
  173. *ptr = lpc_serial->rx_buffer[lpc_serial->read_index];
  174. lpc_serial->read_index ++;
  175. if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE)
  176. lpc_serial->read_index = 0;
  177. }
  178. else
  179. {
  180. /* no data in rx buffer */
  181. /* enable interrupt */
  182. rt_hw_interrupt_enable(level);
  183. break;
  184. }
  185. /* enable interrupt */
  186. rt_hw_interrupt_enable(level);
  187. ptr ++; size --;
  188. }
  189. return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
  190. }
  191. else if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
  192. {
  193. /* not support right now */
  194. RT_ASSERT(0);
  195. }
  196. /* polling mode */
  197. while (size && (UART_LSR(lpc_serial->hw_base) & 0x01))
  198. {
  199. /* Read Character */
  200. *ptr = UART_RBR(lpc_serial->hw_base);
  201. ptr ++;
  202. size --;
  203. }
  204. return (rt_size_t)ptr - (rt_size_t)buffer;
  205. }
  206. static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
  207. {
  208. struct rt_lpcserial* lpc_serial;
  209. char *ptr;
  210. lpc_serial = (struct rt_lpcserial*) dev;
  211. if (dev->flag & RT_DEVICE_FLAG_INT_TX)
  212. {
  213. /* not support */
  214. RT_ASSERT(0);
  215. }
  216. else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
  217. {
  218. /* not support */
  219. RT_ASSERT(0);
  220. }
  221. /* polling write */
  222. ptr = (char *)buffer;
  223. if (dev->flag & RT_DEVICE_FLAG_STREAM)
  224. {
  225. /* stream mode */
  226. while (size)
  227. {
  228. if (*ptr == '\n')
  229. {
  230. while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
  231. UART_THR(lpc_serial->hw_base) = '\r';
  232. }
  233. while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
  234. UART_THR(lpc_serial->hw_base) = *ptr;
  235. ptr ++;
  236. size --;
  237. }
  238. }
  239. else
  240. {
  241. while (size)
  242. {
  243. while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
  244. UART_THR(lpc_serial->hw_base) = *ptr;
  245. ptr ++;
  246. size --;
  247. }
  248. }
  249. return (rt_size_t) ptr - (rt_size_t) buffer;
  250. }
  251. void rt_hw_serial_init(void)
  252. {
  253. struct rt_lpcserial* lpc_serial;
  254. #ifdef RT_USING_UART1
  255. lpc_serial = &serial1;
  256. lpc_serial->parent.type = RT_Device_Class_Char;
  257. lpc_serial->hw_base = 0xE000C000;
  258. lpc_serial->baudrate = 115200;
  259. lpc_serial->irqno = UART0_INT;
  260. rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer));
  261. lpc_serial->read_index = lpc_serial->save_index = 0;
  262. /* Enable UART0 RxD and TxD pins */
  263. PINSEL0 |= 0x05;
  264. /* 8 bits, no Parity, 1 Stop bit */
  265. UART_LCR(lpc_serial->hw_base) = 0x83;
  266. /* Setup Baudrate */
  267. UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF;
  268. UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF;
  269. /* DLAB = 0 */
  270. UART_LCR(lpc_serial->hw_base) = 0x03;
  271. lpc_serial->parent.type = RT_Device_Class_Char;
  272. lpc_serial->parent.init = rt_serial_init;
  273. lpc_serial->parent.open = rt_serial_open;
  274. lpc_serial->parent.close = rt_serial_close;
  275. lpc_serial->parent.read = rt_serial_read;
  276. lpc_serial->parent.write = rt_serial_write;
  277. lpc_serial->parent.control = rt_serial_control;
  278. lpc_serial->parent.user_data = RT_NULL;
  279. rt_device_register(&lpc_serial->parent,
  280. "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
  281. #endif
  282. #ifdef RT_USING_UART2
  283. lpc_serial = &serial2;
  284. lpc_serial->parent.type = RT_Device_Class_Char;
  285. lpc_serial->hw_base = 0xE0010000;
  286. lpc_serial->baudrate = 115200;
  287. lpc_serial->irqno = UART1_INT;
  288. rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer));
  289. lpc_serial->read_index = lpc_serial->save_index = 0;
  290. /* Enable UART1 RxD and TxD pins */
  291. PINSEL0 |= 0x05 << 16;
  292. /* 8 bits, no Parity, 1 Stop bit */
  293. UART_LCR(lpc_serial->hw_base) = 0x83;
  294. /* Setup Baudrate */
  295. UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF;
  296. UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF;
  297. /* DLAB = 0 */
  298. UART_LCR(lpc_serial->hw_base) = 0x03;
  299. lpc_serial->parent.type = RT_Device_Class_Char;
  300. lpc_serial->parent.init = rt_serial_init;
  301. lpc_serial->parent.open = rt_serial_open;
  302. lpc_serial->parent.close = rt_serial_close;
  303. lpc_serial->parent.read = rt_serial_read;
  304. lpc_serial->parent.write = rt_serial_write;
  305. lpc_serial->parent.control = rt_serial_control;
  306. lpc_serial->parent.user_data = RT_NULL;
  307. rt_device_register(&lpc_serial->parent,
  308. "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
  309. #endif
  310. }
  311. /*@}*/