synopGMAC_plat.h 6.5 KB

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  1. /*
  2. * Copyright (c) 2006-2018, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2017-08-24 chinesebear first version
  9. */
  10. #ifndef SYNOP_GMAC_PLAT_H
  11. #define SYNOP_GMAC_PLAT_H 1
  12. /* sw
  13. #include <linux/kernel.h>
  14. #include <asm/io.h>
  15. #include <linux/gfp.h>
  16. #include <linux/slab.h>
  17. #include <linux/pci.h>
  18. */
  19. #include "synopGMAC_types.h"
  20. #include "synopGMAC_debug.h"
  21. //#include "mii.h"
  22. //#include "GMAC_Pmon.h"
  23. //#include "synopGMAC_Host.h"
  24. #include <rtthread.h>
  25. //sw: copy the type define into here
  26. #define IOCTL_READ_REGISTER SIOCDEVPRIVATE+1
  27. #define IOCTL_WRITE_REGISTER SIOCDEVPRIVATE+2
  28. #define IOCTL_READ_IPSTRUCT SIOCDEVPRIVATE+3
  29. #define IOCTL_READ_RXDESC SIOCDEVPRIVATE+4
  30. #define IOCTL_READ_TXDESC SIOCDEVPRIVATE+5
  31. #define IOCTL_POWER_DOWN SIOCDEVPRIVATE+6
  32. #define SYNOP_GMAC0 1
  33. typedef int bool;
  34. //typedef unsigned long dma_addr_t;
  35. //sw
  36. /* write/read MMIO register */
  37. #define writeb(val, addr) (*(volatile u8*)(addr) = (val))
  38. #define writew(val, addr) (*(volatile u16*)(addr) = (val))
  39. #define writel(val, addr) (*(volatile u32*)(addr) = (val))
  40. #define readb(addr) (*(volatile u8*)(addr))
  41. #define readw(addr) (*(volatile u16*)(addr))
  42. #define readl(addr) (*(volatile u32*)(addr))
  43. #define KUSEG_ADDR 0x0
  44. #define CACHED_MEMORY_ADDR 0x80000000
  45. #define UNCACHED_MEMORY_ADDR 0xa0000000
  46. #define KSEG2_ADDR 0xc0000000
  47. #define MAX_MEM_ADDR 0xbe000000
  48. #define RESERVED_ADDR 0xbfc80000
  49. #define CACHED_TO_PHYS(x) ((unsigned)(x) & 0x7fffffff)
  50. #define PHYS_TO_CACHED(x) ((unsigned)(x) | CACHED_MEMORY_ADDR)
  51. #define UNCACHED_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff)
  52. #define PHYS_TO_UNCACHED(x) ((unsigned)(x) | UNCACHED_MEMORY_ADDR)
  53. #define VA_TO_CINDEX(x) ((unsigned)(x) & 0xffffff | CACHED_MEMORY_ADDR)
  54. #define CACHED_TO_UNCACHED(x) (PHYS_TO_UNCACHED(CACHED_TO_PHYS(x)))
  55. #define VA_TO_PA(x) UNCACHED_TO_PHYS(x)
  56. /* sw
  57. #define TR0(fmt, args...) printk(KERN_CRIT "SynopGMAC: " fmt, ##args)
  58. #ifdef DEBUG
  59. #undef TR
  60. # define TR(fmt, args...) printk(KERN_CRIT "SynopGMAC: " fmt, ##args)
  61. #else
  62. # define TR(fmt, args...) // not debugging: nothing
  63. #endif
  64. */
  65. /*
  66. #define TR0(fmt, args...) printf("SynopGMAC: " fmt, ##args)
  67. */
  68. /*
  69. #ifdef DEBUG
  70. #undef TR
  71. # define TR(fmt, args...) printf("SynopGMAC: " fmt, ##args)
  72. #else
  73. //# define TR(fmt, args...) // not debugging: nothing
  74. #define TR(fmt, args...) printf("SynopGMAC: " fmt, ##args)
  75. #endif
  76. */
  77. //sw: nothing to display
  78. #define TR0(fmt, args...) //rt_kprintf(fmt, ##args)
  79. #define TR(fmt, args...) //rt_kprintf(fmt, ##args)
  80. //#define TR rt_kprintf
  81. //typedef int bool;
  82. enum synopGMAC_boolean
  83. {
  84. false = 0,
  85. true = 1
  86. };
  87. #define DEFAULT_DELAY_VARIABLE 10
  88. #define DEFAULT_LOOP_VARIABLE 10000
  89. /* There are platform related endian conversions
  90. *
  91. */
  92. #define LE32_TO_CPU __le32_to_cpu
  93. #define BE32_TO_CPU __be32_to_cpu
  94. #define CPU_TO_LE32 __cpu_to_le32
  95. /* Error Codes */
  96. #define ESYNOPGMACNOERR 0
  97. #define ESYNOPGMACNOMEM 1
  98. #define ESYNOPGMACPHYERR 2
  99. #define ESYNOPGMACBUSY 3
  100. struct Network_interface_data
  101. {
  102. u32 unit;
  103. u32 addr;
  104. u32 data;
  105. };
  106. /**
  107. * These are the wrapper function prototypes for OS/platform related routines
  108. */
  109. void * plat_alloc_memory(u32 );
  110. void plat_free_memory(void *);
  111. //void * plat_alloc_consistent_dmaable_memory(struct pci_dev *, u32, u32 *);
  112. //void plat_free_consistent_dmaable_memory (struct pci_dev *, u32, void *, u32);
  113. void plat_delay(u32);
  114. /**
  115. * The Low level function to read register contents from Hardware.
  116. *
  117. * @param[in] pointer to the base of register map
  118. * @param[in] Offset from the base
  119. * \return Returns the register contents
  120. */
  121. static u32 synopGMACReadReg(u32 RegBase, u32 RegOffset)
  122. {
  123. u32 addr;
  124. u32 data;
  125. addr = RegBase + (u32)RegOffset;
  126. data = *(volatile u32 *)addr;
  127. #if SYNOP_REG_DEBUG
  128. TR("%s RegBase = 0x%08x RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, (u32)RegBase, RegOffset, data );
  129. #endif
  130. // rt_kprintf("%s RegBase = 0x%08x RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, (u32)RegBase, RegOffset, data );
  131. return data;
  132. }
  133. /**
  134. * The Low level function to write to a register in Hardware.
  135. *
  136. * @param[in] pointer to the base of register map
  137. * @param[in] Offset from the base
  138. * @param[in] Data to be written
  139. * \return void
  140. */
  141. static void synopGMACWriteReg(u32 RegBase, u32 RegOffset, u32 RegData )
  142. {
  143. u32 addr;
  144. addr = RegBase + (u32)RegOffset;
  145. // rt_kprintf("%s RegBase = 0x%08x RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__,(u32) RegBase, RegOffset, RegData );
  146. #if SYNOP_REG_DEBUG
  147. TR("%s RegBase = 0x%08x RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__,(u32) RegBase, RegOffset, RegData );
  148. #endif
  149. *(volatile u32 *)addr = RegData;
  150. if(addr == 0xbfe1100c)
  151. DEBUG_MES("regdata = %08x\n", RegData);
  152. return;
  153. }
  154. /**
  155. * The Low level function to set bits of a register in Hardware.
  156. *
  157. * @param[in] pointer to the base of register map
  158. * @param[in] Offset from the base
  159. * @param[in] Bit mask to set bits to logical 1
  160. * \return void
  161. */
  162. static void synopGMACSetBits(u32 RegBase, u32 RegOffset, u32 BitPos)
  163. {
  164. //u64 addr = (u64)RegBase + (u64)RegOffset;
  165. u32 data;
  166. data = synopGMACReadReg(RegBase, RegOffset);
  167. data |= BitPos;
  168. synopGMACWriteReg(RegBase, RegOffset, data);
  169. // writel(data,(void *)addr);
  170. #if SYNOP_REG_DEBUG
  171. TR("%s !!!!!!!!!!!!! RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, RegOffset, data );
  172. #endif
  173. return;
  174. }
  175. /**
  176. * The Low level function to clear bits of a register in Hardware.
  177. *
  178. * @param[in] pointer to the base of register map
  179. * @param[in] Offset from the base
  180. * @param[in] Bit mask to clear bits to logical 0
  181. * \return void
  182. */
  183. static void synopGMACClearBits(u32 RegBase, u32 RegOffset, u32 BitPos)
  184. {
  185. u32 data;
  186. data = synopGMACReadReg(RegBase, RegOffset);
  187. data &= (~BitPos);
  188. synopGMACWriteReg(RegBase, RegOffset, data);
  189. #if SYNOP_REG_DEBUG
  190. TR("%s !!!!!!!!!!!!! RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, RegOffset, data );
  191. #endif
  192. return;
  193. }
  194. /**
  195. * The Low level function to Check the setting of the bits.
  196. *
  197. * @param[in] pointer to the base of register map
  198. * @param[in] Offset from the base
  199. * @param[in] Bit mask to set bits to logical 1
  200. * \return returns TRUE if set to '1' returns FALSE if set to '0'. Result undefined there are no bit set in the BitPos argument.
  201. *
  202. */
  203. static bool synopGMACCheckBits(u32 RegBase, u32 RegOffset, u32 BitPos)
  204. {
  205. u32 data;
  206. data = synopGMACReadReg(RegBase, RegOffset);
  207. data &= BitPos;
  208. if(data) return true;
  209. else return false;
  210. }
  211. #endif