drv_gpio.c 13 KB

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  1. /*
  2. * Copyright (c) 2006-2018, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2019-04-02 henryhuang the first version
  9. */
  10. #include <rtthread.h>
  11. #include <rtdevice.h>
  12. #include <board.h>
  13. #include <rthw.h>
  14. #define MM32_PIN(index, rcc, gpio, gpio_index) { 0, RCC_##rcc##Periph_GPIO##gpio, GPIO##gpio, GPIO_Pin_##gpio_index, GPIO_PortSourceGPIO##gpio, GPIO_PinSource##gpio_index}
  15. #define MM32_PIN_DEFAULT {-1, 0, 0, 0, 0, 0}
  16. /* MM32 GPIO driver */
  17. struct pin_index
  18. {
  19. int index;
  20. uint32_t rcc;
  21. GPIO_TypeDef *gpio;
  22. uint32_t pin;
  23. uint8_t port_source;
  24. uint8_t pin_source;
  25. };
  26. static const struct pin_index mm32_pin_map[] =
  27. {
  28. MM32_PIN_DEFAULT,
  29. MM32_PIN_DEFAULT,
  30. MM32_PIN(2, APB2, C, 13),
  31. MM32_PIN(3, APB2, C, 14),
  32. MM32_PIN(4, APB2, C, 15),
  33. MM32_PIN_DEFAULT,
  34. MM32_PIN_DEFAULT,
  35. MM32_PIN_DEFAULT,
  36. MM32_PIN_DEFAULT,
  37. MM32_PIN_DEFAULT,
  38. MM32_PIN(10, APB2, A, 0),
  39. MM32_PIN(11, APB2, A, 1),
  40. MM32_PIN(12, APB2, A, 2),
  41. MM32_PIN(13, APB2, A, 3),
  42. MM32_PIN(14, APB2, A, 4),
  43. MM32_PIN(15, APB2, A, 5),
  44. MM32_PIN(16, APB2, A, 6),
  45. MM32_PIN(17, APB2, A, 7),
  46. MM32_PIN(18, APB2, B, 0),
  47. MM32_PIN(19, APB2, B, 1),
  48. MM32_PIN(20, APB2, B, 2),
  49. MM32_PIN(21, APB2, B, 10),
  50. MM32_PIN(22, APB2, B, 11),
  51. MM32_PIN_DEFAULT,
  52. MM32_PIN_DEFAULT,
  53. MM32_PIN(25, APB2, B, 12),
  54. MM32_PIN(26, APB2, B, 13),
  55. MM32_PIN(27, APB2, B, 14),
  56. MM32_PIN(28, APB2, B, 15),
  57. MM32_PIN(29, APB2, A, 8),
  58. MM32_PIN(30, APB2, A, 9),
  59. MM32_PIN(31, APB2, A, 10),
  60. MM32_PIN(32, APB2, A, 11),
  61. MM32_PIN(33, APB2, A, 12),
  62. MM32_PIN(34, APB2, A, 13),
  63. MM32_PIN_DEFAULT,
  64. MM32_PIN_DEFAULT,
  65. MM32_PIN(37, APB2, A, 14),
  66. MM32_PIN(38, APB2, A, 15),
  67. MM32_PIN(39, APB2, B, 3),
  68. MM32_PIN(40, APB2, B, 4),
  69. MM32_PIN(41, APB2, B, 5),
  70. MM32_PIN(42, APB2, B, 6),
  71. MM32_PIN(43, APB2, B, 7),
  72. MM32_PIN_DEFAULT,
  73. MM32_PIN(45, APB2, B, 8),
  74. MM32_PIN(46, APB2, B, 9),
  75. MM32_PIN_DEFAULT,
  76. MM32_PIN_DEFAULT,
  77. };
  78. struct pin_irq_map
  79. {
  80. rt_uint16_t pinbit;
  81. rt_uint32_t irqbit;
  82. enum IRQn irqno;
  83. };
  84. const struct pin_irq_map mm32_pin_irq_map[] =
  85. {
  86. {GPIO_Pin_0, EXTI_Line0, EXTI0_IRQn },
  87. {GPIO_Pin_1, EXTI_Line1, EXTI1_IRQn },
  88. {GPIO_Pin_2, EXTI_Line2, EXTI2_IRQn },
  89. {GPIO_Pin_3, EXTI_Line3, EXTI3_IRQn },
  90. {GPIO_Pin_4, EXTI_Line4, EXTI4_IRQn },
  91. {GPIO_Pin_5, EXTI_Line5, EXTI9_5_IRQn },
  92. {GPIO_Pin_6, EXTI_Line6, EXTI9_5_IRQn },
  93. {GPIO_Pin_7, EXTI_Line7, EXTI9_5_IRQn },
  94. {GPIO_Pin_8, EXTI_Line8, EXTI9_5_IRQn },
  95. {GPIO_Pin_9, EXTI_Line9, EXTI9_5_IRQn },
  96. {GPIO_Pin_10, EXTI_Line10, EXTI15_10_IRQn},
  97. {GPIO_Pin_11, EXTI_Line11, EXTI15_10_IRQn},
  98. {GPIO_Pin_12, EXTI_Line12, EXTI15_10_IRQn},
  99. {GPIO_Pin_13, EXTI_Line13, EXTI15_10_IRQn},
  100. {GPIO_Pin_14, EXTI_Line14, EXTI15_10_IRQn},
  101. {GPIO_Pin_15, EXTI_Line15, EXTI15_10_IRQn},
  102. };
  103. struct rt_pin_irq_hdr mm32_pin_irq_hdr_tab[] =
  104. {
  105. {-1, 0, RT_NULL, RT_NULL},
  106. {-1, 0, RT_NULL, RT_NULL},
  107. {-1, 0, RT_NULL, RT_NULL},
  108. {-1, 0, RT_NULL, RT_NULL},
  109. {-1, 0, RT_NULL, RT_NULL},
  110. {-1, 0, RT_NULL, RT_NULL},
  111. {-1, 0, RT_NULL, RT_NULL},
  112. {-1, 0, RT_NULL, RT_NULL},
  113. {-1, 0, RT_NULL, RT_NULL},
  114. {-1, 0, RT_NULL, RT_NULL},
  115. {-1, 0, RT_NULL, RT_NULL},
  116. {-1, 0, RT_NULL, RT_NULL},
  117. {-1, 0, RT_NULL, RT_NULL},
  118. {-1, 0, RT_NULL, RT_NULL},
  119. {-1, 0, RT_NULL, RT_NULL},
  120. {-1, 0, RT_NULL, RT_NULL},
  121. };
  122. #define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
  123. const struct pin_index *get_pin(uint8_t pin)
  124. {
  125. const struct pin_index *index;
  126. if (pin < ITEM_NUM(mm32_pin_map))
  127. {
  128. index = &mm32_pin_map[pin];
  129. if (index->gpio == 0)
  130. index = RT_NULL;
  131. }
  132. else
  133. {
  134. index = RT_NULL;
  135. }
  136. return index;
  137. };
  138. void mm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
  139. {
  140. const struct pin_index *index;
  141. index = get_pin(pin);
  142. if (index == RT_NULL)
  143. {
  144. return;
  145. }
  146. if (value == PIN_LOW)
  147. {
  148. GPIO_ResetBits(index->gpio, index->pin);
  149. }
  150. else
  151. {
  152. GPIO_SetBits(index->gpio, index->pin);
  153. }
  154. }
  155. int mm32_pin_read(rt_device_t dev, rt_base_t pin)
  156. {
  157. int value;
  158. const struct pin_index *index;
  159. value = PIN_LOW;
  160. index = get_pin(pin);
  161. if (index == RT_NULL)
  162. {
  163. return PIN_LOW;
  164. }
  165. if (GPIO_ReadInputDataBit(index->gpio, index->pin) == Bit_RESET)
  166. {
  167. value = PIN_LOW;
  168. }
  169. else
  170. {
  171. value = PIN_HIGH;
  172. }
  173. return value;
  174. }
  175. void mm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
  176. {
  177. const struct pin_index *index;
  178. GPIO_InitTypeDef GPIO_InitStructure;
  179. index = get_pin(pin);
  180. if (index == RT_NULL)
  181. {
  182. return;
  183. }
  184. /* GPIO Periph clock enable */
  185. RCC_APB2PeriphClockCmd(index->rcc, ENABLE);
  186. /* Configure GPIO_InitStructure */
  187. GPIO_InitStructure.GPIO_Pin = index->pin;
  188. GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
  189. GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
  190. if (mode == PIN_MODE_OUTPUT)
  191. {
  192. /* output setting */
  193. GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
  194. }
  195. else if (mode == PIN_MODE_OUTPUT_OD)
  196. {
  197. /* output setting: od. */
  198. GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD;
  199. }
  200. else if (mode == PIN_MODE_INPUT)
  201. {
  202. /* input setting: not pull. */
  203. GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
  204. }
  205. else if (mode == PIN_MODE_INPUT_PULLUP)
  206. {
  207. /* input setting: pull up. */
  208. GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
  209. }
  210. else
  211. {
  212. /* input setting:default. */
  213. GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
  214. }
  215. GPIO_Init( index->gpio, &GPIO_InitStructure);
  216. }
  217. rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
  218. {
  219. int i;
  220. for (i = 0; i < 32; i++)
  221. {
  222. if ((0x01 << i) == bit)
  223. {
  224. return i;
  225. }
  226. }
  227. return -1;
  228. }
  229. rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
  230. {
  231. rt_int32_t mapindex = bit2bitno(pinbit);
  232. if (mapindex < 0 || mapindex >= ITEM_NUM(mm32_pin_irq_map))
  233. {
  234. return RT_NULL;
  235. }
  236. return &mm32_pin_irq_map[mapindex];
  237. };
  238. rt_err_t mm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
  239. rt_uint32_t mode, void (*hdr)(void *args), void *args)
  240. {
  241. const struct pin_index *index;
  242. rt_base_t level;
  243. rt_int32_t irqindex = -1;
  244. index = get_pin(pin);
  245. if (index == RT_NULL)
  246. {
  247. return -RT_ENOSYS;
  248. }
  249. irqindex = bit2bitno(index->pin);
  250. if (irqindex < 0 || irqindex >= ITEM_NUM(mm32_pin_irq_map))
  251. {
  252. return -RT_ENOSYS;
  253. }
  254. level = rt_hw_interrupt_disable();
  255. if (mm32_pin_irq_hdr_tab[irqindex].pin == pin &&
  256. mm32_pin_irq_hdr_tab[irqindex].hdr == hdr &&
  257. mm32_pin_irq_hdr_tab[irqindex].mode == mode &&
  258. mm32_pin_irq_hdr_tab[irqindex].args == args
  259. )
  260. {
  261. rt_hw_interrupt_enable(level);
  262. return RT_EOK;
  263. }
  264. if (mm32_pin_irq_hdr_tab[irqindex].pin != -1)
  265. {
  266. rt_hw_interrupt_enable(level);
  267. return -RT_EBUSY;
  268. }
  269. mm32_pin_irq_hdr_tab[irqindex].pin = pin;
  270. mm32_pin_irq_hdr_tab[irqindex].hdr = hdr;
  271. mm32_pin_irq_hdr_tab[irqindex].mode = mode;
  272. mm32_pin_irq_hdr_tab[irqindex].args = args;
  273. rt_hw_interrupt_enable(level);
  274. return RT_EOK;
  275. }
  276. rt_err_t mm32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
  277. {
  278. const struct pin_index *index;
  279. rt_base_t level;
  280. rt_int32_t irqindex = -1;
  281. index = get_pin(pin);
  282. if (index == RT_NULL)
  283. {
  284. return RT_ENOSYS;
  285. }
  286. irqindex = bit2bitno(index->pin);
  287. if (irqindex < 0 || irqindex >= ITEM_NUM(mm32_pin_irq_map))
  288. {
  289. return RT_ENOSYS;
  290. }
  291. level = rt_hw_interrupt_disable();
  292. if (mm32_pin_irq_hdr_tab[irqindex].pin == -1)
  293. {
  294. rt_hw_interrupt_enable(level);
  295. return RT_EOK;
  296. }
  297. mm32_pin_irq_hdr_tab[irqindex].pin = -1;
  298. mm32_pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
  299. mm32_pin_irq_hdr_tab[irqindex].mode = 0;
  300. mm32_pin_irq_hdr_tab[irqindex].args = RT_NULL;
  301. rt_hw_interrupt_enable(level);
  302. return RT_EOK;
  303. }
  304. rt_err_t mm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
  305. rt_uint32_t enabled)
  306. {
  307. const struct pin_index *index;
  308. const struct pin_irq_map *irqmap;
  309. rt_base_t level;
  310. rt_int32_t irqindex = -1;
  311. GPIO_InitTypeDef GPIO_InitStructure;
  312. NVIC_InitTypeDef NVIC_InitStructure;
  313. EXTI_InitTypeDef EXTI_InitStructure;
  314. index = get_pin(pin);
  315. if (index == RT_NULL)
  316. {
  317. return -RT_ENOSYS;
  318. }
  319. if (enabled == PIN_IRQ_ENABLE)
  320. {
  321. irqindex = bit2bitno(index->pin);
  322. if (irqindex < 0 || irqindex >= ITEM_NUM(mm32_pin_irq_map))
  323. {
  324. return -RT_ENOSYS;
  325. }
  326. level = rt_hw_interrupt_disable();
  327. if (mm32_pin_irq_hdr_tab[irqindex].pin == -1)
  328. {
  329. rt_hw_interrupt_enable(level);
  330. return -RT_ENOSYS;
  331. }
  332. irqmap = &mm32_pin_irq_map[irqindex];
  333. /* GPIO Periph clock enable */
  334. RCC_APB2PeriphClockCmd(index->rcc, ENABLE);
  335. /* Configure GPIO_InitStructure */
  336. GPIO_InitStructure.GPIO_Pin = index->pin;
  337. GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
  338. GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
  339. GPIO_Init(index->gpio, &GPIO_InitStructure);
  340. NVIC_InitStructure.NVIC_IRQChannel = irqmap->irqno;
  341. NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
  342. NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
  343. NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
  344. NVIC_Init(&NVIC_InitStructure);
  345. GPIO_EXTILineConfig(index->port_source, index->pin_source);
  346. EXTI_InitStructure.EXTI_Line = irqmap->irqbit;
  347. EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
  348. switch (mm32_pin_irq_hdr_tab[irqindex].mode)
  349. {
  350. case PIN_IRQ_MODE_RISING:
  351. EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
  352. break;
  353. case PIN_IRQ_MODE_FALLING:
  354. EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
  355. break;
  356. case PIN_IRQ_MODE_RISING_FALLING:
  357. EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
  358. break;
  359. }
  360. EXTI_InitStructure.EXTI_LineCmd = ENABLE;
  361. EXTI_Init(&EXTI_InitStructure);
  362. rt_hw_interrupt_enable(level);
  363. }
  364. else if (enabled == PIN_IRQ_DISABLE)
  365. {
  366. irqmap = get_pin_irq_map(index->pin);
  367. if (irqmap == RT_NULL)
  368. {
  369. return -RT_ENOSYS;
  370. }
  371. EXTI_InitStructure.EXTI_Line = irqmap->irqbit;
  372. EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
  373. EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
  374. EXTI_InitStructure.EXTI_LineCmd = DISABLE;
  375. EXTI_Init(&EXTI_InitStructure);
  376. }
  377. else
  378. {
  379. return -RT_ENOSYS;
  380. }
  381. return RT_EOK;
  382. }
  383. const static struct rt_pin_ops _mm32_pin_ops =
  384. {
  385. mm32_pin_mode,
  386. mm32_pin_write,
  387. mm32_pin_read,
  388. mm32_pin_attach_irq,
  389. mm32_pin_detach_irq,
  390. mm32_pin_irq_enable,
  391. };
  392. int rt_hw_pin_init(void)
  393. {
  394. int result;
  395. result = rt_device_pin_register("pin", &_mm32_pin_ops, RT_NULL);
  396. return result;
  397. }
  398. INIT_BOARD_EXPORT(rt_hw_pin_init);
  399. rt_inline void pin_irq_hdr(int irqno)
  400. {
  401. EXTI_ClearITPendingBit(mm32_pin_irq_map[irqno].irqbit);
  402. if (mm32_pin_irq_hdr_tab[irqno].hdr)
  403. {
  404. mm32_pin_irq_hdr_tab[irqno].hdr(mm32_pin_irq_hdr_tab[irqno].args);
  405. }
  406. }
  407. void EXTI0_IRQHandler(void)
  408. {
  409. /* enter interrupt */
  410. rt_interrupt_enter();
  411. pin_irq_hdr(0);
  412. /* leave interrupt */
  413. rt_interrupt_leave();
  414. }
  415. void EXTI1_IRQHandler(void)
  416. {
  417. /* enter interrupt */
  418. rt_interrupt_enter();
  419. pin_irq_hdr(1);
  420. /* leave interrupt */
  421. rt_interrupt_leave();
  422. }
  423. void EXTI2_IRQHandler(void)
  424. {
  425. /* enter interrupt */
  426. rt_interrupt_enter();
  427. pin_irq_hdr(2);
  428. /* leave interrupt */
  429. rt_interrupt_leave();
  430. }
  431. void EXTI3_IRQHandler(void)
  432. {
  433. /* enter interrupt */
  434. rt_interrupt_enter();
  435. pin_irq_hdr(3);
  436. /* leave interrupt */
  437. rt_interrupt_leave();
  438. }
  439. void EXTI4_IRQHandler(void)
  440. {
  441. /* enter interrupt */
  442. rt_interrupt_enter();
  443. pin_irq_hdr(4);
  444. /* leave interrupt */
  445. rt_interrupt_leave();
  446. }
  447. void EXTI9_5_IRQHandler(void)
  448. {
  449. /* enter interrupt */
  450. rt_interrupt_enter();
  451. if (EXTI_GetITStatus(EXTI_Line5) != RESET)
  452. {
  453. pin_irq_hdr(5);
  454. }
  455. if (EXTI_GetITStatus(EXTI_Line6) != RESET)
  456. {
  457. pin_irq_hdr(6);
  458. }
  459. if (EXTI_GetITStatus(EXTI_Line7) != RESET)
  460. {
  461. pin_irq_hdr(7);
  462. }
  463. if (EXTI_GetITStatus(EXTI_Line8) != RESET)
  464. {
  465. pin_irq_hdr(8);
  466. }
  467. if (EXTI_GetITStatus(EXTI_Line9) != RESET)
  468. {
  469. pin_irq_hdr(9);
  470. }
  471. /* leave interrupt */
  472. rt_interrupt_leave();
  473. }
  474. void EXTI15_10_IRQHandler(void)
  475. {
  476. /* enter interrupt */
  477. rt_interrupt_enter();
  478. if (EXTI_GetITStatus(EXTI_Line10) != RESET)
  479. {
  480. pin_irq_hdr(10);
  481. }
  482. if (EXTI_GetITStatus(EXTI_Line11) != RESET)
  483. {
  484. pin_irq_hdr(11);
  485. }
  486. if (EXTI_GetITStatus(EXTI_Line12) != RESET)
  487. {
  488. pin_irq_hdr(12);
  489. }
  490. if (EXTI_GetITStatus(EXTI_Line13) != RESET)
  491. {
  492. pin_irq_hdr(13);
  493. }
  494. if (EXTI_GetITStatus(EXTI_Line14) != RESET)
  495. {
  496. pin_irq_hdr(14);
  497. }
  498. if (EXTI_GetITStatus(EXTI_Line15) != RESET)
  499. {
  500. pin_irq_hdr(15);
  501. }
  502. /* leave interrupt */
  503. rt_interrupt_leave();
  504. }