arc_startup.S 5.9 KB

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  1. /* ------------------------------------------
  2. * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
  3. * Redistribution and use in source and binary forms, with or without modification,
  4. * are permitted provided that the following conditions are met:
  5. * 1) Redistributions of source code must retain the above copyright notice, this
  6. * list of conditions and the following disclaimer.
  7. * 2) Redistributions in binary form must reproduce the above copyright notice,
  8. * this list of conditions and the following disclaimer in the documentation and/or
  9. * other materials provided with the distribution.
  10. * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
  11. * be used to endorse or promote products derived from this software without
  12. * specific prior written permission.
  13. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  14. * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  15. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  16. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  17. * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  18. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  19. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  20. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  21. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  22. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  23. *
  24. * \version 2016.05
  25. * \date 2014-07-15
  26. * \author Wayne Ren(Wei.Ren@synopsys.com)
  27. --------------------------------------------- */
  28. /**
  29. * \file
  30. * \ingroup ARC_HAL_STARTUP
  31. * \brief assembly part of startup process
  32. */
  33. /**
  34. * \addtogroup ARC_HAL_STARTUP
  35. * @{
  36. */
  37. /** @cond STARTUP_ASM */
  38. #define __ASSEMBLY__
  39. #include "embARC_BSP_config.h"
  40. #include "inc/arc/arc.h"
  41. .file "arc_startup.S"
  42. .weak _f_sdata /* start of small data, defined in link script */
  43. .weak init_hardware_hook /* app hardware init hook */
  44. .weak init_software_hook /* app software init hook */
  45. .extern board_main
  46. .extern exc_entry_table
  47. /* initial vector table */
  48. .section .init_vector, "a"
  49. .long _arc_reset
  50. .section .init_bootstrap, "ax"
  51. .global _arc_reset
  52. .global _start
  53. .align 4
  54. _start:
  55. _arc_reset:
  56. _arc_reset_stage1:
  57. kflag STATUS32_RESET_VALUE
  58. /* STAGE 1 */
  59. /* necessary hardware should be done first to speed up initialization
  60. 1. system clk
  61. 2. mem controller must be initialized before any access to external
  62. mem.
  63. 3. others
  64. */
  65. _arc_cache_init_start:
  66. lr r0, [AUX_BCR_D_CACHE]
  67. cmp r0, 2
  68. /* invalidate dcache */
  69. jle _arc_icache_init
  70. mov r0, 1
  71. sr r0, [AUX_DC_IVDC]
  72. sr r0, [AUX_DC_CTRL]
  73. _arc_icache_init:
  74. lr r0, [AUX_BCR_I_CACHE]
  75. cmp r0, 2
  76. jle _arc_cache_init_end
  77. /* invalidate icache */
  78. mov r0, 1
  79. sr r0, [AUX_IC_IVIC]
  80. nop_s
  81. nop_s
  82. nop_s
  83. sr r0, [AUX_IC_CTRL]
  84. _arc_cache_init_end:
  85. mov r0, init_hardware_hook
  86. cmp r0, 0
  87. jlne [r0]
  88. /* STAGE 2: init necessary registers */
  89. _arc_reset_stage2:
  90. mov r0, 0
  91. /* interrupt related init */
  92. sr r0, [AUX_IRQ_ACT]
  93. sr r0, [AUX_IRQ_CTRL]
  94. sr r0, [AUX_IRQ_HINT]
  95. /* use the new vector table to replace the old one */
  96. #if defined(ARC_FEATURE_SEC_PRESENT) && (SECURESHIELD_VERSION < 2)
  97. sr exc_entry_table, [AUX_INT_VECT_BASE_S]
  98. #else
  99. sr exc_entry_table, [AUX_INT_VECT_BASE]
  100. #endif
  101. /* init stack */
  102. #if ARC_FEATURE_RGF_BANKED_REGS >= 16 && ARC_FEATURE_RGF_BANKED_REGS > 1 && ARC_FEATURE_FIRQ == 1
  103. #if _STACKSIZE < 512
  104. #error "not enough stack size for irq and firq"
  105. #endif
  106. /* switch to register bank1 */
  107. lr r0, [AUX_STATUS32]
  108. bic r0, r0, 0x70000
  109. or r0, r0, 0x10000
  110. kflag r0
  111. /* set sp, gp, fp in bank1 */
  112. mov sp, _e_stack
  113. mov gp, _f_sdata
  114. mov fp, 0
  115. /* come back to bank0 */
  116. lr r0, [AUX_STATUS32]
  117. bic r0, r0, 0x70000
  118. kflag r0
  119. mov sp, _e_stack-256
  120. #else
  121. mov sp, _e_stack /* init stack pointer */
  122. #endif
  123. mov gp, _f_sdata /* init small-data base register */
  124. mov fp, 0 /* init fp register */
  125. _arc_reset_stage3:
  126. _s3_copy_text:
  127. mov r0, _f_text
  128. mov r1, _load_addr_text
  129. cmp r0, r1
  130. /* if load addr == run addr, no need to copy */
  131. jeq _s3_copy_rodata
  132. mov r3, _e_text
  133. _s3_copy_text_loop:
  134. ld.ab r2, [r1, 4]
  135. st.ab r2, [r0, 4]
  136. cmp r0, r3
  137. jlt _s3_copy_text_loop
  138. _s3_copy_rodata:
  139. mov r0, _f_rodata
  140. mov r1, _load_addr_rodata
  141. cmp r0, r1
  142. /* if load addr == run addr, no need to copy */
  143. jeq _s3_copy_data
  144. mov r3, _e_rodata
  145. _s3_copy_rodata_loop:
  146. ld.ab r2, [r1, 4]
  147. st.ab r2, [r0, 4]
  148. cmp r0, r3
  149. jlt _s3_copy_rodata_loop
  150. _s3_copy_data:
  151. mov r0, _f_data
  152. mov r1, _load_addr_data
  153. cmp r0, r1
  154. jeq _s3_clear_bss
  155. /* if load addr == run addr, no need to copy */
  156. mov r3, _e_data
  157. _s3_copy_data_loop:
  158. ld.ab r2, [r1, 4]
  159. st.ab r2, [r0, 4]
  160. cmp r0, r3
  161. jlt _s3_copy_data_loop
  162. _s3_clear_bss:
  163. mov r0, _f_bss
  164. mov r1, _e_bss
  165. cmp r0, r1
  166. jge _arc_reset_call_main
  167. mov r2, 0
  168. _s3_clear_bss_loop:
  169. st.ab r2, [r0, 4]
  170. cmp r0, r1
  171. jlt _s3_clear_bss_loop
  172. /* STAGE 3: go to main */
  173. _arc_reset_call_main:
  174. /* \todo add cpp init here */
  175. mov r0, init_software_hook
  176. cmp r0, 0
  177. jlne [r0]
  178. /* board level library init */
  179. /* early init of interrupt and exception */
  180. jl exc_int_init
  181. /* init cache */
  182. jl arc_cache_init
  183. #if defined(__MW__)
  184. jl _init
  185. #elif defined(__GNU__)
  186. jl __do_global_ctors_aux
  187. jl __do_init_array_aux
  188. #endif
  189. jl board_main /* board-level main */
  190. #if defined(__MW__)
  191. jl _fini
  192. #elif defined(__GNU__)
  193. jl __do_global_dtors_aux
  194. #endif
  195. .global _exit_loop
  196. .global _exit_halt
  197. .align 4
  198. _exit_halt:
  199. _exit_loop:
  200. flag 0x1
  201. nop
  202. nop
  203. nop
  204. b _exit_loop
  205. #if defined(__MW__)
  206. .global _init, _fini
  207. .section ".init",text
  208. _init:
  209. .cfa_bf _init
  210. push %blink
  211. .cfa_push {%blink}
  212. .section ".init$999999", text, 1, 2, check_text_align=0
  213. pop %blink
  214. .cfa_pop {%blink}
  215. j [%blink]
  216. .cfa_ef
  217. .section ".fini", text
  218. _fini:
  219. .cfa_bf _fini
  220. push %blink
  221. .cfa_push {%blink}
  222. .section ".fini$999999", text, 1, 2, check_text_align=0
  223. pop %blink
  224. .cfa_pop {%blink}
  225. j [%blink]
  226. .cfa_ef
  227. #endif
  228. /** @endcond */
  229. /** }@*/