emsk_hardware.h 4.8 KB

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  1. /*
  2. * Copyright (c) 2018, Synopsys, Inc.
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. #ifndef _EMSK_HARDWARE_H_
  7. #define _EMSK_HARDWARE_H_
  8. #include "inc/arc/arc_feature_config.h"
  9. /** CPU Clock Frequency definition */
  10. #if defined(BOARD_CPU_FREQ)
  11. /*!< Get cpu clock frequency definition from build system */
  12. #define CLK_CPU (BOARD_CPU_FREQ)
  13. #elif defined(ARC_FEATURE_CPU_CLOCK_FREQ)
  14. /*!< Get cpu clock frequency definition from tcf file */
  15. #define CLK_CPU (ARC_FEATURE_CPU_CLOCK_FREQ)
  16. #else
  17. /*!< Default cpu clock frequency */
  18. #define CLK_CPU (20000000)
  19. #endif
  20. /** Peripheral Bus Reference Clock definition */
  21. #ifdef BOARD_DEV_FREQ
  22. /*!< Get peripheral bus reference clock defintion from build system */
  23. #define CLK_BUS_APB (BOARD_DEV_FREQ)
  24. #else
  25. /*!< Default peripheral bus reference clock defintion */
  26. #define CLK_BUS_APB (50000000U)
  27. #endif
  28. #ifdef ARC_FEATURE_DMP_PERIPHERAL
  29. #define PERIPHERAL_BASE ARC_FEATURE_DMP_PERIPHERAL
  30. #else
  31. #define PERIPHERAL_BASE _arc_aux_read(AUX_DMP_PERIPHERAL)
  32. #endif
  33. /* Device Register Base Address */
  34. #define REL_REGBASE_PINMUX (0x00000000U) /*!< PINMUX */
  35. #define REL_REGBASE_SPI_MST_CS_CTRL (0x00000014U) /*!< SPI Master Select Ctrl */
  36. #define REL_REGBASE_GPIO0 (0x00002000U) /*!< GPIO 0 Onboard */
  37. #define REL_REGBASE_TIMERS (0x00003000U) /*!< DW TIMER */
  38. #define REL_REGBASE_I2C0 (0x00004000U) /*!< I2C 0 */
  39. #define REL_REGBASE_I2C1 (0x00005000U) /*!< I2C 1 */
  40. #define REL_REGBASE_SPI0 (0x00006000U) /*!< SPI Master */
  41. #define REL_REGBASE_SPI1 (0x00007000U) /*!< SPI Slave */
  42. #define REL_REGBASE_UART0 (0x00008000U) /*!< UART0 is connected to PMOD */
  43. #define REL_REGBASE_UART1 (0x00009000U) /*!< UART1 is USB-UART£¬ use UART1 as default */
  44. #define REL_REGBASE_UART2 (0x0000A000U) /*!< UART2 */
  45. #define REL_REGBASE_WDT (0x0000B000U) /*!< WDT */
  46. // #define REL_REGBASE_I2S_MASTER_IN (0x0000C000U) /*!< I2S Master In */
  47. // #define REL_REGBASE_I2S_MASTER_OUT (0x0000D000U) /*!< I2S Master Out */
  48. // #define REL_REGBASE_GMAC (0x0000E000U) /*!< GMAC */
  49. /* Interrupt Connection */
  50. #define INTNO_TIMER0 16 /*!< ARC Timer0 */
  51. #define INTNO_TIMER1 17 /*!< ARC Timer1 */
  52. #define INTNO_SECURE_TIMER0 20 /*!< Core Secure Timer 0 */
  53. #define INTNO_DMA_START 22 /*!< Core DMA Controller */
  54. #define INTNO_DMA_COMPLETE 22 /*!< Core DMA Controller Complete */
  55. #define INTNO_DMA_ERROR 23 /*!< Core DMA Controller Error */
  56. #define INTNO_GPIO 24 /*!< GPIO controller */
  57. #define INTNO_I2C0 25 /*!< I2C_0 controller */
  58. #define INTNO_I2C1 26 /*!< I2C_1 controller */
  59. #define INTNO_SPI_MASTER 27 /*!< SPI Master controller */
  60. #define INTNO_SPI_SLAVE 28 /*!< SPI Slave controller */
  61. #define INTNO_UART0 29 /*!< UART0 */
  62. #define INTNO_UART1 30 /*!< UART1 */
  63. #define INTNO_UART2 31 /*!< UART2 */
  64. #define INTNO_DW_WDT 32 /*!< WDT */
  65. #define INTNO_DW_TMR0 33 /*!< DW Timer 0 */
  66. #define INTNO_DW_TMR1 34 /*!< DW Timer 1 */
  67. // #define INTNO_I2S_Master_In 33 /*!< I2S Master In */
  68. // #define INTNO_I2S_Master_Out 34 /*!< I2S Master Out */
  69. // #define INTNO_GMAC 35 /*!< GMAC */
  70. /* SPI Mater Signals Usage */
  71. #define EMSK_SPI_LINE_0 0 /*!< CS0 -- Pmod 6 pin1 */
  72. #define EMSK_SPI_LINE_1 1 /*!< CS1 -- Pmod 5 pin1 or Pmod 6 pin 7 */
  73. #define EMSK_SPI_LINE_2 2 /*!< CS2 -- Pmod 6 pin8 */
  74. #define EMSK_SPI_LINE_SDCARD 3 /*!< CS3 -- On-board SD card */
  75. #define EMSK_SPI_LINE_SPISLAVE 4 /*!< CS4 -- Internal SPI slave */
  76. #define EMSK_SPI_LINE_SFLASH 5 /*!< CS5 -- On-board SPI Flash memory */
  77. #endif /* _EMSK_HARDWARE_H_ */