mux.h 4.8 KB

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  1. /*
  2. * Copyright (c) 2018, Synopsys, Inc.
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. #ifndef _MUX_H_
  7. #define _MUX_H_
  8. #include "inc/embARC_toolchain.h"
  9. #define BIT0 (0)
  10. #define BIT1 (1)
  11. #define BIT2 (2)
  12. #define BIT3 (3)
  13. #define PM1_OFFSET (0)
  14. #define PM2_OFFSET (4)
  15. #define PM3_OFFSET (8)
  16. #define PM4_OFFSET (12)
  17. #define PM5_OFFSET (16)
  18. #define PM6_OFFSET (20)
  19. #define PM7_OFFSET (24)
  20. #define PM1_MASK (0xf << PM1_OFFSET)
  21. #define PM2_MASK (0xf << PM2_OFFSET)
  22. #define PM3_MASK (0xf << PM3_OFFSET)
  23. #define PM4_MASK (0xf << PM4_OFFSET)
  24. #define PM5_MASK (0xf << PM5_OFFSET)
  25. #define PM6_MASK (0xf << PM6_OFFSET)
  26. #define PM7_MASK (0xf << PM7_OFFSET)
  27. #define SPI_MAP_NORMAL (0)
  28. #define SPI_MAP_LOOPBACK (1)
  29. #define UART_MAP_TYPE4 (0xE4)
  30. #define UART_MAP_TYPE3 (0x6C)
  31. /**
  32. * \name Default pin muxer settings
  33. * @{
  34. */
  35. #define PMOD_MUX_CTRL_DEFAULT (0) /*!< all pins are configured as GPIO inputs */
  36. #define SPI_MAP_CTRL_DEFAULT (SPI_MAP_NORMAL) /*!< normal SPI mode */
  37. #define UART_MAP_CTRL_DEFAULT (UART_MAP_TYPE4) /*!< TYPE4 PMOD compatible */
  38. /** @} end of name */
  39. /**
  40. * \name PMOD 1 Multiplexor
  41. * @{
  42. */
  43. #define PM1_UR_GPIO_C ((0 << BIT0) << PM1_OFFSET) /*!< Pmod1[4:1] are connected to DW GPIO Port C[11:8] */
  44. #define PM1_UR_UART_0 ((1 << BIT0) << PM1_OFFSET) /*!< Pmod1[4:1] are connected to DW UART0 signals */
  45. #define PM1_LR_GPIO_A ((0 << BIT2) << PM1_OFFSET) /*!< Pmod1[10:7] are connected to DW GPIO Port A[11:8] */
  46. #define PM1_LR_SPI_S ((1 << BIT2) << PM1_OFFSET) /*!< Pmod1[10:7] are connected to DW SPI Slave signals */
  47. /** @} end of name */
  48. /**
  49. * \name PMOD 2 Multiplexor
  50. * @{
  51. */
  52. #define PM2_GPIO_AC ((0 << BIT0) << PM2_OFFSET) /*!< Pmod2[4:1] are connected to DW GPIO Port C[15:12],
  53. Pmod2[10:7] are connected to DW GPIO Port A[15:12] */
  54. #define PM2_I2C_HRI ((1 << BIT0) << PM2_OFFSET) /*!< connect I2C to Pmod2[4:1] and halt/run interface to Pmod2[10:7] */
  55. /** @} end of name */
  56. /**
  57. * \name PMOD 3 Multiplexor
  58. * @{
  59. */
  60. #define PM3_GPIO_AC ((0 << BIT0) << PM3_OFFSET) /*!< Pmod3[4:1] are connected to DW GPIO Port C[19:16],
  61. Pmod3[10:7] are connected to DW GPIO Port A[19:16] */
  62. #define PM3_I2C_GPIO_D ((1 << BIT0) << PM3_OFFSET) /*!< Pmod3[4:3] are connected to DW I2C signals,
  63. Pmod3[2:1] are connected to DW GPIO Port D[1:0],
  64. Pmod3[10:7] are connected to DW GPIO Port D[3:2] */
  65. /** @} end of name */
  66. /**
  67. * \name PMOD 4 Multiplexor
  68. * @{
  69. */
  70. #define PM4_GPIO_AC ((0 << BIT0) << PM4_OFFSET) /*!< Pmod4[4:1] are connected to DW GPIO Port C[23:20],
  71. Pmod4[10:7] are connected to DW GPIO Port A[23:20] */
  72. #define PM4_I2C_GPIO_D ((1 << BIT0) << PM4_OFFSET) /*!< Pmod4[4:3] are connected to DW I2C signals,
  73. Pmod4[2:1] are connected to DW GPIO Port D[5:4],
  74. Pmod4[10:7] are connected to DW GPIO Port D[7:6] */
  75. /** @} end of name */
  76. /**
  77. * \name PMOD 5 Multiplexor
  78. * @{
  79. */
  80. #define PM5_UR_GPIO_C ((0 << BIT0) << PM5_OFFSET) /*!< Pmod5[4:1] are connected to DW GPIO Port C[27:24] */
  81. #define PM5_UR_SPI_M1 ((1 << BIT0) << PM5_OFFSET) /*!< Pmod5[4:1] are connected to DW SPI Master signals using CS1_N */
  82. #define PM5_LR_GPIO_A ((0 << BIT2) << PM5_OFFSET) /*!< Pmod5[10:7] are connected to DW GPIO Port A[27:24] */
  83. #define PM5_LR_SPI_M2 ((1 << BIT2) << PM5_OFFSET) /*!< Pmod5[10:7] are connected to DW SPI Master signals using CS2_N */
  84. /** @} end of name */
  85. /**
  86. * \name PMOD 6 Multiplexor
  87. * @{
  88. */
  89. #define PM6_UR_GPIO_C ((0 << BIT0) << PM6_OFFSET) /*!< Pmod6[4:1] are connected to DW GPIO Port C[31:28] */
  90. #define PM6_UR_SPI_M0 ((1 << BIT0) << PM6_OFFSET) /*!< Pmod6[4:1] are connected to DW SPI Master signals using CS0_N */
  91. #define PM6_LR_GPIO_A ((0 << BIT2) << PM6_OFFSET) /*!< Pmod6[10:7] are connected to DW GPIO Port A[31:28] */
  92. #define PM6_LR_CSS_STAT ((1 << BIT2) << PM6_OFFSET) /*!< Pmod6[8:7] are connected to the DW SPI Master chip select signals CS1_N and CS2_N,
  93. Pmod6[6:5] are connected to the ARC EM halt and sleep status signals */
  94. /** @} end of name */
  95. /**
  96. * \name PMOD 7 Multiplexor
  97. * @{
  98. */
  99. #define PM7_GPIO_D ((0 << BIT0) << PM7_OFFSET) /*!< Pmod7[4:1] are connected to DW GPIO Port D[11:8] */
  100. #define PM7_STAT ((1 << BIT0) << PM7_OFFSET) /*!< Pmod7[4:1] are connected to the ARC EM sleep status signals */
  101. /** @} end of name */
  102. typedef volatile uint32_t MUX_REG;
  103. #ifdef __cplusplus
  104. extern "C" {
  105. #endif
  106. extern void mux_init(MUX_REG *mux_regs);
  107. extern MUX_REG *get_mux_regs(void);
  108. extern void set_pmod_mux(MUX_REG *mux_regs, uint32_t val);
  109. extern uint32_t get_pmod_mux(MUX_REG *mux_regs);
  110. extern void change_pmod_mux(MUX_REG *mux_regs, uint32_t val, uint32_t change_bits);
  111. extern void set_spi_map(MUX_REG *mux_regs, uint32_t val);
  112. extern uint32_t get_spi_map(MUX_REG *mux_regs);
  113. extern void set_uart_map(MUX_REG *mux_regs, uint32_t val);
  114. extern uint32_t get_uart_map(MUX_REG *mux_regs);
  115. #ifdef __cplusplus
  116. }
  117. #endif
  118. #endif /* _MUX_H_ */