drv_wdt.c 3.7 KB

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  1. /*
  2. * Copyright (c) 2006-2022, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2022-03-04 stevetong459 first version
  9. * 2022-12-26 luobeihai add apm32F0 serie MCU support
  10. */
  11. #include <board.h>
  12. #include <sys/time.h>
  13. #ifdef RT_USING_WDT
  14. #define DBG_TAG "drv.wdt"
  15. #define DBG_LVL DBG_INFO
  16. #include <rtdbg.h>
  17. #ifndef LSI_VALUE
  18. #define LSI_VALUE ((uint32_t)40000)
  19. #endif
  20. #define DRV_WDT_TIME_OUT 0xFFFF
  21. typedef struct
  22. {
  23. struct rt_watchdog_device wdt;
  24. rt_uint32_t min_threshold;
  25. rt_uint32_t max_threshold;
  26. rt_uint32_t current_threshold;
  27. } apm32_wdt_t;
  28. static apm32_wdt_t wdt_config;
  29. static rt_err_t apm32_iwdt_init(rt_watchdog_t *wdt)
  30. {
  31. rt_uint32_t counter = 0;
  32. RCM_EnableLSI();
  33. while (!RCM_ReadStatusFlag(RCM_FLAG_LSIRDY))
  34. {
  35. if (++counter > DRV_WDT_TIME_OUT)
  36. {
  37. LOG_E("LSI clock open failed.");
  38. return -RT_ERROR;
  39. }
  40. }
  41. wdt_config.min_threshold = 1;
  42. wdt_config.max_threshold = (0xfff << 8) / LSI_VALUE;
  43. LOG_I("threshold section [%u, %d]", \
  44. wdt_config.min_threshold,
  45. wdt_config.max_threshold);
  46. #if defined(SOC_SERIES_APM32F0)
  47. while (IWDT_ReadStatusFlag(IWDT_FLAG_DIVU))
  48. #else
  49. while (IWDT_ReadStatusFlag(IWDT_FLAG_PSCU))
  50. #endif
  51. {
  52. if (++counter > DRV_WDT_TIME_OUT)
  53. {
  54. LOG_E("watchdog prescaler init failed.");
  55. return -RT_ERROR;
  56. }
  57. }
  58. IWDT_EnableWriteAccess();
  59. #if defined(SOC_SERIES_APM32F0)
  60. IWDT_ConfigDivider(IWDT_DIV_256);
  61. #else
  62. IWDT_ConfigDivider(IWDT_DIVIDER_256);
  63. #endif
  64. IWDT_DisableWriteAccess();
  65. return RT_EOK;
  66. }
  67. /**
  68. * @brief This function will control watchdog device.
  69. *
  70. * @param wdt is a pointer to i2c config class.
  71. *
  72. * @return RT_EOK indicates successful , other value indicates failed.
  73. */
  74. static rt_err_t apm32_iwdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
  75. {
  76. volatile rt_uint32_t param, counter = 0;
  77. switch (cmd)
  78. {
  79. case RT_DEVICE_CTRL_WDT_KEEPALIVE:
  80. IWDT_Refresh();
  81. break;
  82. case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
  83. param = *(rt_uint32_t *) arg;
  84. if ((param > wdt_config.max_threshold) || \
  85. (param < wdt_config.min_threshold))
  86. {
  87. LOG_E("invalid param@%u.", param);
  88. return -RT_ERROR;
  89. }
  90. else
  91. {
  92. wdt_config.current_threshold = param;
  93. }
  94. while (IWDT_ReadStatusFlag(IWDT_FLAG_CNTU))
  95. {
  96. if (++counter > DRV_WDT_TIME_OUT)
  97. {
  98. LOG_E("Update watchdog reload value complete.");
  99. return -RT_ERROR;
  100. }
  101. }
  102. IWDT_Refresh();
  103. IWDT_EnableWriteAccess();
  104. IWDT_ConfigReload(param * LSI_VALUE >> 8);
  105. IWDT_DisableWriteAccess();
  106. break;
  107. case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
  108. *(rt_uint32_t *)arg = wdt_config.current_threshold;
  109. break;
  110. case RT_DEVICE_CTRL_WDT_START:
  111. IWDT_Enable();
  112. IWDT_Refresh();
  113. break;
  114. default:
  115. LOG_W("This command is not supported.");
  116. return -RT_ERROR;
  117. }
  118. return RT_EOK;
  119. }
  120. static struct rt_watchdog_ops apm32_wdt_ops =
  121. {
  122. apm32_iwdt_init,
  123. apm32_iwdt_control,
  124. };
  125. static int rt_hw_wdt_init(void)
  126. {
  127. wdt_config.wdt.ops = &apm32_wdt_ops;
  128. /* register watchdog device */
  129. if (rt_hw_watchdog_register(&wdt_config.wdt, "wdt", \
  130. RT_DEVICE_FLAG_DEACTIVATE, RT_NULL) != RT_EOK)
  131. {
  132. LOG_E("wdt device register failed.");
  133. return -RT_ERROR;
  134. }
  135. LOG_D("wdt device register success.");
  136. return RT_EOK;
  137. }
  138. INIT_BOARD_EXPORT(rt_hw_wdt_init);
  139. #endif