drv_spi.c 31 KB

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  1. /*
  2. * Copyright (c) 2006-2023, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-11-5 SummerGift first version
  9. * 2018-12-11 greedyhao Porting for stm32f7xx
  10. * 2019-01-03 zylx modify DMA initialization and spixfer function
  11. * 2020-01-15 whj4674672 Porting for stm32h7xx
  12. * 2020-06-18 thread-liu Porting for stm32mp1xx
  13. * 2020-10-14 Dozingfiretruck Porting for stm32wbxx
  14. */
  15. #include <rtthread.h>
  16. #include <rtdevice.h>
  17. #include "board.h"
  18. #ifdef BSP_USING_SPI
  19. #if defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3) || defined(BSP_USING_SPI4) || defined(BSP_USING_SPI5) || defined(BSP_USING_SPI6)
  20. #include "drv_spi.h"
  21. #include "drv_config.h"
  22. #include <string.h>
  23. //#define DRV_DEBUG
  24. #define LOG_TAG "drv.spi"
  25. #include <drv_log.h>
  26. enum
  27. {
  28. #ifdef BSP_USING_SPI1
  29. SPI1_INDEX,
  30. #endif
  31. #ifdef BSP_USING_SPI2
  32. SPI2_INDEX,
  33. #endif
  34. #ifdef BSP_USING_SPI3
  35. SPI3_INDEX,
  36. #endif
  37. #ifdef BSP_USING_SPI4
  38. SPI4_INDEX,
  39. #endif
  40. #ifdef BSP_USING_SPI5
  41. SPI5_INDEX,
  42. #endif
  43. #ifdef BSP_USING_SPI6
  44. SPI6_INDEX,
  45. #endif
  46. };
  47. static struct stm32_spi_config spi_config[] =
  48. {
  49. #ifdef BSP_USING_SPI1
  50. SPI1_BUS_CONFIG,
  51. #endif
  52. #ifdef BSP_USING_SPI2
  53. SPI2_BUS_CONFIG,
  54. #endif
  55. #ifdef BSP_USING_SPI3
  56. SPI3_BUS_CONFIG,
  57. #endif
  58. #ifdef BSP_USING_SPI4
  59. SPI4_BUS_CONFIG,
  60. #endif
  61. #ifdef BSP_USING_SPI5
  62. SPI5_BUS_CONFIG,
  63. #endif
  64. #ifdef BSP_USING_SPI6
  65. SPI6_BUS_CONFIG,
  66. #endif
  67. };
  68. static struct stm32_spi spi_bus_obj[sizeof(spi_config) / sizeof(spi_config[0])] = {0};
  69. static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configuration *cfg)
  70. {
  71. RT_ASSERT(spi_drv != RT_NULL);
  72. RT_ASSERT(cfg != RT_NULL);
  73. SPI_HandleTypeDef *spi_handle = &spi_drv->handle;
  74. if (cfg->mode & RT_SPI_SLAVE)
  75. {
  76. spi_handle->Init.Mode = SPI_MODE_SLAVE;
  77. }
  78. else
  79. {
  80. spi_handle->Init.Mode = SPI_MODE_MASTER;
  81. }
  82. if (cfg->mode & RT_SPI_3WIRE)
  83. {
  84. spi_handle->Init.Direction = SPI_DIRECTION_1LINE;
  85. }
  86. else
  87. {
  88. spi_handle->Init.Direction = SPI_DIRECTION_2LINES;
  89. }
  90. if (cfg->data_width == 8)
  91. {
  92. spi_handle->Init.DataSize = SPI_DATASIZE_8BIT;
  93. spi_handle->TxXferSize = 8;
  94. spi_handle->RxXferSize = 8;
  95. }
  96. else if (cfg->data_width == 16)
  97. {
  98. spi_handle->Init.DataSize = SPI_DATASIZE_16BIT;
  99. }
  100. else
  101. {
  102. return RT_EIO;
  103. }
  104. if (cfg->mode & RT_SPI_CPHA)
  105. {
  106. spi_handle->Init.CLKPhase = SPI_PHASE_2EDGE;
  107. }
  108. else
  109. {
  110. spi_handle->Init.CLKPhase = SPI_PHASE_1EDGE;
  111. }
  112. if (cfg->mode & RT_SPI_CPOL)
  113. {
  114. spi_handle->Init.CLKPolarity = SPI_POLARITY_HIGH;
  115. }
  116. else
  117. {
  118. spi_handle->Init.CLKPolarity = SPI_POLARITY_LOW;
  119. }
  120. spi_handle->Init.NSS = SPI_NSS_SOFT;
  121. uint32_t SPI_CLOCK;
  122. /* Some series may only have APBPERIPH_BASE, but don't have HAL_RCC_GetPCLK2Freq */
  123. #if defined(APBPERIPH_BASE)
  124. SPI_CLOCK = HAL_RCC_GetPCLK1Freq();
  125. #elif defined(APB1PERIPH_BASE) || defined(APB2PERIPH_BASE)
  126. /* The SPI clock for H7 cannot be configured with a peripheral bus clock, so it needs to be written separately */
  127. #if defined(SOC_SERIES_STM32H7)
  128. /* When the configuration is generated using CUBEMX, the configuration for the SPI clock is placed in the HAL_SPI_Init function.
  129. Therefore, it is necessary to initialize and configure the SPI clock to automatically configure the frequency division */
  130. HAL_SPI_Init(spi_handle);
  131. SPI_CLOCK = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI123);
  132. #else
  133. if ((rt_uint32_t)spi_drv->config->Instance >= APB2PERIPH_BASE)
  134. {
  135. SPI_CLOCK = HAL_RCC_GetPCLK2Freq();
  136. }
  137. else
  138. {
  139. SPI_CLOCK = HAL_RCC_GetPCLK1Freq();
  140. }
  141. #endif /* SOC_SERIES_STM32H7) */
  142. #endif /* APBPERIPH_BASE */
  143. if (cfg->max_hz >= SPI_CLOCK / 2)
  144. {
  145. spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
  146. }
  147. else if (cfg->max_hz >= SPI_CLOCK / 4)
  148. {
  149. spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4;
  150. }
  151. else if (cfg->max_hz >= SPI_CLOCK / 8)
  152. {
  153. spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8;
  154. }
  155. else if (cfg->max_hz >= SPI_CLOCK / 16)
  156. {
  157. spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16;
  158. }
  159. else if (cfg->max_hz >= SPI_CLOCK / 32)
  160. {
  161. spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32;
  162. }
  163. else if (cfg->max_hz >= SPI_CLOCK / 64)
  164. {
  165. spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_64;
  166. }
  167. else if (cfg->max_hz >= SPI_CLOCK / 128)
  168. {
  169. spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_128;
  170. }
  171. else
  172. {
  173. /* min prescaler 256 */
  174. spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256;
  175. }
  176. LOG_D("sys freq: %d, pclk freq: %d, SPI limiting freq: %d, SPI usage freq: %d",
  177. #if defined(SOC_SERIES_STM32MP1)
  178. HAL_RCC_GetSystemCoreClockFreq(),
  179. #else
  180. HAL_RCC_GetSysClockFreq(),
  181. #endif
  182. SPI_CLOCK,
  183. cfg->max_hz,
  184. SPI_CLOCK / (rt_size_t)pow(2,(spi_handle->Init.BaudRatePrescaler >> 28) + 1));
  185. if (cfg->mode & RT_SPI_MSB)
  186. {
  187. spi_handle->Init.FirstBit = SPI_FIRSTBIT_MSB;
  188. }
  189. else
  190. {
  191. spi_handle->Init.FirstBit = SPI_FIRSTBIT_LSB;
  192. }
  193. spi_handle->Init.TIMode = SPI_TIMODE_DISABLE;
  194. spi_handle->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
  195. spi_handle->State = HAL_SPI_STATE_RESET;
  196. #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32WB)
  197. spi_handle->Init.NSSPMode = SPI_NSS_PULSE_DISABLE;
  198. #elif defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
  199. spi_handle->Init.Mode = SPI_MODE_MASTER;
  200. spi_handle->Init.NSS = SPI_NSS_SOFT;
  201. spi_handle->Init.NSSPMode = SPI_NSS_PULSE_DISABLE;
  202. spi_handle->Init.NSSPolarity = SPI_NSS_POLARITY_LOW;
  203. spi_handle->Init.CRCPolynomial = 7;
  204. spi_handle->Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
  205. spi_handle->Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
  206. spi_handle->Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE;
  207. spi_handle->Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE;
  208. spi_handle->Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE;
  209. spi_handle->Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_ENABLE;
  210. spi_handle->Init.IOSwap = SPI_IO_SWAP_DISABLE;
  211. spi_handle->Init.FifoThreshold = SPI_FIFO_THRESHOLD_08DATA;
  212. #endif
  213. if (HAL_SPI_Init(spi_handle) != HAL_OK)
  214. {
  215. return RT_EIO;
  216. }
  217. #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) \
  218. || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32WB)
  219. SET_BIT(spi_handle->Instance->CR2, SPI_RXFIFO_THRESHOLD_HF);
  220. #endif
  221. /* DMA configuration */
  222. if (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG)
  223. {
  224. HAL_DMA_Init(&spi_drv->dma.handle_rx);
  225. __HAL_LINKDMA(&spi_drv->handle, hdmarx, spi_drv->dma.handle_rx);
  226. /* NVIC configuration for DMA transfer complete interrupt */
  227. HAL_NVIC_SetPriority(spi_drv->config->dma_rx->dma_irq, 0, 0);
  228. HAL_NVIC_EnableIRQ(spi_drv->config->dma_rx->dma_irq);
  229. }
  230. if (spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG)
  231. {
  232. HAL_DMA_Init(&spi_drv->dma.handle_tx);
  233. __HAL_LINKDMA(&spi_drv->handle, hdmatx, spi_drv->dma.handle_tx);
  234. /* NVIC configuration for DMA transfer complete interrupt */
  235. HAL_NVIC_SetPriority(spi_drv->config->dma_tx->dma_irq, 1, 0);
  236. HAL_NVIC_EnableIRQ(spi_drv->config->dma_tx->dma_irq);
  237. }
  238. if(spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG || spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG)
  239. {
  240. HAL_NVIC_SetPriority(spi_drv->config->irq_type, 2, 0);
  241. HAL_NVIC_EnableIRQ(spi_drv->config->irq_type);
  242. }
  243. LOG_D("%s init done", spi_drv->config->bus_name);
  244. return RT_EOK;
  245. }
  246. static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
  247. {
  248. HAL_StatusTypeDef state;
  249. rt_size_t message_length, already_send_length;
  250. rt_uint16_t send_length;
  251. rt_uint8_t *recv_buf;
  252. const rt_uint8_t *send_buf;
  253. RT_ASSERT(device != RT_NULL);
  254. RT_ASSERT(device->bus != RT_NULL);
  255. RT_ASSERT(message != RT_NULL);
  256. struct stm32_spi *spi_drv = rt_container_of(device->bus, struct stm32_spi, spi_bus);
  257. SPI_HandleTypeDef *spi_handle = &spi_drv->handle;
  258. if (message->cs_take && !(device->config.mode & RT_SPI_NO_CS) && (device->cs_pin != PIN_NONE))
  259. {
  260. if (device->config.mode & RT_SPI_CS_HIGH)
  261. rt_pin_write(device->cs_pin, PIN_HIGH);
  262. else
  263. rt_pin_write(device->cs_pin, PIN_LOW);
  264. }
  265. LOG_D("%s transfer prepare and start", spi_drv->config->bus_name);
  266. LOG_D("%s sendbuf: %X, recvbuf: %X, length: %d",
  267. spi_drv->config->bus_name,
  268. (uint32_t)message->send_buf,
  269. (uint32_t)message->recv_buf, message->length);
  270. message_length = message->length;
  271. recv_buf = message->recv_buf;
  272. send_buf = message->send_buf;
  273. while (message_length)
  274. {
  275. /* the HAL library use uint16 to save the data length */
  276. if (message_length > 65535)
  277. {
  278. send_length = 65535;
  279. message_length = message_length - 65535;
  280. }
  281. else
  282. {
  283. send_length = message_length;
  284. message_length = 0;
  285. }
  286. /* calculate the start address */
  287. already_send_length = message->length - send_length - message_length;
  288. send_buf = (rt_uint8_t *)message->send_buf + already_send_length;
  289. recv_buf = (rt_uint8_t *)message->recv_buf + already_send_length;
  290. #if defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
  291. rt_uint32_t* dma_buf = RT_NULL;
  292. if ((spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG) && (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG))
  293. {
  294. dma_buf = (rt_uint32_t *)rt_malloc_align(send_length,32);
  295. if(send_buf)
  296. {
  297. rt_memcpy(dma_buf, send_buf, send_length);
  298. }
  299. else
  300. {
  301. rt_memset(dma_buf, 0xFF, send_length);
  302. }
  303. rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, dma_buf, send_length);
  304. state = HAL_SPI_TransmitReceive_DMA(spi_handle, (uint8_t *)dma_buf, (uint8_t *)dma_buf, send_length);
  305. }
  306. else
  307. #endif /* SOC_SERIES_STM32H7 || SOC_SERIES_STM32F7 */
  308. /* start once data exchange in DMA mode */
  309. if (message->send_buf && message->recv_buf)
  310. {
  311. if ((spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG) && (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG))
  312. {
  313. state = HAL_SPI_TransmitReceive_DMA(spi_handle, (uint8_t *)send_buf, (uint8_t *)recv_buf, send_length);
  314. }
  315. else
  316. {
  317. state = HAL_SPI_TransmitReceive(spi_handle, (uint8_t *)send_buf, (uint8_t *)recv_buf, send_length, 1000);
  318. }
  319. }
  320. else if (message->send_buf)
  321. {
  322. if (spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG)
  323. {
  324. state = HAL_SPI_Transmit_DMA(spi_handle, (uint8_t *)send_buf, send_length);
  325. }
  326. else
  327. {
  328. state = HAL_SPI_Transmit(spi_handle, (uint8_t *)send_buf, send_length, 1000);
  329. }
  330. if (message->cs_release && (device->config.mode & RT_SPI_3WIRE))
  331. {
  332. /* release the CS by disable SPI when using 3 wires SPI */
  333. __HAL_SPI_DISABLE(spi_handle);
  334. }
  335. }
  336. else
  337. {
  338. memset((uint8_t *)recv_buf, 0xff, send_length);
  339. if (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG)
  340. {
  341. state = HAL_SPI_Receive_DMA(spi_handle, (uint8_t *)recv_buf, send_length);
  342. }
  343. else
  344. {
  345. /* clear the old error flag */
  346. __HAL_SPI_CLEAR_OVRFLAG(spi_handle);
  347. state = HAL_SPI_Receive(spi_handle, (uint8_t *)recv_buf, send_length, 1000);
  348. }
  349. }
  350. if (state != HAL_OK)
  351. {
  352. LOG_I("spi transfer error : %d", state);
  353. message->length = 0;
  354. spi_handle->State = HAL_SPI_STATE_READY;
  355. }
  356. else
  357. {
  358. LOG_D("%s transfer done", spi_drv->config->bus_name);
  359. }
  360. /* For simplicity reasons, this example is just waiting till the end of the
  361. transfer, but application may perform other tasks while transfer operation
  362. is ongoing. */
  363. if (spi_drv->spi_dma_flag & (SPI_USING_TX_DMA_FLAG | SPI_USING_RX_DMA_FLAG))
  364. {
  365. /* blocking the thread,and the other tasks can run */
  366. rt_completion_wait(&spi_drv->cpt, RT_WAITING_FOREVER);
  367. }
  368. else
  369. {
  370. while (HAL_SPI_GetState(spi_handle) != HAL_SPI_STATE_READY);
  371. }
  372. #if defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
  373. if(dma_buf)
  374. {
  375. if(recv_buf)
  376. {
  377. rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, dma_buf, send_length);
  378. rt_memcpy(recv_buf, dma_buf,send_length);
  379. }
  380. rt_free_align(dma_buf);
  381. }
  382. #endif /* SOC_SERIES_STM32H7 || SOC_SERIES_STM32F7 */
  383. }
  384. if (message->cs_release && !(device->config.mode & RT_SPI_NO_CS) && (device->cs_pin != PIN_NONE))
  385. {
  386. if (device->config.mode & RT_SPI_CS_HIGH)
  387. rt_pin_write(device->cs_pin, PIN_LOW);
  388. else
  389. rt_pin_write(device->cs_pin, PIN_HIGH);
  390. }
  391. return message->length;
  392. }
  393. static rt_err_t spi_configure(struct rt_spi_device *device,
  394. struct rt_spi_configuration *configuration)
  395. {
  396. RT_ASSERT(device != RT_NULL);
  397. RT_ASSERT(configuration != RT_NULL);
  398. struct stm32_spi *spi_drv = rt_container_of(device->bus, struct stm32_spi, spi_bus);
  399. spi_drv->cfg = configuration;
  400. return stm32_spi_init(spi_drv, configuration);
  401. }
  402. static const struct rt_spi_ops stm_spi_ops =
  403. {
  404. .configure = spi_configure,
  405. .xfer = spixfer,
  406. };
  407. static int rt_hw_spi_bus_init(void)
  408. {
  409. rt_err_t result;
  410. for (rt_size_t i = 0; i < sizeof(spi_config) / sizeof(spi_config[0]); i++)
  411. {
  412. spi_bus_obj[i].config = &spi_config[i];
  413. spi_bus_obj[i].spi_bus.parent.user_data = &spi_config[i];
  414. spi_bus_obj[i].handle.Instance = spi_config[i].Instance;
  415. if (spi_bus_obj[i].spi_dma_flag & SPI_USING_RX_DMA_FLAG)
  416. {
  417. /* Configure the DMA handler for Transmission process */
  418. spi_bus_obj[i].dma.handle_rx.Instance = spi_config[i].dma_rx->Instance;
  419. #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
  420. spi_bus_obj[i].dma.handle_rx.Init.Channel = spi_config[i].dma_rx->channel;
  421. #elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
  422. spi_bus_obj[i].dma.handle_rx.Init.Request = spi_config[i].dma_rx->request;
  423. #endif
  424. spi_bus_obj[i].dma.handle_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
  425. spi_bus_obj[i].dma.handle_rx.Init.PeriphInc = DMA_PINC_DISABLE;
  426. spi_bus_obj[i].dma.handle_rx.Init.MemInc = DMA_MINC_ENABLE;
  427. spi_bus_obj[i].dma.handle_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
  428. spi_bus_obj[i].dma.handle_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
  429. spi_bus_obj[i].dma.handle_rx.Init.Mode = DMA_NORMAL;
  430. spi_bus_obj[i].dma.handle_rx.Init.Priority = DMA_PRIORITY_HIGH;
  431. #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7)
  432. spi_bus_obj[i].dma.handle_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
  433. spi_bus_obj[i].dma.handle_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
  434. spi_bus_obj[i].dma.handle_rx.Init.MemBurst = DMA_MBURST_INC4;
  435. spi_bus_obj[i].dma.handle_rx.Init.PeriphBurst = DMA_PBURST_INC4;
  436. #endif
  437. {
  438. rt_uint32_t tmpreg = 0x00U;
  439. #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32F0)
  440. /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
  441. SET_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
  442. tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
  443. #elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
  444. SET_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc);
  445. /* Delay after an RCC peripheral clock enabling */
  446. tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc);
  447. #elif defined(SOC_SERIES_STM32MP1)
  448. __HAL_RCC_DMAMUX_CLK_ENABLE();
  449. SET_BIT(RCC->MP_AHB2ENSETR, spi_config[i].dma_rx->dma_rcc);
  450. tmpreg = READ_BIT(RCC->MP_AHB2ENSETR, spi_config[i].dma_rx->dma_rcc);
  451. #endif
  452. UNUSED(tmpreg); /* To avoid compiler warnings */
  453. }
  454. }
  455. if (spi_bus_obj[i].spi_dma_flag & SPI_USING_TX_DMA_FLAG)
  456. {
  457. /* Configure the DMA handler for Transmission process */
  458. spi_bus_obj[i].dma.handle_tx.Instance = spi_config[i].dma_tx->Instance;
  459. #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
  460. spi_bus_obj[i].dma.handle_tx.Init.Channel = spi_config[i].dma_tx->channel;
  461. #elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
  462. spi_bus_obj[i].dma.handle_tx.Init.Request = spi_config[i].dma_tx->request;
  463. #endif
  464. spi_bus_obj[i].dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
  465. spi_bus_obj[i].dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE;
  466. spi_bus_obj[i].dma.handle_tx.Init.MemInc = DMA_MINC_ENABLE;
  467. spi_bus_obj[i].dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
  468. spi_bus_obj[i].dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
  469. spi_bus_obj[i].dma.handle_tx.Init.Mode = DMA_NORMAL;
  470. spi_bus_obj[i].dma.handle_tx.Init.Priority = DMA_PRIORITY_LOW;
  471. #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7)
  472. spi_bus_obj[i].dma.handle_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
  473. spi_bus_obj[i].dma.handle_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
  474. spi_bus_obj[i].dma.handle_tx.Init.MemBurst = DMA_MBURST_INC4;
  475. spi_bus_obj[i].dma.handle_tx.Init.PeriphBurst = DMA_PBURST_INC4;
  476. #endif
  477. {
  478. rt_uint32_t tmpreg = 0x00U;
  479. #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32F0)
  480. /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
  481. SET_BIT(RCC->AHBENR, spi_config[i].dma_tx->dma_rcc);
  482. tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_tx->dma_rcc);
  483. #elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
  484. SET_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc);
  485. /* Delay after an RCC peripheral clock enabling */
  486. tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc);
  487. #elif defined(SOC_SERIES_STM32MP1)
  488. __HAL_RCC_DMAMUX_CLK_ENABLE();
  489. SET_BIT(RCC->MP_AHB2ENSETR, spi_config[i].dma_tx->dma_rcc);
  490. tmpreg = READ_BIT(RCC->MP_AHB2ENSETR, spi_config[i].dma_tx->dma_rcc);
  491. #endif
  492. UNUSED(tmpreg); /* To avoid compiler warnings */
  493. }
  494. }
  495. /* initialize completion object */
  496. rt_completion_init(&spi_bus_obj[i].cpt);
  497. result = rt_spi_bus_register(&spi_bus_obj[i].spi_bus, spi_config[i].bus_name, &stm_spi_ops);
  498. RT_ASSERT(result == RT_EOK);
  499. LOG_D("%s bus init done", spi_config[i].bus_name);
  500. }
  501. return result;
  502. }
  503. /**
  504. * Attach the spi device to SPI bus, this function must be used after initialization.
  505. */
  506. rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin)
  507. {
  508. RT_ASSERT(bus_name != RT_NULL);
  509. RT_ASSERT(device_name != RT_NULL);
  510. rt_err_t result;
  511. struct rt_spi_device *spi_device;
  512. /* attach the device to spi bus*/
  513. spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
  514. RT_ASSERT(spi_device != RT_NULL);
  515. result = rt_spi_bus_attach_device_cspin(spi_device, device_name, bus_name, cs_pin, RT_NULL);
  516. if (result != RT_EOK)
  517. {
  518. LOG_E("%s attach to %s faild, %d\n", device_name, bus_name, result);
  519. }
  520. RT_ASSERT(result == RT_EOK);
  521. LOG_D("%s attach to %s done", device_name, bus_name);
  522. return result;
  523. }
  524. #if defined(BSP_SPI1_TX_USING_DMA) || defined(BSP_SPI1_RX_USING_DMA)
  525. void SPI1_IRQHandler(void)
  526. {
  527. /* enter interrupt */
  528. rt_interrupt_enter();
  529. HAL_SPI_IRQHandler(&spi_bus_obj[SPI1_INDEX].handle);
  530. /* leave interrupt */
  531. rt_interrupt_leave();
  532. }
  533. #endif
  534. #if defined(BSP_USING_SPI1) && defined(BSP_SPI1_RX_USING_DMA)
  535. /**
  536. * @brief This function handles DMA Rx interrupt request.
  537. * @param None
  538. * @retval None
  539. */
  540. void SPI1_DMA_RX_IRQHandler(void)
  541. {
  542. /* enter interrupt */
  543. rt_interrupt_enter();
  544. HAL_DMA_IRQHandler(&spi_bus_obj[SPI1_INDEX].dma.handle_rx);
  545. /* leave interrupt */
  546. rt_interrupt_leave();
  547. }
  548. #endif
  549. #if defined(BSP_USING_SPI1) && defined(BSP_SPI1_TX_USING_DMA)
  550. /**
  551. * @brief This function handles DMA Tx interrupt request.
  552. * @param None
  553. * @retval None
  554. */
  555. void SPI1_DMA_TX_IRQHandler(void)
  556. {
  557. /* enter interrupt */
  558. rt_interrupt_enter();
  559. HAL_DMA_IRQHandler(&spi_bus_obj[SPI1_INDEX].dma.handle_tx);
  560. /* leave interrupt */
  561. rt_interrupt_leave();
  562. }
  563. #endif /* defined(BSP_USING_SPI1) && defined(BSP_SPI_USING_DMA) */
  564. #if defined(BSP_SPI2_TX_USING_DMA) || defined(BSP_SPI2_RX_USING_DMA)
  565. void SPI2_IRQHandler(void)
  566. {
  567. /* enter interrupt */
  568. rt_interrupt_enter();
  569. HAL_SPI_IRQHandler(&spi_bus_obj[SPI2_INDEX].handle);
  570. /* leave interrupt */
  571. rt_interrupt_leave();
  572. }
  573. #endif
  574. #if defined(BSP_USING_SPI2) && defined(BSP_SPI2_RX_USING_DMA)
  575. /**
  576. * @brief This function handles DMA Rx interrupt request.
  577. * @param None
  578. * @retval None
  579. */
  580. void SPI2_DMA_RX_IRQHandler(void)
  581. {
  582. /* enter interrupt */
  583. rt_interrupt_enter();
  584. HAL_DMA_IRQHandler(&spi_bus_obj[SPI2_INDEX].dma.handle_rx);
  585. /* leave interrupt */
  586. rt_interrupt_leave();
  587. }
  588. #endif
  589. #if defined(BSP_USING_SPI2) && defined(BSP_SPI2_TX_USING_DMA)
  590. /**
  591. * @brief This function handles DMA Tx interrupt request.
  592. * @param None
  593. * @retval None
  594. */
  595. void SPI2_DMA_TX_IRQHandler(void)
  596. {
  597. /* enter interrupt */
  598. rt_interrupt_enter();
  599. HAL_DMA_IRQHandler(&spi_bus_obj[SPI2_INDEX].dma.handle_tx);
  600. /* leave interrupt */
  601. rt_interrupt_leave();
  602. }
  603. #endif /* defined(BSP_USING_SPI2) && defined(BSP_SPI_USING_DMA) */
  604. #if defined(BSP_SPI3_TX_USING_DMA) || defined(BSP_SPI3_RX_USING_DMA)
  605. void SPI3_IRQHandler(void)
  606. {
  607. /* enter interrupt */
  608. rt_interrupt_enter();
  609. HAL_SPI_IRQHandler(&spi_bus_obj[SPI3_INDEX].handle);
  610. /* leave interrupt */
  611. rt_interrupt_leave();
  612. }
  613. #endif
  614. #if defined(BSP_USING_SPI3) && defined(BSP_SPI3_RX_USING_DMA)
  615. /**
  616. * @brief This function handles DMA Rx interrupt request.
  617. * @param None
  618. * @retval None
  619. */
  620. void SPI3_DMA_RX_IRQHandler(void)
  621. {
  622. /* enter interrupt */
  623. rt_interrupt_enter();
  624. HAL_DMA_IRQHandler(&spi_bus_obj[SPI3_INDEX].dma.handle_rx);
  625. /* leave interrupt */
  626. rt_interrupt_leave();
  627. }
  628. #endif
  629. #if defined(BSP_USING_SPI3) && defined(BSP_SPI3_TX_USING_DMA)
  630. /**
  631. * @brief This function handles DMA Tx interrupt request.
  632. * @param None
  633. * @retval None
  634. */
  635. void SPI3_DMA_TX_IRQHandler(void)
  636. {
  637. /* enter interrupt */
  638. rt_interrupt_enter();
  639. HAL_DMA_IRQHandler(&spi_bus_obj[SPI3_INDEX].dma.handle_tx);
  640. /* leave interrupt */
  641. rt_interrupt_leave();
  642. }
  643. #endif /* defined(BSP_USING_SPI3) && defined(BSP_SPI_USING_DMA) */
  644. #if defined(BSP_SPI4_TX_USING_DMA) || defined(BSP_SPI4_RX_USING_DMA)
  645. void SPI4_IRQHandler(void)
  646. {
  647. /* enter interrupt */
  648. rt_interrupt_enter();
  649. HAL_SPI_IRQHandler(&spi_bus_obj[SPI4_INDEX].handle);
  650. /* leave interrupt */
  651. rt_interrupt_leave();
  652. }
  653. #endif
  654. #if defined(BSP_USING_SPI4) && defined(BSP_SPI4_RX_USING_DMA)
  655. /**
  656. * @brief This function handles DMA Rx interrupt request.
  657. * @param None
  658. * @retval None
  659. */
  660. void SPI4_DMA_RX_IRQHandler(void)
  661. {
  662. /* enter interrupt */
  663. rt_interrupt_enter();
  664. HAL_DMA_IRQHandler(&spi_bus_obj[SPI4_INDEX].dma.handle_rx);
  665. /* leave interrupt */
  666. rt_interrupt_leave();
  667. }
  668. #endif
  669. #if defined(BSP_USING_SPI4) && defined(BSP_SPI4_TX_USING_DMA)
  670. /**
  671. * @brief This function handles DMA Tx interrupt request.
  672. * @param None
  673. * @retval None
  674. */
  675. void SPI4_DMA_TX_IRQHandler(void)
  676. {
  677. /* enter interrupt */
  678. rt_interrupt_enter();
  679. HAL_DMA_IRQHandler(&spi_bus_obj[SPI4_INDEX].dma.handle_tx);
  680. /* leave interrupt */
  681. rt_interrupt_leave();
  682. }
  683. #endif /* defined(BSP_USING_SPI4) && defined(BSP_SPI_USING_DMA) */
  684. #if defined(BSP_SPI5_TX_USING_DMA) || defined(BSP_SPI5_RX_USING_DMA)
  685. void SPI5_IRQHandler(void)
  686. {
  687. /* enter interrupt */
  688. rt_interrupt_enter();
  689. HAL_SPI_IRQHandler(&spi_bus_obj[SPI5_INDEX].handle);
  690. /* leave interrupt */
  691. rt_interrupt_leave();
  692. }
  693. #endif
  694. #if defined(BSP_USING_SPI5) && defined(BSP_SPI5_RX_USING_DMA)
  695. /**
  696. * @brief This function handles DMA Rx interrupt request.
  697. * @param None
  698. * @retval None
  699. */
  700. void SPI5_DMA_RX_IRQHandler(void)
  701. {
  702. /* enter interrupt */
  703. rt_interrupt_enter();
  704. HAL_DMA_IRQHandler(&spi_bus_obj[SPI5_INDEX].dma.handle_rx);
  705. /* leave interrupt */
  706. rt_interrupt_leave();
  707. }
  708. #endif
  709. #if defined(BSP_USING_SPI5) && defined(BSP_SPI5_TX_USING_DMA)
  710. /**
  711. * @brief This function handles DMA Tx interrupt request.
  712. * @param None
  713. * @retval None
  714. */
  715. void SPI5_DMA_TX_IRQHandler(void)
  716. {
  717. /* enter interrupt */
  718. rt_interrupt_enter();
  719. HAL_DMA_IRQHandler(&spi_bus_obj[SPI5_INDEX].dma.handle_tx);
  720. /* leave interrupt */
  721. rt_interrupt_leave();
  722. }
  723. #endif /* defined(BSP_USING_SPI5) && defined(BSP_SPI_USING_DMA) */
  724. #if defined(BSP_USING_SPI6) && defined(BSP_SPI6_RX_USING_DMA)
  725. /**
  726. * @brief This function handles DMA Rx interrupt request.
  727. * @param None
  728. * @retval None
  729. */
  730. void SPI6_DMA_RX_IRQHandler(void)
  731. {
  732. /* enter interrupt */
  733. rt_interrupt_enter();
  734. HAL_DMA_IRQHandler(&spi_bus_obj[SPI6_INDEX].dma.handle_rx);
  735. /* leave interrupt */
  736. rt_interrupt_leave();
  737. }
  738. #endif
  739. #if defined(BSP_USING_SPI6) && defined(BSP_SPI6_TX_USING_DMA)
  740. /**
  741. * @brief This function handles DMA Tx interrupt request.
  742. * @param None
  743. * @retval None
  744. */
  745. void SPI6_DMA_TX_IRQHandler(void)
  746. {
  747. /* enter interrupt */
  748. rt_interrupt_enter();
  749. HAL_DMA_IRQHandler(&spi_bus_obj[SPI6_INDEX].dma.handle_tx);
  750. /* leave interrupt */
  751. rt_interrupt_leave();
  752. }
  753. #endif /* defined(BSP_USING_SPI6) && defined(BSP_SPI_USING_DMA) */
  754. static void stm32_get_dma_info(void)
  755. {
  756. #ifdef BSP_SPI1_RX_USING_DMA
  757. spi_bus_obj[SPI1_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
  758. static struct dma_config spi1_dma_rx = SPI1_RX_DMA_CONFIG;
  759. spi_config[SPI1_INDEX].dma_rx = &spi1_dma_rx;
  760. #endif
  761. #ifdef BSP_SPI1_TX_USING_DMA
  762. spi_bus_obj[SPI1_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
  763. static struct dma_config spi1_dma_tx = SPI1_TX_DMA_CONFIG;
  764. spi_config[SPI1_INDEX].dma_tx = &spi1_dma_tx;
  765. #endif
  766. #ifdef BSP_SPI2_RX_USING_DMA
  767. spi_bus_obj[SPI2_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
  768. static struct dma_config spi2_dma_rx = SPI2_RX_DMA_CONFIG;
  769. spi_config[SPI2_INDEX].dma_rx = &spi2_dma_rx;
  770. #endif
  771. #ifdef BSP_SPI2_TX_USING_DMA
  772. spi_bus_obj[SPI2_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
  773. static struct dma_config spi2_dma_tx = SPI2_TX_DMA_CONFIG;
  774. spi_config[SPI2_INDEX].dma_tx = &spi2_dma_tx;
  775. #endif
  776. #ifdef BSP_SPI3_RX_USING_DMA
  777. spi_bus_obj[SPI3_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
  778. static struct dma_config spi3_dma_rx = SPI3_RX_DMA_CONFIG;
  779. spi_config[SPI3_INDEX].dma_rx = &spi3_dma_rx;
  780. #endif
  781. #ifdef BSP_SPI3_TX_USING_DMA
  782. spi_bus_obj[SPI3_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
  783. static struct dma_config spi3_dma_tx = SPI3_TX_DMA_CONFIG;
  784. spi_config[SPI3_INDEX].dma_tx = &spi3_dma_tx;
  785. #endif
  786. #ifdef BSP_SPI4_RX_USING_DMA
  787. spi_bus_obj[SPI4_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
  788. static struct dma_config spi4_dma_rx = SPI4_RX_DMA_CONFIG;
  789. spi_config[SPI4_INDEX].dma_rx = &spi4_dma_rx;
  790. #endif
  791. #ifdef BSP_SPI4_TX_USING_DMA
  792. spi_bus_obj[SPI4_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
  793. static struct dma_config spi4_dma_tx = SPI4_TX_DMA_CONFIG;
  794. spi_config[SPI4_INDEX].dma_tx = &spi4_dma_tx;
  795. #endif
  796. #ifdef BSP_SPI5_RX_USING_DMA
  797. spi_bus_obj[SPI5_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
  798. static struct dma_config spi5_dma_rx = SPI5_RX_DMA_CONFIG;
  799. spi_config[SPI5_INDEX].dma_rx = &spi5_dma_rx;
  800. #endif
  801. #ifdef BSP_SPI5_TX_USING_DMA
  802. spi_bus_obj[SPI5_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
  803. static struct dma_config spi5_dma_tx = SPI5_TX_DMA_CONFIG;
  804. spi_config[SPI5_INDEX].dma_tx = &spi5_dma_tx;
  805. #endif
  806. #ifdef BSP_SPI6_RX_USING_DMA
  807. spi_bus_obj[SPI6_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
  808. static struct dma_config spi6_dma_rx = SPI6_RX_DMA_CONFIG;
  809. spi_config[SPI6_INDEX].dma_rx = &spi6_dma_rx;
  810. #endif
  811. #ifdef BSP_SPI6_TX_USING_DMA
  812. spi_bus_obj[SPI6_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
  813. static struct dma_config spi6_dma_tx = SPI6_TX_DMA_CONFIG;
  814. spi_config[SPI6_INDEX].dma_tx = &spi6_dma_tx;
  815. #endif
  816. }
  817. void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
  818. {
  819. struct stm32_spi *spi_drv = rt_container_of(hspi, struct stm32_spi, handle);
  820. rt_completion_done(&spi_drv->cpt);
  821. }
  822. void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
  823. {
  824. struct stm32_spi *spi_drv = rt_container_of(hspi, struct stm32_spi, handle);
  825. rt_completion_done(&spi_drv->cpt);
  826. }
  827. void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
  828. {
  829. struct stm32_spi *spi_drv = rt_container_of(hspi, struct stm32_spi, handle);
  830. rt_completion_done(&spi_drv->cpt);
  831. }
  832. #if defined(SOC_SERIES_STM32F0)
  833. void SPI1_DMA_RX_TX_IRQHandler(void)
  834. {
  835. #if defined(BSP_USING_SPI1) && defined(BSP_SPI1_TX_USING_DMA)
  836. SPI1_DMA_TX_IRQHandler();
  837. #endif
  838. #if defined(BSP_USING_SPI1) && defined(BSP_SPI1_RX_USING_DMA)
  839. SPI1_DMA_RX_IRQHandler();
  840. #endif
  841. }
  842. void SPI2_DMA_RX_TX_IRQHandler(void)
  843. {
  844. #if defined(BSP_USING_SPI2) && defined(BSP_SPI2_TX_USING_DMA)
  845. SPI2_DMA_TX_IRQHandler();
  846. #endif
  847. #if defined(BSP_USING_SPI2) && defined(BSP_SPI2_RX_USING_DMA)
  848. SPI2_DMA_RX_IRQHandler();
  849. #endif
  850. }
  851. #endif /* SOC_SERIES_STM32F0 */
  852. int rt_hw_spi_init(void)
  853. {
  854. stm32_get_dma_info();
  855. return rt_hw_spi_bus_init();
  856. }
  857. INIT_BOARD_EXPORT(rt_hw_spi_init);
  858. #endif /* BSP_USING_SPI1 || BSP_USING_SPI2 || BSP_USING_SPI3 || BSP_USING_SPI4 || BSP_USING_SPI5 */
  859. #endif /* BSP_USING_SPI */