drv_rtc.c 4.9 KB

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  1. /*
  2. * Copyright (c) 2020-2021, Bluetrum Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2021-01-28 greedyhao first version
  9. */
  10. #include "board.h"
  11. #include <time.h>
  12. #ifdef BSP_USING_ONCHIP_RTC
  13. //#define DRV_DEBUG
  14. #define LOG_TAG "drv.rtc"
  15. #include <drv_log.h>
  16. static struct rt_device rtc;
  17. /************** HAL Start *******************/
  18. #define IRTC_ENTER_CRITICAL() uint32_t cpu_ie = PICCON & BIT(0); PICCONCLR = BIT(0);
  19. #define IRTC_EXIT_CRITICAL() PICCON |= cpu_ie
  20. uint8_t get_weekday(struct tm *const _tm)
  21. {
  22. uint8_t weekday;
  23. time_t secs = mktime(_tm);
  24. weekday = (secs / 86400 + 4) % 7;
  25. return weekday;
  26. }
  27. void irtc_write(uint32_t cmd)
  28. {
  29. RTCDAT = cmd;
  30. while (RTCCON & RTC_CON_TRANS_DONE);
  31. }
  32. uint8_t irtc_read(void)
  33. {
  34. RTCDAT = 0x00;
  35. while (RTCCON & RTC_CON_TRANS_DONE);
  36. return (uint8_t)RTCDAT;
  37. }
  38. void irtc_time_write(uint32_t cmd, uint32_t dat)
  39. {
  40. IRTC_ENTER_CRITICAL();
  41. RTCCON |= RTC_CON_CHIP_SELECT;
  42. irtc_write(cmd | RTC_WR);
  43. irtc_write((uint8_t)(dat >> 24));
  44. irtc_write((uint8_t)(dat >> 16));
  45. irtc_write((uint8_t)(dat >> 8));
  46. irtc_write((uint8_t)(dat >> 0));
  47. RTCCON &= ~RTC_CON_CHIP_SELECT;
  48. IRTC_EXIT_CRITICAL();
  49. }
  50. uint32_t irtc_time_read(uint32_t cmd)
  51. {
  52. uint32_t rd_val;
  53. IRTC_ENTER_CRITICAL();
  54. RTCCON |= RTC_CON_CHIP_SELECT;
  55. irtc_write(cmd | RTC_RD);
  56. *((uint8_t *)&rd_val + 3) = irtc_read();
  57. *((uint8_t *)&rd_val + 2) = irtc_read();
  58. *((uint8_t *)&rd_val + 1) = irtc_read();
  59. *((uint8_t *)&rd_val + 0) = irtc_read();
  60. RTCCON &= ~RTC_CON_CHIP_SELECT;
  61. IRTC_EXIT_CRITICAL();
  62. return rd_val;
  63. }
  64. void irtc_sfr_write(uint32_t cmd, uint8_t dat)
  65. {
  66. IRTC_ENTER_CRITICAL();
  67. RTCCON |= RTC_CON_CHIP_SELECT;
  68. irtc_write(cmd | RTC_WR);
  69. irtc_write(dat);
  70. RTCCON &= ~RTC_CON_CHIP_SELECT;
  71. IRTC_EXIT_CRITICAL();
  72. }
  73. uint8_t irtc_sfr_read(uint32_t cmd)
  74. {
  75. uint8_t rd_val;
  76. IRTC_ENTER_CRITICAL();
  77. RTCCON |= RTC_CON_CHIP_SELECT;
  78. irtc_write(cmd | RTC_RD);
  79. rd_val = irtc_read();
  80. RTCCON &= ~RTC_CON_CHIP_SELECT;
  81. IRTC_EXIT_CRITICAL();
  82. }
  83. void hal_rtc_init(void)
  84. {
  85. time_t sec = 0;
  86. struct tm tm_new = {0};
  87. uint8_t temp = irtc_sfr_read(RTCCON0_CMD);
  88. temp &= ~RTC_CON0_XOSC32K_ENABLE;
  89. temp |= RTC_CON0_EXTERNAL_32K;
  90. irtc_sfr_write(RTCCON0_CMD, temp);
  91. temp = irtc_sfr_read(RTCCON2_CMD);
  92. irtc_sfr_write(RTCCON2_CMD, temp | RTC_CON2_32K_SELECT);
  93. temp = irtc_sfr_read(RTCCON0_CMD);
  94. if (temp & BIT(7)) {
  95. temp &= ~BIT(7);
  96. irtc_sfr_write(RTCCON0_CMD, temp); /* First power on */
  97. }
  98. tm_new.tm_mday = 29;
  99. tm_new.tm_mon = 1 - 1;
  100. tm_new.tm_year = 2021 - 1900;
  101. sec = mktime(&tm_new);
  102. irtc_time_write(RTCCNT_CMD, sec);
  103. }
  104. /************** HAL End *******************/
  105. static time_t get_rtc_timestamp(void)
  106. {
  107. time_t sec = 0;
  108. sec = irtc_time_read(RTCCNT_CMD);
  109. LOG_D("get rtc time.");
  110. return sec;
  111. }
  112. static rt_err_t set_rtc_time_stamp(time_t time_stamp)
  113. {
  114. irtc_time_write(RTCCNT_CMD, time_stamp);
  115. return RT_EOK;
  116. }
  117. static void rt_rtc_init(void)
  118. {
  119. hal_rtc_init();
  120. }
  121. static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args)
  122. {
  123. rt_err_t result = RT_EOK;
  124. RT_ASSERT(dev != RT_NULL);
  125. switch (cmd)
  126. {
  127. case RT_DEVICE_CTRL_RTC_GET_TIME:
  128. *(rt_uint32_t *)args = get_rtc_timestamp();
  129. LOG_D("RTC: get rtc_time %x\n", *(rt_uint32_t *)args);
  130. break;
  131. case RT_DEVICE_CTRL_RTC_SET_TIME:
  132. if (set_rtc_time_stamp(*(rt_uint32_t *)args))
  133. {
  134. result = -RT_ERROR;
  135. }
  136. LOG_D("RTC: set rtc_time %x\n", *(rt_uint32_t *)args);
  137. break;
  138. }
  139. return result;
  140. }
  141. #ifdef RT_USING_DEVICE_OPS
  142. const static struct rt_device_ops rtc_ops =
  143. {
  144. RT_NULL,
  145. RT_NULL,
  146. RT_NULL,
  147. RT_NULL,
  148. RT_NULL,
  149. rt_rtc_control
  150. };
  151. #endif
  152. static rt_err_t rt_hw_rtc_register(rt_device_t device, const char *name, rt_uint32_t flag)
  153. {
  154. RT_ASSERT(device != RT_NULL);
  155. rt_rtc_init();
  156. #ifdef RT_USING_DEVICE_OPS
  157. device->ops = &rtc_ops;
  158. #else
  159. device->init = RT_NULL;
  160. device->open = RT_NULL;
  161. device->close = RT_NULL;
  162. device->read = RT_NULL;
  163. device->write = RT_NULL;
  164. device->control = rt_rtc_control;
  165. #endif
  166. device->type = RT_Device_Class_RTC;
  167. device->rx_indicate = RT_NULL;
  168. device->tx_complete = RT_NULL;
  169. device->user_data = RT_NULL;
  170. /* register a character device */
  171. return rt_device_register(device, name, flag);
  172. }
  173. int rt_hw_rtc_init(void)
  174. {
  175. rt_err_t result;
  176. result = rt_hw_rtc_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR);
  177. if (result != RT_EOK)
  178. {
  179. LOG_E("rtc register err code: %d", result);
  180. return result;
  181. }
  182. LOG_D("rtc init success");
  183. return RT_EOK;
  184. }
  185. INIT_DEVICE_EXPORT(rt_hw_rtc_init);
  186. #endif /* BSP_USING_ONCHIP_RTC */