drv_usart.c 38 KB

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  1. /*
  2. * Copyright (c) 2006-2024, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-10-30 SummerGift first version
  9. * 2020-03-16 SummerGift add device close feature
  10. * 2020-03-20 SummerGift fix bug caused by ORE
  11. * 2020-05-02 whj4674672 support stm32h7 uart dma
  12. * 2020-09-09 forest-rain support stm32wl uart
  13. * 2020-10-14 Dozingfiretruck Porting for stm32wbxx
  14. */
  15. #include "board.h"
  16. #include "drv_usart.h"
  17. #include "drv_config.h"
  18. #ifdef RT_USING_SERIAL
  19. //#define DRV_DEBUG
  20. #define LOG_TAG "drv.usart"
  21. #include <drv_log.h>
  22. #if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && \
  23. !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && \
  24. !defined(BSP_USING_UART7) && !defined(BSP_USING_UART8) && !defined(BSP_USING_LPUART1)
  25. #error "Please define at least one BSP_USING_UARTx"
  26. /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
  27. #endif
  28. #ifdef RT_SERIAL_USING_DMA
  29. static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag);
  30. #endif
  31. /* Number of while blocking timeouts for the stm32_putc */
  32. #define TX_BLOCK_TIMEOUT 2000
  33. enum
  34. {
  35. #ifdef BSP_USING_UART1
  36. UART1_INDEX,
  37. #endif
  38. #ifdef BSP_USING_UART2
  39. UART2_INDEX,
  40. #endif
  41. #ifdef BSP_USING_UART3
  42. UART3_INDEX,
  43. #endif
  44. #ifdef BSP_USING_UART4
  45. UART4_INDEX,
  46. #endif
  47. #ifdef BSP_USING_UART5
  48. UART5_INDEX,
  49. #endif
  50. #ifdef BSP_USING_UART6
  51. UART6_INDEX,
  52. #endif
  53. #ifdef BSP_USING_UART7
  54. UART7_INDEX,
  55. #endif
  56. #ifdef BSP_USING_UART8
  57. UART8_INDEX,
  58. #endif
  59. #ifdef BSP_USING_LPUART1
  60. LPUART1_INDEX,
  61. #endif
  62. };
  63. static struct stm32_uart_config uart_config[] =
  64. {
  65. #ifdef BSP_USING_UART1
  66. UART1_CONFIG,
  67. #endif
  68. #ifdef BSP_USING_UART2
  69. UART2_CONFIG,
  70. #endif
  71. #ifdef BSP_USING_UART3
  72. UART3_CONFIG,
  73. #endif
  74. #ifdef BSP_USING_UART4
  75. UART4_CONFIG,
  76. #endif
  77. #ifdef BSP_USING_UART5
  78. UART5_CONFIG,
  79. #endif
  80. #ifdef BSP_USING_UART6
  81. UART6_CONFIG,
  82. #endif
  83. #ifdef BSP_USING_UART7
  84. UART7_CONFIG,
  85. #endif
  86. #ifdef BSP_USING_UART8
  87. UART8_CONFIG,
  88. #endif
  89. #ifdef BSP_USING_LPUART1
  90. LPUART1_CONFIG,
  91. #endif
  92. };
  93. static struct stm32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
  94. rt_uint32_t stm32_uart_get_mask(rt_uint32_t word_length, rt_uint32_t parity)
  95. {
  96. rt_uint32_t mask = 0x00FFU;
  97. if (word_length == UART_WORDLENGTH_8B)
  98. {
  99. if (parity == UART_PARITY_NONE)
  100. {
  101. mask = 0x00FFU ;
  102. }
  103. else
  104. {
  105. mask = 0x007FU ;
  106. }
  107. }
  108. #ifdef UART_WORDLENGTH_9B
  109. else if (word_length == UART_WORDLENGTH_9B)
  110. {
  111. if (parity == UART_PARITY_NONE)
  112. {
  113. mask = 0x01FFU ;
  114. }
  115. else
  116. {
  117. mask = 0x00FFU ;
  118. }
  119. }
  120. #endif
  121. #ifdef UART_WORDLENGTH_7B
  122. else if (word_length == UART_WORDLENGTH_7B)
  123. {
  124. if (parity == UART_PARITY_NONE)
  125. {
  126. mask = 0x007FU ;
  127. }
  128. else
  129. {
  130. mask = 0x003FU ;
  131. }
  132. }
  133. else
  134. {
  135. mask = 0x0000U;
  136. }
  137. #endif
  138. return mask;
  139. }
  140. static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
  141. {
  142. struct stm32_uart *uart;
  143. RT_ASSERT(serial != RT_NULL);
  144. RT_ASSERT(cfg != RT_NULL);
  145. uart = rt_container_of(serial, struct stm32_uart, serial);
  146. uart->handle.Instance = uart->config->Instance;
  147. uart->handle.Init.BaudRate = cfg->baud_rate;
  148. uart->handle.Init.Mode = UART_MODE_TX_RX;
  149. #ifdef USART_CR1_OVER8
  150. uart->handle.Init.OverSampling = cfg->baud_rate > 5000000 ? UART_OVERSAMPLING_8 : UART_OVERSAMPLING_16;
  151. #else
  152. uart->handle.Init.OverSampling = UART_OVERSAMPLING_16;
  153. #endif /* USART_CR1_OVER8 */
  154. switch (cfg->flowcontrol)
  155. {
  156. case RT_SERIAL_FLOWCONTROL_NONE:
  157. uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
  158. break;
  159. case RT_SERIAL_FLOWCONTROL_CTSRTS:
  160. uart->handle.Init.HwFlowCtl = UART_HWCONTROL_RTS_CTS;
  161. break;
  162. default:
  163. uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
  164. break;
  165. }
  166. switch (cfg->data_bits)
  167. {
  168. case DATA_BITS_8:
  169. if (cfg->parity == PARITY_ODD || cfg->parity == PARITY_EVEN)
  170. uart->handle.Init.WordLength = UART_WORDLENGTH_9B;
  171. else
  172. uart->handle.Init.WordLength = UART_WORDLENGTH_8B;
  173. break;
  174. case DATA_BITS_9:
  175. uart->handle.Init.WordLength = UART_WORDLENGTH_9B;
  176. break;
  177. default:
  178. uart->handle.Init.WordLength = UART_WORDLENGTH_8B;
  179. break;
  180. }
  181. switch (cfg->stop_bits)
  182. {
  183. case STOP_BITS_1:
  184. uart->handle.Init.StopBits = UART_STOPBITS_1;
  185. break;
  186. case STOP_BITS_2:
  187. uart->handle.Init.StopBits = UART_STOPBITS_2;
  188. break;
  189. default:
  190. uart->handle.Init.StopBits = UART_STOPBITS_1;
  191. break;
  192. }
  193. switch (cfg->parity)
  194. {
  195. case PARITY_NONE:
  196. uart->handle.Init.Parity = UART_PARITY_NONE;
  197. break;
  198. case PARITY_ODD:
  199. uart->handle.Init.Parity = UART_PARITY_ODD;
  200. break;
  201. case PARITY_EVEN:
  202. uart->handle.Init.Parity = UART_PARITY_EVEN;
  203. break;
  204. default:
  205. uart->handle.Init.Parity = UART_PARITY_NONE;
  206. break;
  207. }
  208. #ifdef RT_SERIAL_USING_DMA
  209. if (!(serial->parent.open_flag & RT_DEVICE_OFLAG_OPEN)) {
  210. uart->dma_rx.remaining_cnt = cfg->bufsz;
  211. }
  212. #endif
  213. if (HAL_UART_Init(&uart->handle) != HAL_OK)
  214. {
  215. return -RT_ERROR;
  216. }
  217. uart->DR_mask = stm32_uart_get_mask(uart->handle.Init.WordLength, uart->handle.Init.Parity);
  218. uart->tx_block_timeout = TX_BLOCK_TIMEOUT;
  219. return RT_EOK;
  220. }
  221. static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *arg)
  222. {
  223. struct stm32_uart *uart;
  224. #ifdef RT_SERIAL_USING_DMA
  225. rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
  226. #endif
  227. RT_ASSERT(serial != RT_NULL);
  228. uart = rt_container_of(serial, struct stm32_uart, serial);
  229. switch (cmd)
  230. {
  231. /* disable interrupt */
  232. case RT_DEVICE_CTRL_CLR_INT:
  233. {
  234. /* disable uart irq */
  235. NVIC_DisableIRQ(uart->config->irq_type);
  236. rt_uint32_t direction = (rt_uint32_t)arg;
  237. if(direction == RT_DEVICE_FLAG_INT_RX)
  238. {
  239. /* disable interrupt */
  240. __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_RXNE);
  241. }
  242. #ifdef RT_SERIAL_USING_DMA
  243. /* disable DMA */
  244. if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX)
  245. {
  246. HAL_NVIC_DisableIRQ(uart->config->dma_rx->dma_irq);
  247. if (HAL_DMA_Abort(&(uart->dma_rx.handle)) != HAL_OK)
  248. {
  249. RT_ASSERT(0);
  250. }
  251. if (HAL_DMA_DeInit(&(uart->dma_rx.handle)) != HAL_OK)
  252. {
  253. RT_ASSERT(0);
  254. }
  255. }
  256. else if(ctrl_arg == RT_DEVICE_FLAG_DMA_TX)
  257. {
  258. HAL_NVIC_DisableIRQ(uart->config->dma_tx->dma_irq);
  259. if (HAL_DMA_DeInit(&(uart->dma_tx.handle)) != HAL_OK)
  260. {
  261. RT_ASSERT(0);
  262. }
  263. }
  264. #endif
  265. break;
  266. }
  267. /* enable interrupt */
  268. case RT_DEVICE_CTRL_SET_INT:
  269. {
  270. /* enable uart irq */
  271. HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0);
  272. HAL_NVIC_EnableIRQ(uart->config->irq_type);
  273. rt_uint32_t direction = (rt_uint32_t)arg;
  274. if(direction == RT_DEVICE_FLAG_INT_RX)
  275. {
  276. /* enable interrupt */
  277. __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_RXNE);
  278. }
  279. break;
  280. }
  281. #ifdef RT_SERIAL_USING_DMA
  282. case RT_DEVICE_CTRL_CONFIG:
  283. {
  284. stm32_dma_config(serial, ctrl_arg);
  285. break;
  286. }
  287. #endif
  288. case RT_DEVICE_CTRL_CLOSE:
  289. {
  290. if (HAL_UART_DeInit(&(uart->handle)) != HAL_OK )
  291. {
  292. RT_ASSERT(0)
  293. }
  294. break;
  295. }
  296. case UART_CTRL_SET_BLOCK_TIMEOUT:
  297. {
  298. rt_uint32_t block_timeout = (rt_uint32_t)arg;
  299. if(block_timeout > 0)
  300. {
  301. uart->tx_block_timeout = block_timeout;
  302. }
  303. else
  304. {
  305. return -RT_ERROR;
  306. }
  307. break;
  308. }
  309. default:
  310. break;
  311. }
  312. return RT_EOK;
  313. }
  314. static int stm32_putc(struct rt_serial_device *serial, char c)
  315. {
  316. struct stm32_uart *uart;
  317. RT_ASSERT(serial != RT_NULL);
  318. uart = rt_container_of(serial, struct stm32_uart, serial);
  319. rt_uint32_t block_timeout = uart->tx_block_timeout;
  320. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
  321. #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
  322. || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L5) \
  323. || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32F3) \
  324. || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS)
  325. uart->handle.Instance->TDR = c;
  326. #else
  327. uart->handle.Instance->DR = c;
  328. #endif
  329. while (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) == RESET && block_timeout--);
  330. return (block_timeout != 0) ? 1 : -1;
  331. }
  332. static int stm32_getc(struct rt_serial_device *serial)
  333. {
  334. int ch;
  335. struct stm32_uart *uart;
  336. RT_ASSERT(serial != RT_NULL);
  337. uart = rt_container_of(serial, struct stm32_uart, serial);
  338. ch = -1;
  339. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET)
  340. {
  341. #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
  342. || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L5) \
  343. || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3) \
  344. || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS)
  345. ch = uart->handle.Instance->RDR & uart->DR_mask;
  346. #else
  347. ch = uart->handle.Instance->DR & uart->DR_mask;
  348. #endif
  349. }
  350. return ch;
  351. }
  352. static rt_ssize_t stm32_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
  353. {
  354. struct stm32_uart *uart;
  355. RT_ASSERT(serial != RT_NULL);
  356. RT_ASSERT(buf != RT_NULL);
  357. uart = rt_container_of(serial, struct stm32_uart, serial);
  358. if (size == 0)
  359. {
  360. return 0;
  361. }
  362. if (RT_SERIAL_DMA_TX == direction)
  363. {
  364. if (HAL_UART_Transmit_DMA(&uart->handle, buf, size) == HAL_OK)
  365. {
  366. return size;
  367. }
  368. else
  369. {
  370. return 0;
  371. }
  372. }
  373. return 0;
  374. }
  375. #ifdef RT_SERIAL_USING_DMA
  376. static void dma_recv_isr(struct rt_serial_device *serial, rt_uint8_t isr_flag)
  377. {
  378. struct stm32_uart *uart;
  379. rt_base_t level;
  380. rt_size_t recv_len, counter;
  381. RT_ASSERT(serial != RT_NULL);
  382. uart = rt_container_of(serial, struct stm32_uart, serial);
  383. level = rt_hw_interrupt_disable();
  384. recv_len = 0;
  385. counter = __HAL_DMA_GET_COUNTER(&(uart->dma_rx.handle));
  386. switch (isr_flag)
  387. {
  388. case UART_RX_DMA_IT_IDLE_FLAG:
  389. if (counter <= uart->dma_rx.remaining_cnt)
  390. recv_len = uart->dma_rx.remaining_cnt - counter;
  391. else
  392. recv_len = serial->config.bufsz + uart->dma_rx.remaining_cnt - counter;
  393. break;
  394. case UART_RX_DMA_IT_HT_FLAG:
  395. if (counter < uart->dma_rx.remaining_cnt)
  396. recv_len = uart->dma_rx.remaining_cnt - counter;
  397. break;
  398. case UART_RX_DMA_IT_TC_FLAG:
  399. if(counter >= uart->dma_rx.remaining_cnt)
  400. recv_len = serial->config.bufsz + uart->dma_rx.remaining_cnt - counter;
  401. default:
  402. break;
  403. }
  404. if (recv_len)
  405. {
  406. uart->dma_rx.remaining_cnt = counter;
  407. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
  408. }
  409. rt_hw_interrupt_enable(level);
  410. }
  411. #endif
  412. /**
  413. * Uart common interrupt process. This need add to uart ISR.
  414. *
  415. * @param serial serial device
  416. */
  417. static void uart_isr(struct rt_serial_device *serial)
  418. {
  419. struct stm32_uart *uart;
  420. RT_ASSERT(serial != RT_NULL);
  421. uart = rt_container_of(serial, struct stm32_uart, serial);
  422. /* UART in mode Receiver -------------------------------------------------*/
  423. if ((__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET) &&
  424. (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_RXNE) != RESET))
  425. {
  426. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
  427. }
  428. else if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) &&
  429. (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_TC) != RESET))
  430. {
  431. if ((serial->parent.open_flag & RT_DEVICE_FLAG_DMA_TX) != 0)
  432. {
  433. HAL_UART_IRQHandler(&(uart->handle));
  434. }
  435. else
  436. {
  437. /* Transmission complete interrupt disable ( CR1 Register) */
  438. __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_TC);
  439. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE);
  440. }
  441. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
  442. }
  443. #ifdef RT_SERIAL_USING_DMA
  444. else if ((uart->uart_dma_flag) && (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_IDLE) != RESET)
  445. && (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_IDLE) != RESET))
  446. {
  447. dma_recv_isr(serial, UART_RX_DMA_IT_IDLE_FLAG);
  448. __HAL_UART_CLEAR_IDLEFLAG(&uart->handle);
  449. }
  450. #endif
  451. else
  452. {
  453. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_ORE) != RESET)
  454. {
  455. __HAL_UART_CLEAR_OREFLAG(&uart->handle);
  456. }
  457. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_NE) != RESET)
  458. {
  459. __HAL_UART_CLEAR_NEFLAG(&uart->handle);
  460. }
  461. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_FE) != RESET)
  462. {
  463. __HAL_UART_CLEAR_FEFLAG(&uart->handle);
  464. }
  465. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_PE) != RESET)
  466. {
  467. __HAL_UART_CLEAR_PEFLAG(&uart->handle);
  468. }
  469. #if !defined(SOC_SERIES_STM32L4) && !defined(SOC_SERIES_STM32WL) && !defined(SOC_SERIES_STM32F7) && !defined(SOC_SERIES_STM32F0) \
  470. && !defined(SOC_SERIES_STM32L0) && !defined(SOC_SERIES_STM32G0) && !defined(SOC_SERIES_STM32H7) \
  471. && !defined(SOC_SERIES_STM32G4) && !defined(SOC_SERIES_STM32MP1) && !defined(SOC_SERIES_STM32WB) \
  472. && !defined(SOC_SERIES_STM32L5) && !defined(SOC_SERIES_STM32U5) && !defined(SOC_SERIES_STM32H5) && !defined(SOC_SERIES_STM32H7RS)
  473. #ifdef SOC_SERIES_STM32F3
  474. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBDF) != RESET)
  475. {
  476. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_LBDF);
  477. }
  478. #else
  479. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBD) != RESET)
  480. {
  481. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_LBD);
  482. }
  483. #endif
  484. #endif
  485. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_CTS) != RESET)
  486. {
  487. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_CTS);
  488. }
  489. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TXE) != RESET)
  490. {
  491. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TXE);
  492. }
  493. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET)
  494. {
  495. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_RXNE);
  496. }
  497. }
  498. }
  499. #if defined(BSP_USING_UART1)
  500. void USART1_IRQHandler(void)
  501. {
  502. /* enter interrupt */
  503. rt_interrupt_enter();
  504. uart_isr(&(uart_obj[UART1_INDEX].serial));
  505. /* leave interrupt */
  506. rt_interrupt_leave();
  507. }
  508. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA)
  509. void UART1_DMA_RX_IRQHandler(void)
  510. {
  511. /* enter interrupt */
  512. rt_interrupt_enter();
  513. HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_rx.handle);
  514. /* leave interrupt */
  515. rt_interrupt_leave();
  516. }
  517. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) */
  518. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA)
  519. void UART1_DMA_TX_IRQHandler(void)
  520. {
  521. /* enter interrupt */
  522. rt_interrupt_enter();
  523. HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_tx.handle);
  524. /* leave interrupt */
  525. rt_interrupt_leave();
  526. }
  527. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA) */
  528. #endif /* BSP_USING_UART1 */
  529. #if defined(BSP_USING_UART2)
  530. void USART2_IRQHandler(void)
  531. {
  532. /* enter interrupt */
  533. rt_interrupt_enter();
  534. uart_isr(&(uart_obj[UART2_INDEX].serial));
  535. /* leave interrupt */
  536. rt_interrupt_leave();
  537. }
  538. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA)
  539. void UART2_DMA_RX_IRQHandler(void)
  540. {
  541. /* enter interrupt */
  542. rt_interrupt_enter();
  543. HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma_rx.handle);
  544. /* leave interrupt */
  545. rt_interrupt_leave();
  546. }
  547. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) */
  548. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA)
  549. void UART2_DMA_TX_IRQHandler(void)
  550. {
  551. /* enter interrupt */
  552. rt_interrupt_enter();
  553. HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma_tx.handle);
  554. /* leave interrupt */
  555. rt_interrupt_leave();
  556. }
  557. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA) */
  558. #endif /* BSP_USING_UART2 */
  559. #if defined(BSP_USING_UART3)
  560. void USART3_IRQHandler(void)
  561. {
  562. /* enter interrupt */
  563. rt_interrupt_enter();
  564. uart_isr(&(uart_obj[UART3_INDEX].serial));
  565. /* leave interrupt */
  566. rt_interrupt_leave();
  567. }
  568. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_RX_USING_DMA)
  569. void UART3_DMA_RX_IRQHandler(void)
  570. {
  571. /* enter interrupt */
  572. rt_interrupt_enter();
  573. HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma_rx.handle);
  574. /* leave interrupt */
  575. rt_interrupt_leave();
  576. }
  577. #endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART3_RX_USING_DMA) */
  578. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_TX_USING_DMA)
  579. void UART3_DMA_TX_IRQHandler(void)
  580. {
  581. /* enter interrupt */
  582. rt_interrupt_enter();
  583. HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma_tx.handle);
  584. /* leave interrupt */
  585. rt_interrupt_leave();
  586. }
  587. #endif /* defined(BSP_UART_USING_DMA_TX) && defined(BSP_UART3_TX_USING_DMA) */
  588. #endif /* BSP_USING_UART3*/
  589. #if defined(BSP_USING_UART4)
  590. void UART4_IRQHandler(void)
  591. {
  592. /* enter interrupt */
  593. rt_interrupt_enter();
  594. uart_isr(&(uart_obj[UART4_INDEX].serial));
  595. /* leave interrupt */
  596. rt_interrupt_leave();
  597. }
  598. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_RX_USING_DMA)
  599. void UART4_DMA_RX_IRQHandler(void)
  600. {
  601. /* enter interrupt */
  602. rt_interrupt_enter();
  603. HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma_rx.handle);
  604. /* leave interrupt */
  605. rt_interrupt_leave();
  606. }
  607. #endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART4_RX_USING_DMA) */
  608. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_TX_USING_DMA)
  609. void UART4_DMA_TX_IRQHandler(void)
  610. {
  611. /* enter interrupt */
  612. rt_interrupt_enter();
  613. HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma_tx.handle);
  614. /* leave interrupt */
  615. rt_interrupt_leave();
  616. }
  617. #endif /* defined(BSP_UART_USING_DMA_TX) && defined(BSP_UART4_TX_USING_DMA) */
  618. #endif /* BSP_USING_UART4*/
  619. #if defined(BSP_USING_UART5)
  620. void UART5_IRQHandler(void)
  621. {
  622. /* enter interrupt */
  623. rt_interrupt_enter();
  624. uart_isr(&(uart_obj[UART5_INDEX].serial));
  625. /* leave interrupt */
  626. rt_interrupt_leave();
  627. }
  628. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA)
  629. void UART5_DMA_RX_IRQHandler(void)
  630. {
  631. /* enter interrupt */
  632. rt_interrupt_enter();
  633. HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma_rx.handle);
  634. /* leave interrupt */
  635. rt_interrupt_leave();
  636. }
  637. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA) */
  638. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA)
  639. void UART5_DMA_TX_IRQHandler(void)
  640. {
  641. /* enter interrupt */
  642. rt_interrupt_enter();
  643. HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma_tx.handle);
  644. /* leave interrupt */
  645. rt_interrupt_leave();
  646. }
  647. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA) */
  648. #endif /* BSP_USING_UART5*/
  649. #if defined(BSP_USING_UART6)
  650. void USART6_IRQHandler(void)
  651. {
  652. /* enter interrupt */
  653. rt_interrupt_enter();
  654. uart_isr(&(uart_obj[UART6_INDEX].serial));
  655. /* leave interrupt */
  656. rt_interrupt_leave();
  657. }
  658. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA)
  659. void UART6_DMA_RX_IRQHandler(void)
  660. {
  661. /* enter interrupt */
  662. rt_interrupt_enter();
  663. HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma_rx.handle);
  664. /* leave interrupt */
  665. rt_interrupt_leave();
  666. }
  667. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA) */
  668. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA)
  669. void UART6_DMA_TX_IRQHandler(void)
  670. {
  671. /* enter interrupt */
  672. rt_interrupt_enter();
  673. HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma_tx.handle);
  674. /* leave interrupt */
  675. rt_interrupt_leave();
  676. }
  677. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA) */
  678. #endif /* BSP_USING_UART6*/
  679. #if defined(BSP_USING_UART7)
  680. void UART7_IRQHandler(void)
  681. {
  682. /* enter interrupt */
  683. rt_interrupt_enter();
  684. uart_isr(&(uart_obj[UART7_INDEX].serial));
  685. /* leave interrupt */
  686. rt_interrupt_leave();
  687. }
  688. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA)
  689. void UART7_DMA_RX_IRQHandler(void)
  690. {
  691. /* enter interrupt */
  692. rt_interrupt_enter();
  693. HAL_DMA_IRQHandler(&uart_obj[UART7_INDEX].dma_rx.handle);
  694. /* leave interrupt */
  695. rt_interrupt_leave();
  696. }
  697. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA) */
  698. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA)
  699. void UART7_DMA_TX_IRQHandler(void)
  700. {
  701. /* enter interrupt */
  702. rt_interrupt_enter();
  703. HAL_DMA_IRQHandler(&uart_obj[UART7_INDEX].dma_tx.handle);
  704. /* leave interrupt */
  705. rt_interrupt_leave();
  706. }
  707. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA) */
  708. #endif /* BSP_USING_UART7*/
  709. #if defined(BSP_USING_UART8)
  710. void UART8_IRQHandler(void)
  711. {
  712. /* enter interrupt */
  713. rt_interrupt_enter();
  714. uart_isr(&(uart_obj[UART8_INDEX].serial));
  715. /* leave interrupt */
  716. rt_interrupt_leave();
  717. }
  718. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA)
  719. void UART8_DMA_RX_IRQHandler(void)
  720. {
  721. /* enter interrupt */
  722. rt_interrupt_enter();
  723. HAL_DMA_IRQHandler(&uart_obj[UART8_INDEX].dma_rx.handle);
  724. /* leave interrupt */
  725. rt_interrupt_leave();
  726. }
  727. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA) */
  728. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA)
  729. void UART8_DMA_TX_IRQHandler(void)
  730. {
  731. /* enter interrupt */
  732. rt_interrupt_enter();
  733. HAL_DMA_IRQHandler(&uart_obj[UART8_INDEX].dma_tx.handle);
  734. /* leave interrupt */
  735. rt_interrupt_leave();
  736. }
  737. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA) */
  738. #endif /* BSP_USING_UART8*/
  739. #if defined(BSP_USING_LPUART1)
  740. void LPUART1_IRQHandler(void)
  741. {
  742. /* enter interrupt */
  743. rt_interrupt_enter();
  744. uart_isr(&(uart_obj[LPUART1_INDEX].serial));
  745. /* leave interrupt */
  746. rt_interrupt_leave();
  747. }
  748. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA)
  749. void LPUART1_DMA_RX_IRQHandler(void)
  750. {
  751. /* enter interrupt */
  752. rt_interrupt_enter();
  753. HAL_DMA_IRQHandler(&uart_obj[LPUART1_INDEX].dma_rx.handle);
  754. /* leave interrupt */
  755. rt_interrupt_leave();
  756. }
  757. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA) */
  758. #endif /* BSP_USING_LPUART1*/
  759. #if defined(SOC_SERIES_STM32G0)
  760. #if defined(BSP_USING_UART2)
  761. #if defined(STM32G0B1xx) || defined(STM32G0C1xx)
  762. void USART2_LPUART2_IRQHandler(void)
  763. {
  764. USART2_IRQHandler();
  765. }
  766. #endif /* defined(STM32G0B1xx) || defined(STM32G0C1xx) */
  767. #endif /* defined(BSP_USING_UART2) */
  768. #if defined(BSP_USING_UART3) || defined(BSP_USING_UART4) || defined(BSP_USING_UART5) || defined(BSP_USING_UART6) \
  769. || defined(BSP_USING_LPUART1)
  770. #if defined(STM32G070xx)
  771. void USART3_4_IRQHandler(void)
  772. #elif defined(STM32G071xx) || defined(STM32G081xx)
  773. void USART3_4_LPUART1_IRQHandler(void)
  774. #elif defined(STM32G0B0xx)
  775. void USART3_4_5_6_IRQHandler(void)
  776. #elif defined(STM32G0B1xx) || defined(STM32G0C1xx)
  777. void USART3_4_5_6_LPUART1_IRQHandler(void)
  778. #endif /* defined(STM32G070xx) */
  779. {
  780. #if defined(BSP_USING_UART3)
  781. USART3_IRQHandler();
  782. #endif
  783. #if defined(BSP_USING_UART4)
  784. UART4_IRQHandler();
  785. #endif
  786. #if defined(BSP_USING_UART5)
  787. UART5_IRQHandler();
  788. #endif
  789. #if defined(BSP_USING_UART6)
  790. USART6_IRQHandler();
  791. #endif
  792. #if defined(BSP_USING_LPUART1)
  793. LPUART1_IRQHandler();
  794. #endif
  795. }
  796. #endif /* defined(BSP_USING_UART3) || defined(BSP_USING_UART4) || defined(BSP_USING_UART5) || defined(BSP_USING_UART6) */
  797. #if defined(RT_SERIAL_USING_DMA)
  798. void UART_DMA_RX_TX_IRQHandler(void)
  799. {
  800. #if defined(BSP_USING_UART1) && defined(BSP_UART1_TX_USING_DMA)
  801. UART1_DMA_TX_IRQHandler();
  802. #endif
  803. #if defined(BSP_USING_UART1) && defined(BSP_UART1_RX_USING_DMA)
  804. UART1_DMA_RX_IRQHandler();
  805. #endif
  806. #if defined(BSP_USING_UART2) && defined(BSP_UART2_TX_USING_DMA)
  807. UART2_DMA_TX_IRQHandler();
  808. #endif
  809. #if defined(BSP_USING_UART2) && defined(BSP_UART2_RX_USING_DMA)
  810. UART2_DMA_RX_IRQHandler();
  811. #endif
  812. }
  813. #endif /* defined(RT_SERIAL_USING_DMA) */
  814. #endif /* defined(SOC_SERIES_STM32G0) */
  815. static void stm32_uart_get_dma_config(void)
  816. {
  817. #ifdef BSP_USING_UART1
  818. uart_obj[UART1_INDEX].uart_dma_flag = 0;
  819. #ifdef BSP_UART1_RX_USING_DMA
  820. uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  821. static struct dma_config uart1_dma_rx = UART1_DMA_RX_CONFIG;
  822. uart_config[UART1_INDEX].dma_rx = &uart1_dma_rx;
  823. #endif
  824. #ifdef BSP_UART1_TX_USING_DMA
  825. uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  826. static struct dma_config uart1_dma_tx = UART1_DMA_TX_CONFIG;
  827. uart_config[UART1_INDEX].dma_tx = &uart1_dma_tx;
  828. #endif
  829. #endif
  830. #ifdef BSP_USING_UART2
  831. uart_obj[UART2_INDEX].uart_dma_flag = 0;
  832. #ifdef BSP_UART2_RX_USING_DMA
  833. uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  834. static struct dma_config uart2_dma_rx = UART2_DMA_RX_CONFIG;
  835. uart_config[UART2_INDEX].dma_rx = &uart2_dma_rx;
  836. #endif
  837. #ifdef BSP_UART2_TX_USING_DMA
  838. uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  839. static struct dma_config uart2_dma_tx = UART2_DMA_TX_CONFIG;
  840. uart_config[UART2_INDEX].dma_tx = &uart2_dma_tx;
  841. #endif
  842. #endif
  843. #ifdef BSP_USING_UART3
  844. uart_obj[UART3_INDEX].uart_dma_flag = 0;
  845. #ifdef BSP_UART3_RX_USING_DMA
  846. uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  847. static struct dma_config uart3_dma_rx = UART3_DMA_RX_CONFIG;
  848. uart_config[UART3_INDEX].dma_rx = &uart3_dma_rx;
  849. #endif
  850. #ifdef BSP_UART3_TX_USING_DMA
  851. uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  852. static struct dma_config uart3_dma_tx = UART3_DMA_TX_CONFIG;
  853. uart_config[UART3_INDEX].dma_tx = &uart3_dma_tx;
  854. #endif
  855. #endif
  856. #ifdef BSP_USING_UART4
  857. uart_obj[UART4_INDEX].uart_dma_flag = 0;
  858. #ifdef BSP_UART4_RX_USING_DMA
  859. uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  860. static struct dma_config uart4_dma_rx = UART4_DMA_RX_CONFIG;
  861. uart_config[UART4_INDEX].dma_rx = &uart4_dma_rx;
  862. #endif
  863. #ifdef BSP_UART4_TX_USING_DMA
  864. uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  865. static struct dma_config uart4_dma_tx = UART4_DMA_TX_CONFIG;
  866. uart_config[UART4_INDEX].dma_tx = &uart4_dma_tx;
  867. #endif
  868. #endif
  869. #ifdef BSP_USING_UART5
  870. uart_obj[UART5_INDEX].uart_dma_flag = 0;
  871. #ifdef BSP_UART5_RX_USING_DMA
  872. uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  873. static struct dma_config uart5_dma_rx = UART5_DMA_RX_CONFIG;
  874. uart_config[UART5_INDEX].dma_rx = &uart5_dma_rx;
  875. #endif
  876. #ifdef BSP_UART5_TX_USING_DMA
  877. uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  878. static struct dma_config uart5_dma_tx = UART5_DMA_TX_CONFIG;
  879. uart_config[UART5_INDEX].dma_tx = &uart5_dma_tx;
  880. #endif
  881. #endif
  882. #ifdef BSP_USING_UART6
  883. uart_obj[UART6_INDEX].uart_dma_flag = 0;
  884. #ifdef BSP_UART6_RX_USING_DMA
  885. uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  886. static struct dma_config uart6_dma_rx = UART6_DMA_RX_CONFIG;
  887. uart_config[UART6_INDEX].dma_rx = &uart6_dma_rx;
  888. #endif
  889. #ifdef BSP_UART6_TX_USING_DMA
  890. uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  891. static struct dma_config uart6_dma_tx = UART6_DMA_TX_CONFIG;
  892. uart_config[UART6_INDEX].dma_tx = &uart6_dma_tx;
  893. #endif
  894. #endif
  895. #ifdef BSP_USING_UART7
  896. uart_obj[UART7_INDEX].uart_dma_flag = 0;
  897. #ifdef BSP_UART7_RX_USING_DMA
  898. uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  899. static struct dma_config uart7_dma_rx = UART7_DMA_RX_CONFIG;
  900. uart_config[UART7_INDEX].dma_rx = &uart7_dma_rx;
  901. #endif
  902. #ifdef BSP_UART7_TX_USING_DMA
  903. uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  904. static struct dma_config uart7_dma_tx = UART7_DMA_TX_CONFIG;
  905. uart_config[UART7_INDEX].dma_tx = &uart7_dma_tx;
  906. #endif
  907. #endif
  908. #ifdef BSP_USING_UART8
  909. uart_obj[UART8_INDEX].uart_dma_flag = 0;
  910. #ifdef BSP_UART8_RX_USING_DMA
  911. uart_obj[UART8_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  912. static struct dma_config uart8_dma_rx = UART8_DMA_RX_CONFIG;
  913. uart_config[UART8_INDEX].dma_rx = &uart8_dma_rx;
  914. #endif
  915. #ifdef BSP_UART8_TX_USING_DMA
  916. uart_obj[UART8_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  917. static struct dma_config uart8_dma_tx = UART8_DMA_TX_CONFIG;
  918. uart_config[UART8_INDEX].dma_tx = &uart8_dma_tx;
  919. #endif
  920. #endif
  921. #ifdef BSP_USING_LPUART1
  922. uart_obj[LPUART1_INDEX].uart_dma_flag = 0;
  923. #ifdef BSP_LPUART1_RX_USING_DMA
  924. uart_obj[LPUART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  925. static struct dma_config lpuart1_dma_rx = LPUART1_DMA_CONFIG;
  926. uart_config[LPUART1_INDEX].dma_rx = &lpuart1_dma_rx;
  927. #endif
  928. #endif
  929. }
  930. #ifdef RT_SERIAL_USING_DMA
  931. static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
  932. {
  933. struct rt_serial_rx_fifo *rx_fifo;
  934. DMA_HandleTypeDef *DMA_Handle;
  935. struct dma_config *dma_config;
  936. struct stm32_uart *uart;
  937. RT_ASSERT(serial != RT_NULL);
  938. RT_ASSERT(flag == RT_DEVICE_FLAG_DMA_TX || flag == RT_DEVICE_FLAG_DMA_RX);
  939. uart = rt_container_of(serial, struct stm32_uart, serial);
  940. if (RT_DEVICE_FLAG_DMA_RX == flag)
  941. {
  942. DMA_Handle = &uart->dma_rx.handle;
  943. dma_config = uart->config->dma_rx;
  944. }
  945. else /* RT_DEVICE_FLAG_DMA_TX == flag */
  946. {
  947. DMA_Handle = &uart->dma_tx.handle;
  948. dma_config = uart->config->dma_tx;
  949. }
  950. LOG_D("%s dma config start", uart->config->name);
  951. {
  952. rt_uint32_t tmpreg = 0x00U;
  953. #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) \
  954. || defined(SOC_SERIES_STM32L0)|| defined(SOC_SERIES_STM32F3) || defined(SOC_SERIES_STM32L1)
  955. /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
  956. SET_BIT(RCC->AHBENR, dma_config->dma_rcc);
  957. tmpreg = READ_BIT(RCC->AHBENR, dma_config->dma_rcc);
  958. #elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) \
  959. || defined(SOC_SERIES_STM32G4)|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32WB)
  960. /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
  961. SET_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
  962. tmpreg = READ_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
  963. #elif defined(SOC_SERIES_STM32MP1)
  964. /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
  965. SET_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc);
  966. tmpreg = READ_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc);
  967. #endif
  968. #if (defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)) && defined(DMAMUX1)
  969. /* enable DMAMUX clock for L4+ and G4 */
  970. __HAL_RCC_DMAMUX1_CLK_ENABLE();
  971. #elif defined(SOC_SERIES_STM32MP1)
  972. __HAL_RCC_DMAMUX_CLK_ENABLE();
  973. #endif
  974. UNUSED(tmpreg); /* To avoid compiler warnings */
  975. }
  976. if (RT_DEVICE_FLAG_DMA_RX == flag)
  977. {
  978. __HAL_LINKDMA(&(uart->handle), hdmarx, uart->dma_rx.handle);
  979. }
  980. else if (RT_DEVICE_FLAG_DMA_TX == flag)
  981. {
  982. __HAL_LINKDMA(&(uart->handle), hdmatx, uart->dma_tx.handle);
  983. }
  984. #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32L0)|| defined(SOC_SERIES_STM32F3) || defined(SOC_SERIES_STM32L1) || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5)
  985. DMA_Handle->Instance = dma_config->Instance;
  986. #elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
  987. DMA_Handle->Instance = dma_config->Instance;
  988. DMA_Handle->Init.Channel = dma_config->channel;
  989. #elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)\
  990. || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
  991. DMA_Handle->Instance = dma_config->Instance;
  992. DMA_Handle->Init.Request = dma_config->request;
  993. #endif
  994. DMA_Handle->Init.PeriphInc = DMA_PINC_DISABLE;
  995. DMA_Handle->Init.MemInc = DMA_MINC_ENABLE;
  996. DMA_Handle->Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
  997. DMA_Handle->Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
  998. if (RT_DEVICE_FLAG_DMA_RX == flag)
  999. {
  1000. DMA_Handle->Init.Direction = DMA_PERIPH_TO_MEMORY;
  1001. DMA_Handle->Init.Mode = DMA_CIRCULAR;
  1002. }
  1003. else if (RT_DEVICE_FLAG_DMA_TX == flag)
  1004. {
  1005. DMA_Handle->Init.Direction = DMA_MEMORY_TO_PERIPH;
  1006. DMA_Handle->Init.Mode = DMA_NORMAL;
  1007. }
  1008. DMA_Handle->Init.Priority = DMA_PRIORITY_MEDIUM;
  1009. #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
  1010. DMA_Handle->Init.FIFOMode = DMA_FIFOMODE_DISABLE;
  1011. #endif
  1012. if (HAL_DMA_DeInit(DMA_Handle) != HAL_OK)
  1013. {
  1014. RT_ASSERT(0);
  1015. }
  1016. if (HAL_DMA_Init(DMA_Handle) != HAL_OK)
  1017. {
  1018. RT_ASSERT(0);
  1019. }
  1020. /* enable interrupt */
  1021. if (flag == RT_DEVICE_FLAG_DMA_RX)
  1022. {
  1023. rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
  1024. /* Start DMA transfer */
  1025. if (HAL_UART_Receive_DMA(&(uart->handle), rx_fifo->buffer, serial->config.bufsz) != HAL_OK)
  1026. {
  1027. /* Transfer error in reception process */
  1028. RT_ASSERT(0);
  1029. }
  1030. CLEAR_BIT(uart->handle.Instance->CR3, USART_CR3_EIE);
  1031. __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_IDLE);
  1032. }
  1033. /* DMA irq should set in DMA TX mode, or HAL_UART_TxCpltCallback function will not be called */
  1034. HAL_NVIC_SetPriority(dma_config->dma_irq, 0, 0);
  1035. HAL_NVIC_EnableIRQ(dma_config->dma_irq);
  1036. HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0);
  1037. HAL_NVIC_EnableIRQ(uart->config->irq_type);
  1038. LOG_D("%s dma %s instance: %x", uart->config->name, flag == RT_DEVICE_FLAG_DMA_RX ? "RX" : "TX", DMA_Handle->Instance);
  1039. LOG_D("%s dma config done", uart->config->name);
  1040. }
  1041. /**
  1042. * @brief UART error callbacks
  1043. * @param huart: UART handle
  1044. * @note This example shows a simple way to report transfer error, and you can
  1045. * add your own implementation.
  1046. * @retval None
  1047. */
  1048. void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
  1049. {
  1050. RT_ASSERT(huart != NULL);
  1051. struct stm32_uart *uart = (struct stm32_uart *)huart;
  1052. LOG_D("%s: %s %d\n", __FUNCTION__, uart->config->name, huart->ErrorCode);
  1053. UNUSED(uart);
  1054. }
  1055. /**
  1056. * @brief Rx Transfer completed callback
  1057. * @param huart: UART handle
  1058. * @note This example shows a simple way to report end of DMA Rx transfer, and
  1059. * you can add your own implementation.
  1060. * @retval None
  1061. */
  1062. void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
  1063. {
  1064. struct stm32_uart *uart;
  1065. RT_ASSERT(huart != NULL);
  1066. uart = (struct stm32_uart *)huart;
  1067. dma_recv_isr(&uart->serial, UART_RX_DMA_IT_TC_FLAG);
  1068. }
  1069. /**
  1070. * @brief Rx Half transfer completed callback
  1071. * @param huart: UART handle
  1072. * @note This example shows a simple way to report end of DMA Rx Half transfer,
  1073. * and you can add your own implementation.
  1074. * @retval None
  1075. */
  1076. void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
  1077. {
  1078. struct stm32_uart *uart;
  1079. RT_ASSERT(huart != NULL);
  1080. uart = (struct stm32_uart *)huart;
  1081. dma_recv_isr(&uart->serial, UART_RX_DMA_IT_HT_FLAG);
  1082. }
  1083. static void _dma_tx_complete(struct rt_serial_device *serial)
  1084. {
  1085. struct stm32_uart *uart;
  1086. rt_size_t trans_total_index;
  1087. rt_base_t level;
  1088. RT_ASSERT(serial != RT_NULL);
  1089. uart = rt_container_of(serial, struct stm32_uart, serial);
  1090. level = rt_hw_interrupt_disable();
  1091. trans_total_index = __HAL_DMA_GET_COUNTER(&(uart->dma_tx.handle));
  1092. rt_hw_interrupt_enable(level);
  1093. if (trans_total_index == 0)
  1094. {
  1095. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DMADONE);
  1096. }
  1097. }
  1098. /**
  1099. * @brief HAL_UART_TxCpltCallback
  1100. * @param huart: UART handle
  1101. * @note This callback can be called by two functions, first in UART_EndTransmit_IT when
  1102. * UART Tx complete and second in UART_DMATransmitCplt function in DMA Circular mode.
  1103. * @retval None
  1104. */
  1105. void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
  1106. {
  1107. struct stm32_uart *uart;
  1108. RT_ASSERT(huart != NULL);
  1109. uart = (struct stm32_uart *)huart;
  1110. _dma_tx_complete(&uart->serial);
  1111. }
  1112. #endif /* RT_SERIAL_USING_DMA */
  1113. static const struct rt_uart_ops stm32_uart_ops =
  1114. {
  1115. .configure = stm32_configure,
  1116. .control = stm32_control,
  1117. .putc = stm32_putc,
  1118. .getc = stm32_getc,
  1119. .dma_transmit = stm32_dma_transmit
  1120. };
  1121. int rt_hw_usart_init(void)
  1122. {
  1123. struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
  1124. rt_err_t result = 0;
  1125. stm32_uart_get_dma_config();
  1126. for (rt_size_t i = 0; i < sizeof(uart_obj) / sizeof(struct stm32_uart); i++)
  1127. {
  1128. /* init UART object */
  1129. uart_obj[i].config = &uart_config[i];
  1130. uart_obj[i].serial.ops = &stm32_uart_ops;
  1131. uart_obj[i].serial.config = config;
  1132. /* register UART device */
  1133. result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name,
  1134. RT_DEVICE_FLAG_RDWR
  1135. | RT_DEVICE_FLAG_INT_RX
  1136. | RT_DEVICE_FLAG_INT_TX
  1137. | uart_obj[i].uart_dma_flag
  1138. , NULL);
  1139. RT_ASSERT(result == RT_EOK);
  1140. }
  1141. return result;
  1142. }
  1143. #endif /* RT_USING_SERIAL */