drv_spi.c 5.8 KB

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  1. /*
  2. * Copyright (c) 2006-2024 RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2024-08-1 hywing The first version for MCXA
  9. */
  10. #include "rtdevice.h"
  11. #include "drv_spi.h"
  12. #include "fsl_lpspi.h"
  13. #include "fsl_lpspi_edma.h"
  14. #define DMA_MAX_TRANSFER_SIZE (32767)
  15. enum
  16. {
  17. #ifdef BSP_USING_SPI0
  18. SPI0_INDEX
  19. #endif
  20. };
  21. struct lpc_spi
  22. {
  23. struct rt_spi_bus parent;
  24. LPSPI_Type *LPSPIx;
  25. clock_attach_id_t clock_attach_id;
  26. clock_div_name_t clock_div_name;
  27. clock_name_t clock_name;
  28. DMA_Type *DMAx;
  29. uint8_t tx_dma_chl;
  30. uint8_t rx_dma_chl;
  31. edma_handle_t dma_tx_handle;
  32. edma_handle_t dma_rx_handle;
  33. dma_request_source_t tx_dma_request;
  34. dma_request_source_t rx_dma_request;
  35. lpspi_master_edma_handle_t spi_dma_handle;
  36. rt_sem_t sem;
  37. char *name;
  38. };
  39. static struct lpc_spi lpc_obj[] =
  40. {
  41. #ifdef BSP_USING_SPI0
  42. {
  43. .LPSPIx = LPSPI0,
  44. .clock_attach_id = kFRO12M_to_LPSPI0,
  45. .clock_div_name = kCLOCK_DivLPSPI0,
  46. .clock_name = kCLOCK_Fro12M,
  47. .tx_dma_request = kDma0RequestLPSPI0Tx,
  48. .rx_dma_request = kDma0RequestLPSPI0Rx,
  49. .DMAx = DMA0,
  50. .tx_dma_chl = 0,
  51. .rx_dma_chl = 1,
  52. .name = "spi0",
  53. },
  54. #endif
  55. };
  56. struct lpc_sw_spi_cs
  57. {
  58. rt_uint32_t pin;
  59. };
  60. rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_uint32_t pin)
  61. {
  62. rt_err_t ret = RT_EOK;
  63. struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
  64. struct lpc_sw_spi_cs *cs_pin = (struct lpc_sw_spi_cs *)rt_malloc(sizeof(struct lpc_sw_spi_cs));
  65. cs_pin->pin = pin;
  66. rt_pin_mode(pin, PIN_MODE_OUTPUT);
  67. rt_pin_write(pin, PIN_HIGH);
  68. ret = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
  69. return ret;
  70. }
  71. static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg)
  72. {
  73. return RT_EOK;
  74. }
  75. static void LPSPI_MasterUserCallback(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, status_t status, void *userData)
  76. {
  77. struct lpc_spi *spi = (struct lpc_spi *)userData;
  78. rt_sem_release(spi->sem);
  79. }
  80. static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
  81. {
  82. int i;
  83. lpspi_transfer_t transfer = {0};
  84. RT_ASSERT(device != RT_NULL);
  85. RT_ASSERT(device->bus != RT_NULL);
  86. RT_ASSERT(device->bus->parent.user_data != RT_NULL);
  87. struct lpc_spi *spi = (struct lpc_spi *)(device->bus->parent.user_data);
  88. struct lpc_sw_spi_cs *cs = device->parent.user_data;
  89. if (message->cs_take)
  90. {
  91. rt_pin_write(cs->pin, PIN_LOW);
  92. }
  93. transfer.dataSize = message->length;
  94. transfer.rxData = (uint8_t *)(message->recv_buf);
  95. transfer.txData = (uint8_t *)(message->send_buf);
  96. /* if(message->length < MAX_DMA_TRANSFER_SIZE)*/
  97. uint32_t block, remain;
  98. block = message->length / DMA_MAX_TRANSFER_SIZE;
  99. remain = message->length % DMA_MAX_TRANSFER_SIZE;
  100. for (i = 0; i < block; i++)
  101. {
  102. transfer.dataSize = DMA_MAX_TRANSFER_SIZE;
  103. if (message->recv_buf) transfer.rxData = (uint8_t *)(message->recv_buf + i * DMA_MAX_TRANSFER_SIZE);
  104. if (message->send_buf) transfer.txData = (uint8_t *)(message->send_buf + i * DMA_MAX_TRANSFER_SIZE);
  105. LPSPI_MasterTransferEDMA(spi->LPSPIx, &spi->spi_dma_handle, &transfer);
  106. rt_sem_take(spi->sem, RT_WAITING_FOREVER);
  107. }
  108. if (remain)
  109. {
  110. transfer.dataSize = remain;
  111. if (message->recv_buf) transfer.rxData = (uint8_t *)(message->recv_buf + i * DMA_MAX_TRANSFER_SIZE);
  112. if (message->send_buf) transfer.txData = (uint8_t *)(message->send_buf + i * DMA_MAX_TRANSFER_SIZE);
  113. LPSPI_MasterTransferEDMA(spi->LPSPIx, &spi->spi_dma_handle, &transfer);
  114. rt_sem_take(spi->sem, RT_WAITING_FOREVER);
  115. }
  116. if (message->cs_release)
  117. {
  118. rt_pin_write(cs->pin, PIN_HIGH);
  119. }
  120. return message->length;
  121. }
  122. static struct rt_spi_ops lpc_spi_ops =
  123. {
  124. .configure = spi_configure,
  125. .xfer = spixfer
  126. };
  127. int rt_hw_spi_init(void)
  128. {
  129. int i;
  130. for (i = 0; i < ARRAY_SIZE(lpc_obj); i++)
  131. {
  132. CLOCK_SetClockDiv(lpc_obj[i].clock_div_name, 1u);
  133. CLOCK_AttachClk(lpc_obj[i].clock_attach_id);
  134. lpc_obj[i].parent.parent.user_data = &lpc_obj[i];
  135. lpc_obj[i].sem = rt_sem_create("sem_spi", 0, RT_IPC_FLAG_FIFO);
  136. lpspi_master_config_t masterConfig;
  137. LPSPI_MasterGetDefaultConfig(&masterConfig);
  138. masterConfig.baudRate = 1 * 1000 * 1000;
  139. masterConfig.pcsToSckDelayInNanoSec = 1000000000U / masterConfig.baudRate * 1U;
  140. masterConfig.lastSckToPcsDelayInNanoSec = 1000000000U / masterConfig.baudRate * 1U;
  141. masterConfig.betweenTransferDelayInNanoSec = 1000000000U / masterConfig.baudRate * 1U;
  142. LPSPI_MasterInit(lpc_obj[i].LPSPIx, &masterConfig, CLOCK_GetFreq(lpc_obj[i].clock_name));
  143. EDMA_CreateHandle(&lpc_obj[i].dma_tx_handle, lpc_obj[i].DMAx, lpc_obj[i].tx_dma_chl);
  144. EDMA_CreateHandle(&lpc_obj[i].dma_rx_handle, lpc_obj[i].DMAx, lpc_obj[i].rx_dma_chl);
  145. EDMA_SetChannelMux(lpc_obj[i].DMAx, lpc_obj[i].tx_dma_chl, lpc_obj[i].tx_dma_request);
  146. EDMA_SetChannelMux(lpc_obj[i].DMAx, lpc_obj[i].rx_dma_chl, lpc_obj[i].rx_dma_request);
  147. LPSPI_MasterTransferCreateHandleEDMA(lpc_obj[i].LPSPIx, &lpc_obj[i].spi_dma_handle, LPSPI_MasterUserCallback, &lpc_obj[i], &lpc_obj[i].dma_rx_handle, &lpc_obj[i].dma_tx_handle);
  148. rt_spi_bus_register(&lpc_obj[i].parent, lpc_obj[i].name, &lpc_spi_ops);
  149. }
  150. return RT_EOK;
  151. }
  152. INIT_DEVICE_EXPORT(rt_hw_spi_init);