drv_usart.c 32 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-10-30 SummerGift first version
  9. * 2020-03-16 SummerGift add device close feature
  10. * 2020-03-20 SummerGift fix bug caused by ORE
  11. * 2020-05-02 whj4674672 support stm32h7 uart dma
  12. * 2020-09-09 forest-rain support stm32wl uart
  13. * 2020-10-14 Dozingfiretruck Porting for stm32wbxx
  14. */
  15. #include "board.h"
  16. #include "drv_usart.h"
  17. #include "drv_config.h"
  18. #ifdef RT_USING_SERIAL
  19. //#define DRV_DEBUG
  20. #define LOG_TAG "drv.usart"
  21. #include <drv_log.h>
  22. #if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && \
  23. !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && \
  24. !defined(BSP_USING_UART7) && !defined(BSP_USING_UART8) && !defined(BSP_USING_LPUART1)
  25. #error "Please define at least one BSP_USING_UARTx"
  26. /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
  27. #endif
  28. #ifdef RT_SERIAL_USING_DMA
  29. static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag);
  30. #endif
  31. enum
  32. {
  33. #ifdef BSP_USING_UART1
  34. UART1_INDEX,
  35. #endif
  36. #ifdef BSP_USING_UART2
  37. UART2_INDEX,
  38. #endif
  39. #ifdef BSP_USING_UART3
  40. UART3_INDEX,
  41. #endif
  42. #ifdef BSP_USING_UART4
  43. UART4_INDEX,
  44. #endif
  45. #ifdef BSP_USING_UART5
  46. UART5_INDEX,
  47. #endif
  48. #ifdef BSP_USING_UART6
  49. UART6_INDEX,
  50. #endif
  51. #ifdef BSP_USING_UART7
  52. UART7_INDEX,
  53. #endif
  54. #ifdef BSP_USING_UART8
  55. UART8_INDEX,
  56. #endif
  57. #ifdef BSP_USING_LPUART1
  58. LPUART1_INDEX,
  59. #endif
  60. };
  61. static struct stm32_uart_config uart_config[] =
  62. {
  63. #ifdef BSP_USING_UART1
  64. UART1_CONFIG,
  65. #endif
  66. #ifdef BSP_USING_UART2
  67. UART2_CONFIG,
  68. #endif
  69. #ifdef BSP_USING_UART3
  70. UART3_CONFIG,
  71. #endif
  72. #ifdef BSP_USING_UART4
  73. UART4_CONFIG,
  74. #endif
  75. #ifdef BSP_USING_UART5
  76. UART5_CONFIG,
  77. #endif
  78. #ifdef BSP_USING_UART6
  79. UART6_CONFIG,
  80. #endif
  81. #ifdef BSP_USING_UART7
  82. UART7_CONFIG,
  83. #endif
  84. #ifdef BSP_USING_UART8
  85. UART8_CONFIG,
  86. #endif
  87. #ifdef BSP_USING_LPUART1
  88. LPUART1_CONFIG,
  89. #endif
  90. };
  91. static struct stm32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
  92. static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
  93. {
  94. struct stm32_uart *uart;
  95. RT_ASSERT(serial != RT_NULL);
  96. RT_ASSERT(cfg != RT_NULL);
  97. uart = rt_container_of(serial, struct stm32_uart, serial);
  98. uart->handle.Instance = uart->config->Instance;
  99. uart->handle.Init.BaudRate = cfg->baud_rate;
  100. uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
  101. uart->handle.Init.Mode = UART_MODE_TX_RX;
  102. uart->handle.Init.OverSampling = UART_OVERSAMPLING_16;
  103. switch (cfg->data_bits)
  104. {
  105. case DATA_BITS_8:
  106. if (cfg->parity == PARITY_ODD || cfg->parity == PARITY_EVEN)
  107. uart->handle.Init.WordLength = UART_WORDLENGTH_9B;
  108. else
  109. uart->handle.Init.WordLength = UART_WORDLENGTH_8B;
  110. break;
  111. case DATA_BITS_9:
  112. uart->handle.Init.WordLength = UART_WORDLENGTH_9B;
  113. break;
  114. default:
  115. uart->handle.Init.WordLength = UART_WORDLENGTH_8B;
  116. break;
  117. }
  118. switch (cfg->stop_bits)
  119. {
  120. case STOP_BITS_1:
  121. uart->handle.Init.StopBits = UART_STOPBITS_1;
  122. break;
  123. case STOP_BITS_2:
  124. uart->handle.Init.StopBits = UART_STOPBITS_2;
  125. break;
  126. default:
  127. uart->handle.Init.StopBits = UART_STOPBITS_1;
  128. break;
  129. }
  130. switch (cfg->parity)
  131. {
  132. case PARITY_NONE:
  133. uart->handle.Init.Parity = UART_PARITY_NONE;
  134. break;
  135. case PARITY_ODD:
  136. uart->handle.Init.Parity = UART_PARITY_ODD;
  137. break;
  138. case PARITY_EVEN:
  139. uart->handle.Init.Parity = UART_PARITY_EVEN;
  140. break;
  141. default:
  142. uart->handle.Init.Parity = UART_PARITY_NONE;
  143. break;
  144. }
  145. #ifdef RT_SERIAL_USING_DMA
  146. uart->dma_rx.last_index = 0;
  147. #endif
  148. if (HAL_UART_Init(&uart->handle) != HAL_OK)
  149. {
  150. return -RT_ERROR;
  151. }
  152. return RT_EOK;
  153. }
  154. static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *arg)
  155. {
  156. struct stm32_uart *uart;
  157. #ifdef RT_SERIAL_USING_DMA
  158. rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
  159. #endif
  160. RT_ASSERT(serial != RT_NULL);
  161. uart = rt_container_of(serial, struct stm32_uart, serial);
  162. switch (cmd)
  163. {
  164. /* disable interrupt */
  165. case RT_DEVICE_CTRL_CLR_INT:
  166. /* disable rx irq */
  167. NVIC_DisableIRQ(uart->config->irq_type);
  168. /* disable interrupt */
  169. __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_RXNE);
  170. #ifdef RT_SERIAL_USING_DMA
  171. /* disable DMA */
  172. if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX)
  173. {
  174. HAL_NVIC_DisableIRQ(uart->config->dma_rx->dma_irq);
  175. if (HAL_DMA_Abort(&(uart->dma_rx.handle)) != HAL_OK)
  176. {
  177. RT_ASSERT(0);
  178. }
  179. if (HAL_DMA_DeInit(&(uart->dma_rx.handle)) != HAL_OK)
  180. {
  181. RT_ASSERT(0);
  182. }
  183. }
  184. else if(ctrl_arg == RT_DEVICE_FLAG_DMA_TX)
  185. {
  186. HAL_NVIC_DisableIRQ(uart->config->dma_tx->dma_irq);
  187. if (HAL_DMA_DeInit(&(uart->dma_tx.handle)) != HAL_OK)
  188. {
  189. RT_ASSERT(0);
  190. }
  191. }
  192. #endif
  193. break;
  194. /* enable interrupt */
  195. case RT_DEVICE_CTRL_SET_INT:
  196. /* enable rx irq */
  197. HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0);
  198. HAL_NVIC_EnableIRQ(uart->config->irq_type);
  199. /* enable interrupt */
  200. __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_RXNE);
  201. break;
  202. #ifdef RT_SERIAL_USING_DMA
  203. case RT_DEVICE_CTRL_CONFIG:
  204. stm32_dma_config(serial, ctrl_arg);
  205. break;
  206. #endif
  207. case RT_DEVICE_CTRL_CLOSE:
  208. if (HAL_UART_DeInit(&(uart->handle)) != HAL_OK )
  209. {
  210. RT_ASSERT(0)
  211. }
  212. break;
  213. }
  214. return RT_EOK;
  215. }
  216. static int stm32_putc(struct rt_serial_device *serial, char c)
  217. {
  218. struct stm32_uart *uart;
  219. RT_ASSERT(serial != RT_NULL);
  220. uart = rt_container_of(serial, struct stm32_uart, serial);
  221. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
  222. #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
  223. || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) \
  224. || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32F3)
  225. uart->handle.Instance->TDR = c;
  226. #else
  227. uart->handle.Instance->DR = c;
  228. #endif
  229. while (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) == RESET);
  230. return 1;
  231. }
  232. static int stm32_getc(struct rt_serial_device *serial)
  233. {
  234. int ch;
  235. struct stm32_uart *uart;
  236. RT_ASSERT(serial != RT_NULL);
  237. uart = rt_container_of(serial, struct stm32_uart, serial);
  238. ch = -1;
  239. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET)
  240. {
  241. #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
  242. || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) \
  243. || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3)
  244. ch = uart->handle.Instance->RDR & 0xff;
  245. #else
  246. ch = uart->handle.Instance->DR & 0xff;
  247. #endif
  248. }
  249. return ch;
  250. }
  251. static rt_size_t stm32_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
  252. {
  253. struct stm32_uart *uart;
  254. RT_ASSERT(serial != RT_NULL);
  255. RT_ASSERT(buf != RT_NULL);
  256. uart = rt_container_of(serial, struct stm32_uart, serial);
  257. if (size == 0)
  258. {
  259. return 0;
  260. }
  261. if (RT_SERIAL_DMA_TX == direction)
  262. {
  263. if (HAL_UART_Transmit_DMA(&uart->handle, buf, size) == HAL_OK)
  264. {
  265. return size;
  266. }
  267. else
  268. {
  269. return 0;
  270. }
  271. }
  272. return 0;
  273. }
  274. /**
  275. * Uart common interrupt process. This need add to uart ISR.
  276. *
  277. * @param serial serial device
  278. */
  279. static void uart_isr(struct rt_serial_device *serial)
  280. {
  281. struct stm32_uart *uart;
  282. #ifdef RT_SERIAL_USING_DMA
  283. rt_size_t recv_total_index, recv_len;
  284. rt_base_t level;
  285. #endif
  286. RT_ASSERT(serial != RT_NULL);
  287. uart = rt_container_of(serial, struct stm32_uart, serial);
  288. /* UART in mode Receiver -------------------------------------------------*/
  289. if ((__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET) &&
  290. (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_RXNE) != RESET))
  291. {
  292. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
  293. }
  294. #ifdef RT_SERIAL_USING_DMA
  295. else if ((uart->uart_dma_flag) && (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_IDLE) != RESET)
  296. && (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_IDLE) != RESET))
  297. {
  298. level = rt_hw_interrupt_disable();
  299. recv_total_index = serial->config.bufsz - __HAL_DMA_GET_COUNTER(&(uart->dma_rx.handle));
  300. recv_len = recv_total_index - uart->dma_rx.last_index;
  301. uart->dma_rx.last_index = recv_total_index;
  302. rt_hw_interrupt_enable(level);
  303. if (recv_len)
  304. {
  305. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
  306. }
  307. __HAL_UART_CLEAR_IDLEFLAG(&uart->handle);
  308. }
  309. else if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) &&
  310. (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_TC) != RESET))
  311. {
  312. if ((serial->parent.open_flag & RT_DEVICE_FLAG_DMA_TX) != 0)
  313. {
  314. HAL_UART_IRQHandler(&(uart->handle));
  315. }
  316. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
  317. }
  318. #endif
  319. else
  320. {
  321. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_ORE) != RESET)
  322. {
  323. __HAL_UART_CLEAR_OREFLAG(&uart->handle);
  324. }
  325. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_NE) != RESET)
  326. {
  327. __HAL_UART_CLEAR_NEFLAG(&uart->handle);
  328. }
  329. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_FE) != RESET)
  330. {
  331. __HAL_UART_CLEAR_FEFLAG(&uart->handle);
  332. }
  333. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_PE) != RESET)
  334. {
  335. __HAL_UART_CLEAR_PEFLAG(&uart->handle);
  336. }
  337. #if !defined(SOC_SERIES_STM32L4) && !defined(SOC_SERIES_STM32WL) && !defined(SOC_SERIES_STM32F7) && !defined(SOC_SERIES_STM32F0) \
  338. && !defined(SOC_SERIES_STM32L0) && !defined(SOC_SERIES_STM32G0) && !defined(SOC_SERIES_STM32H7) \
  339. && !defined(SOC_SERIES_STM32G4) && !defined(SOC_SERIES_STM32MP1) && !defined(SOC_SERIES_STM32WB)
  340. #ifdef SOC_SERIES_STM32F3
  341. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBDF) != RESET)
  342. {
  343. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_LBDF);
  344. }
  345. #else
  346. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBD) != RESET)
  347. {
  348. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_LBD);
  349. }
  350. #endif
  351. #endif
  352. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_CTS) != RESET)
  353. {
  354. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_CTS);
  355. }
  356. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TXE) != RESET)
  357. {
  358. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TXE);
  359. }
  360. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) != RESET)
  361. {
  362. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
  363. }
  364. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET)
  365. {
  366. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_RXNE);
  367. }
  368. }
  369. }
  370. #ifdef RT_SERIAL_USING_DMA
  371. static void dma_isr(struct rt_serial_device *serial)
  372. {
  373. struct stm32_uart *uart;
  374. rt_size_t recv_total_index, recv_len;
  375. rt_base_t level;
  376. RT_ASSERT(serial != RT_NULL);
  377. uart = rt_container_of(serial, struct stm32_uart, serial);
  378. if ((__HAL_DMA_GET_IT_SOURCE(&(uart->dma_rx.handle), DMA_IT_TC) != RESET) ||
  379. (__HAL_DMA_GET_IT_SOURCE(&(uart->dma_rx.handle), DMA_IT_HT) != RESET))
  380. {
  381. level = rt_hw_interrupt_disable();
  382. recv_total_index = serial->config.bufsz - __HAL_DMA_GET_COUNTER(&(uart->dma_rx.handle));
  383. if (recv_total_index == 0)
  384. {
  385. recv_len = serial->config.bufsz - uart->dma_rx.last_index;
  386. }
  387. else
  388. {
  389. recv_len = recv_total_index - uart->dma_rx.last_index;
  390. }
  391. uart->dma_rx.last_index = recv_total_index;
  392. rt_hw_interrupt_enable(level);
  393. if (recv_len)
  394. {
  395. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
  396. }
  397. }
  398. }
  399. #endif
  400. #if defined(BSP_USING_UART1)
  401. void USART1_IRQHandler(void)
  402. {
  403. /* enter interrupt */
  404. rt_interrupt_enter();
  405. uart_isr(&(uart_obj[UART1_INDEX].serial));
  406. /* leave interrupt */
  407. rt_interrupt_leave();
  408. }
  409. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA)
  410. void UART1_DMA_RX_IRQHandler(void)
  411. {
  412. /* enter interrupt */
  413. rt_interrupt_enter();
  414. HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_rx.handle);
  415. /* leave interrupt */
  416. rt_interrupt_leave();
  417. }
  418. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) */
  419. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA)
  420. void UART1_DMA_TX_IRQHandler(void)
  421. {
  422. /* enter interrupt */
  423. rt_interrupt_enter();
  424. HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_tx.handle);
  425. /* leave interrupt */
  426. rt_interrupt_leave();
  427. }
  428. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA) */
  429. #endif /* BSP_USING_UART1 */
  430. #if defined(BSP_USING_UART2)
  431. void USART2_IRQHandler(void)
  432. {
  433. /* enter interrupt */
  434. rt_interrupt_enter();
  435. uart_isr(&(uart_obj[UART2_INDEX].serial));
  436. /* leave interrupt */
  437. rt_interrupt_leave();
  438. }
  439. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA)
  440. void UART2_DMA_RX_IRQHandler(void)
  441. {
  442. /* enter interrupt */
  443. rt_interrupt_enter();
  444. HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma_rx.handle);
  445. /* leave interrupt */
  446. rt_interrupt_leave();
  447. }
  448. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) */
  449. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA)
  450. void UART2_DMA_TX_IRQHandler(void)
  451. {
  452. /* enter interrupt */
  453. rt_interrupt_enter();
  454. HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma_tx.handle);
  455. /* leave interrupt */
  456. rt_interrupt_leave();
  457. }
  458. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA) */
  459. #endif /* BSP_USING_UART2 */
  460. #if defined(BSP_USING_UART3)
  461. void USART3_IRQHandler(void)
  462. {
  463. /* enter interrupt */
  464. rt_interrupt_enter();
  465. uart_isr(&(uart_obj[UART3_INDEX].serial));
  466. /* leave interrupt */
  467. rt_interrupt_leave();
  468. }
  469. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_RX_USING_DMA)
  470. void UART3_DMA_RX_IRQHandler(void)
  471. {
  472. /* enter interrupt */
  473. rt_interrupt_enter();
  474. HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma_rx.handle);
  475. /* leave interrupt */
  476. rt_interrupt_leave();
  477. }
  478. #endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART3_RX_USING_DMA) */
  479. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_TX_USING_DMA)
  480. void UART3_DMA_TX_IRQHandler(void)
  481. {
  482. /* enter interrupt */
  483. rt_interrupt_enter();
  484. HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma_tx.handle);
  485. /* leave interrupt */
  486. rt_interrupt_leave();
  487. }
  488. #endif /* defined(BSP_UART_USING_DMA_TX) && defined(BSP_UART3_TX_USING_DMA) */
  489. #endif /* BSP_USING_UART3*/
  490. #if defined(BSP_USING_UART4)
  491. void UART4_IRQHandler(void)
  492. {
  493. /* enter interrupt */
  494. rt_interrupt_enter();
  495. uart_isr(&(uart_obj[UART4_INDEX].serial));
  496. /* leave interrupt */
  497. rt_interrupt_leave();
  498. }
  499. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_RX_USING_DMA)
  500. void UART4_DMA_RX_IRQHandler(void)
  501. {
  502. /* enter interrupt */
  503. rt_interrupt_enter();
  504. HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma_rx.handle);
  505. /* leave interrupt */
  506. rt_interrupt_leave();
  507. }
  508. #endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART4_RX_USING_DMA) */
  509. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_TX_USING_DMA)
  510. void UART4_DMA_TX_IRQHandler(void)
  511. {
  512. /* enter interrupt */
  513. rt_interrupt_enter();
  514. HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma_tx.handle);
  515. /* leave interrupt */
  516. rt_interrupt_leave();
  517. }
  518. #endif /* defined(BSP_UART_USING_DMA_TX) && defined(BSP_UART4_TX_USING_DMA) */
  519. #endif /* BSP_USING_UART4*/
  520. #if defined(BSP_USING_UART5)
  521. void UART5_IRQHandler(void)
  522. {
  523. /* enter interrupt */
  524. rt_interrupt_enter();
  525. uart_isr(&(uart_obj[UART5_INDEX].serial));
  526. /* leave interrupt */
  527. rt_interrupt_leave();
  528. }
  529. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA)
  530. void UART5_DMA_RX_IRQHandler(void)
  531. {
  532. /* enter interrupt */
  533. rt_interrupt_enter();
  534. HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma_rx.handle);
  535. /* leave interrupt */
  536. rt_interrupt_leave();
  537. }
  538. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA) */
  539. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA)
  540. void UART5_DMA_TX_IRQHandler(void)
  541. {
  542. /* enter interrupt */
  543. rt_interrupt_enter();
  544. HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma_tx.handle);
  545. /* leave interrupt */
  546. rt_interrupt_leave();
  547. }
  548. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA) */
  549. #endif /* BSP_USING_UART5*/
  550. #if defined(BSP_USING_UART6)
  551. void USART6_IRQHandler(void)
  552. {
  553. /* enter interrupt */
  554. rt_interrupt_enter();
  555. uart_isr(&(uart_obj[UART6_INDEX].serial));
  556. /* leave interrupt */
  557. rt_interrupt_leave();
  558. }
  559. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA)
  560. void UART6_DMA_RX_IRQHandler(void)
  561. {
  562. /* enter interrupt */
  563. rt_interrupt_enter();
  564. HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma_rx.handle);
  565. /* leave interrupt */
  566. rt_interrupt_leave();
  567. }
  568. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA) */
  569. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA)
  570. void UART6_DMA_TX_IRQHandler(void)
  571. {
  572. /* enter interrupt */
  573. rt_interrupt_enter();
  574. HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma_tx.handle);
  575. /* leave interrupt */
  576. rt_interrupt_leave();
  577. }
  578. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA) */
  579. #endif /* BSP_USING_UART6*/
  580. #if defined(BSP_USING_UART7)
  581. void UART7_IRQHandler(void)
  582. {
  583. /* enter interrupt */
  584. rt_interrupt_enter();
  585. uart_isr(&(uart_obj[UART7_INDEX].serial));
  586. /* leave interrupt */
  587. rt_interrupt_leave();
  588. }
  589. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA)
  590. void UART7_DMA_RX_IRQHandler(void)
  591. {
  592. /* enter interrupt */
  593. rt_interrupt_enter();
  594. HAL_DMA_IRQHandler(&uart_obj[UART7_INDEX].dma_rx.handle);
  595. /* leave interrupt */
  596. rt_interrupt_leave();
  597. }
  598. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA) */
  599. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA)
  600. void UART7_DMA_TX_IRQHandler(void)
  601. {
  602. /* enter interrupt */
  603. rt_interrupt_enter();
  604. HAL_DMA_IRQHandler(&uart_obj[UART7_INDEX].dma_tx.handle);
  605. /* leave interrupt */
  606. rt_interrupt_leave();
  607. }
  608. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA) */
  609. #endif /* BSP_USING_UART7*/
  610. #if defined(BSP_USING_UART8)
  611. void UART8_IRQHandler(void)
  612. {
  613. /* enter interrupt */
  614. rt_interrupt_enter();
  615. uart_isr(&(uart_obj[UART8_INDEX].serial));
  616. /* leave interrupt */
  617. rt_interrupt_leave();
  618. }
  619. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA)
  620. void UART8_DMA_RX_IRQHandler(void)
  621. {
  622. /* enter interrupt */
  623. rt_interrupt_enter();
  624. HAL_DMA_IRQHandler(&uart_obj[UART8_INDEX].dma_rx.handle);
  625. /* leave interrupt */
  626. rt_interrupt_leave();
  627. }
  628. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA) */
  629. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA)
  630. void UART8_DMA_TX_IRQHandler(void)
  631. {
  632. /* enter interrupt */
  633. rt_interrupt_enter();
  634. HAL_DMA_IRQHandler(&uart_obj[UART8_INDEX].dma_tx.handle);
  635. /* leave interrupt */
  636. rt_interrupt_leave();
  637. }
  638. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA) */
  639. #endif /* BSP_USING_UART8*/
  640. #if defined(BSP_USING_LPUART1)
  641. void LPUART1_IRQHandler(void)
  642. {
  643. /* enter interrupt */
  644. rt_interrupt_enter();
  645. uart_isr(&(uart_obj[LPUART1_INDEX].serial));
  646. /* leave interrupt */
  647. rt_interrupt_leave();
  648. }
  649. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA)
  650. void LPUART1_DMA_RX_IRQHandler(void)
  651. {
  652. /* enter interrupt */
  653. rt_interrupt_enter();
  654. HAL_DMA_IRQHandler(&uart_obj[LPUART1_INDEX].dma_rx.handle);
  655. /* leave interrupt */
  656. rt_interrupt_leave();
  657. }
  658. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA) */
  659. #endif /* BSP_USING_LPUART1*/
  660. static void stm32_uart_get_dma_config(void)
  661. {
  662. #ifdef BSP_USING_UART1
  663. uart_obj[UART1_INDEX].uart_dma_flag = 0;
  664. #ifdef BSP_UART1_RX_USING_DMA
  665. uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  666. static struct dma_config uart1_dma_rx = UART1_DMA_RX_CONFIG;
  667. uart_config[UART1_INDEX].dma_rx = &uart1_dma_rx;
  668. #endif
  669. #ifdef BSP_UART1_TX_USING_DMA
  670. uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  671. static struct dma_config uart1_dma_tx = UART1_DMA_TX_CONFIG;
  672. uart_config[UART1_INDEX].dma_tx = &uart1_dma_tx;
  673. #endif
  674. #endif
  675. #ifdef BSP_USING_UART2
  676. uart_obj[UART2_INDEX].uart_dma_flag = 0;
  677. #ifdef BSP_UART2_RX_USING_DMA
  678. uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  679. static struct dma_config uart2_dma_rx = UART2_DMA_RX_CONFIG;
  680. uart_config[UART2_INDEX].dma_rx = &uart2_dma_rx;
  681. #endif
  682. #ifdef BSP_UART2_TX_USING_DMA
  683. uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  684. static struct dma_config uart2_dma_tx = UART2_DMA_TX_CONFIG;
  685. uart_config[UART2_INDEX].dma_tx = &uart2_dma_tx;
  686. #endif
  687. #endif
  688. #ifdef BSP_USING_UART3
  689. uart_obj[UART3_INDEX].uart_dma_flag = 0;
  690. #ifdef BSP_UART3_RX_USING_DMA
  691. uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  692. static struct dma_config uart3_dma_rx = UART3_DMA_RX_CONFIG;
  693. uart_config[UART3_INDEX].dma_rx = &uart3_dma_rx;
  694. #endif
  695. #ifdef BSP_UART3_TX_USING_DMA
  696. uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  697. static struct dma_config uart3_dma_tx = UART3_DMA_TX_CONFIG;
  698. uart_config[UART3_INDEX].dma_tx = &uart3_dma_tx;
  699. #endif
  700. #endif
  701. #ifdef BSP_USING_UART4
  702. uart_obj[UART4_INDEX].uart_dma_flag = 0;
  703. #ifdef BSP_UART4_RX_USING_DMA
  704. uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  705. static struct dma_config uart4_dma_rx = UART4_DMA_RX_CONFIG;
  706. uart_config[UART4_INDEX].dma_rx = &uart4_dma_rx;
  707. #endif
  708. #ifdef BSP_UART4_TX_USING_DMA
  709. uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  710. static struct dma_config uart4_dma_tx = UART4_DMA_TX_CONFIG;
  711. uart_config[UART4_INDEX].dma_tx = &uart4_dma_tx;
  712. #endif
  713. #endif
  714. #ifdef BSP_USING_UART5
  715. uart_obj[UART5_INDEX].uart_dma_flag = 0;
  716. #ifdef BSP_UART5_RX_USING_DMA
  717. uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  718. static struct dma_config uart5_dma_rx = UART5_DMA_RX_CONFIG;
  719. uart_config[UART5_INDEX].dma_rx = &uart5_dma_rx;
  720. #endif
  721. #ifdef BSP_UART5_TX_USING_DMA
  722. uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  723. static struct dma_config uart5_dma_tx = UART5_DMA_TX_CONFIG;
  724. uart_config[UART5_INDEX].dma_tx = &uart5_dma_tx;
  725. #endif
  726. #endif
  727. #ifdef BSP_USING_UART6
  728. uart_obj[UART6_INDEX].uart_dma_flag = 0;
  729. #ifdef BSP_UART6_RX_USING_DMA
  730. uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  731. static struct dma_config uart6_dma_rx = UART6_DMA_RX_CONFIG;
  732. uart_config[UART6_INDEX].dma_rx = &uart6_dma_rx;
  733. #endif
  734. #ifdef BSP_UART6_TX_USING_DMA
  735. uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  736. static struct dma_config uart6_dma_tx = UART6_DMA_TX_CONFIG;
  737. uart_config[UART6_INDEX].dma_tx = &uart6_dma_tx;
  738. #endif
  739. #endif
  740. }
  741. #ifdef RT_SERIAL_USING_DMA
  742. static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
  743. {
  744. struct rt_serial_rx_fifo *rx_fifo;
  745. DMA_HandleTypeDef *DMA_Handle;
  746. struct dma_config *dma_config;
  747. struct stm32_uart *uart;
  748. RT_ASSERT(serial != RT_NULL);
  749. uart = rt_container_of(serial, struct stm32_uart, serial);
  750. if (RT_DEVICE_FLAG_DMA_RX == flag)
  751. {
  752. DMA_Handle = &uart->dma_rx.handle;
  753. dma_config = uart->config->dma_rx;
  754. }
  755. else if (RT_DEVICE_FLAG_DMA_TX == flag)
  756. {
  757. DMA_Handle = &uart->dma_tx.handle;
  758. dma_config = uart->config->dma_tx;
  759. }
  760. LOG_D("%s dma config start", uart->config->name);
  761. {
  762. rt_uint32_t tmpreg = 0x00U;
  763. #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) \
  764. || defined(SOC_SERIES_STM32L0)|| defined(SOC_SERIES_STM32F3)
  765. /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
  766. SET_BIT(RCC->AHBENR, dma_config->dma_rcc);
  767. tmpreg = READ_BIT(RCC->AHBENR, dma_config->dma_rcc);
  768. #elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) \
  769. || defined(SOC_SERIES_STM32G4)|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32WB)
  770. /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
  771. SET_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
  772. tmpreg = READ_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
  773. #elif defined(SOC_SERIES_STM32MP1)
  774. /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
  775. SET_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc);
  776. tmpreg = READ_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc);
  777. #endif
  778. #if (defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)) && defined(DMAMUX1)
  779. /* enable DMAMUX clock for L4+ and G4 */
  780. __HAL_RCC_DMAMUX1_CLK_ENABLE();
  781. #elif defined(SOC_SERIES_STM32MP1)
  782. __HAL_RCC_DMAMUX_CLK_ENABLE();
  783. #endif
  784. UNUSED(tmpreg); /* To avoid compiler warnings */
  785. }
  786. if (RT_DEVICE_FLAG_DMA_RX == flag)
  787. {
  788. __HAL_LINKDMA(&(uart->handle), hdmarx, uart->dma_rx.handle);
  789. }
  790. else if (RT_DEVICE_FLAG_DMA_TX == flag)
  791. {
  792. __HAL_LINKDMA(&(uart->handle), hdmatx, uart->dma_tx.handle);
  793. }
  794. #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32L0)|| defined(SOC_SERIES_STM32F3)
  795. DMA_Handle->Instance = dma_config->Instance;
  796. #elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
  797. DMA_Handle->Instance = dma_config->Instance;
  798. DMA_Handle->Init.Channel = dma_config->channel;
  799. #elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)\
  800. || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
  801. DMA_Handle->Instance = dma_config->Instance;
  802. DMA_Handle->Init.Request = dma_config->request;
  803. #endif
  804. DMA_Handle->Init.PeriphInc = DMA_PINC_DISABLE;
  805. DMA_Handle->Init.MemInc = DMA_MINC_ENABLE;
  806. DMA_Handle->Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
  807. DMA_Handle->Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
  808. if (RT_DEVICE_FLAG_DMA_RX == flag)
  809. {
  810. DMA_Handle->Init.Direction = DMA_PERIPH_TO_MEMORY;
  811. DMA_Handle->Init.Mode = DMA_CIRCULAR;
  812. }
  813. else if (RT_DEVICE_FLAG_DMA_TX == flag)
  814. {
  815. DMA_Handle->Init.Direction = DMA_MEMORY_TO_PERIPH;
  816. DMA_Handle->Init.Mode = DMA_NORMAL;
  817. }
  818. DMA_Handle->Init.Priority = DMA_PRIORITY_MEDIUM;
  819. #if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
  820. DMA_Handle->Init.FIFOMode = DMA_FIFOMODE_DISABLE;
  821. #endif
  822. if (HAL_DMA_DeInit(DMA_Handle) != HAL_OK)
  823. {
  824. RT_ASSERT(0);
  825. }
  826. if (HAL_DMA_Init(DMA_Handle) != HAL_OK)
  827. {
  828. RT_ASSERT(0);
  829. }
  830. /* enable interrupt */
  831. if (flag == RT_DEVICE_FLAG_DMA_RX)
  832. {
  833. rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
  834. /* Start DMA transfer */
  835. if (HAL_UART_Receive_DMA(&(uart->handle), rx_fifo->buffer, serial->config.bufsz) != HAL_OK)
  836. {
  837. /* Transfer error in reception process */
  838. RT_ASSERT(0);
  839. }
  840. CLEAR_BIT(uart->handle.Instance->CR3, USART_CR3_EIE);
  841. __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_IDLE);
  842. }
  843. /* DMA irq should set in DMA TX mode, or HAL_UART_TxCpltCallback function will not be called */
  844. HAL_NVIC_SetPriority(dma_config->dma_irq, 0, 0);
  845. HAL_NVIC_EnableIRQ(dma_config->dma_irq);
  846. HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0);
  847. HAL_NVIC_EnableIRQ(uart->config->irq_type);
  848. LOG_D("%s dma %s instance: %x", uart->config->name, flag == RT_DEVICE_FLAG_DMA_RX ? "RX" : "TX", DMA_Handle->Instance);
  849. LOG_D("%s dma config done", uart->config->name);
  850. }
  851. /**
  852. * @brief UART error callbacks
  853. * @param huart: UART handle
  854. * @note This example shows a simple way to report transfer error, and you can
  855. * add your own implementation.
  856. * @retval None
  857. */
  858. void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
  859. {
  860. RT_ASSERT(huart != NULL);
  861. struct stm32_uart *uart = (struct stm32_uart *)huart;
  862. LOG_D("%s: %s %d\n", __FUNCTION__, uart->config->name, huart->ErrorCode);
  863. UNUSED(uart);
  864. }
  865. /**
  866. * @brief Rx Transfer completed callback
  867. * @param huart: UART handle
  868. * @note This example shows a simple way to report end of DMA Rx transfer, and
  869. * you can add your own implementation.
  870. * @retval None
  871. */
  872. void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
  873. {
  874. struct stm32_uart *uart;
  875. RT_ASSERT(huart != NULL);
  876. uart = (struct stm32_uart *)huart;
  877. dma_isr(&uart->serial);
  878. }
  879. /**
  880. * @brief Rx Half transfer completed callback
  881. * @param huart: UART handle
  882. * @note This example shows a simple way to report end of DMA Rx Half transfer,
  883. * and you can add your own implementation.
  884. * @retval None
  885. */
  886. void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
  887. {
  888. struct stm32_uart *uart;
  889. RT_ASSERT(huart != NULL);
  890. uart = (struct stm32_uart *)huart;
  891. dma_isr(&uart->serial);
  892. }
  893. static void _dma_tx_complete(struct rt_serial_device *serial)
  894. {
  895. struct stm32_uart *uart;
  896. rt_size_t trans_total_index;
  897. rt_base_t level;
  898. RT_ASSERT(serial != RT_NULL);
  899. uart = rt_container_of(serial, struct stm32_uart, serial);
  900. level = rt_hw_interrupt_disable();
  901. trans_total_index = __HAL_DMA_GET_COUNTER(&(uart->dma_tx.handle));
  902. rt_hw_interrupt_enable(level);
  903. if (trans_total_index == 0)
  904. {
  905. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DMADONE);
  906. }
  907. }
  908. /**
  909. * @brief HAL_UART_TxCpltCallback
  910. * @param huart: UART handle
  911. * @note This callback can be called by two functions, first in UART_EndTransmit_IT when
  912. * UART Tx complete and second in UART_DMATransmitCplt function in DMA Circular mode.
  913. * @retval None
  914. */
  915. void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
  916. {
  917. struct stm32_uart *uart;
  918. RT_ASSERT(huart != NULL);
  919. uart = (struct stm32_uart *)huart;
  920. _dma_tx_complete(&uart->serial);
  921. }
  922. #endif /* RT_SERIAL_USING_DMA */
  923. static const struct rt_uart_ops stm32_uart_ops =
  924. {
  925. .configure = stm32_configure,
  926. .control = stm32_control,
  927. .putc = stm32_putc,
  928. .getc = stm32_getc,
  929. .dma_transmit = stm32_dma_transmit
  930. };
  931. int rt_hw_usart_init(void)
  932. {
  933. rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct stm32_uart);
  934. struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
  935. rt_err_t result = 0;
  936. stm32_uart_get_dma_config();
  937. for (int i = 0; i < obj_num; i++)
  938. {
  939. /* init UART object */
  940. uart_obj[i].config = &uart_config[i];
  941. uart_obj[i].serial.ops = &stm32_uart_ops;
  942. uart_obj[i].serial.config = config;
  943. /* register UART device */
  944. result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name,
  945. RT_DEVICE_FLAG_RDWR
  946. | RT_DEVICE_FLAG_INT_RX
  947. | RT_DEVICE_FLAG_INT_TX
  948. | uart_obj[i].uart_dma_flag
  949. , NULL);
  950. RT_ASSERT(result == RT_EOK);
  951. }
  952. return result;
  953. }
  954. #endif /* RT_USING_SERIAL */