board.c 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409
  1. /*
  2. * Copyright (c) 2006-2022, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2010-12-21 onelife Initial creation for EFM32
  9. * 2011-05-06 onelife Add EFM32 development kit and SPI Flash support
  10. * 2011-07-12 onelife Add SWO output enable function
  11. * 2011-12-08 onelife Add giant gecko development kit support
  12. * 2011-12-09 onelife Add giant gecko support
  13. * 2011-12-09 onelife Add LEUART module support
  14. * 2011-12-14 onelife Add LFXO enabling routine in driver initialization function
  15. * 2011-12-15 onelife Add MicroSD initialization routine in driver
  16. * initialization function
  17. * 2011-12-29 onelife Add keys and joystick initialization routine in
  18. * driver initialization function
  19. * 2012-02-15 onelife Modify SWO setup function to support giant gecko
  20. * 2012-xx-xx onelife Modify system clock and ticket related code
  21. */
  22. /***************************************************************************//**
  23. * @addtogroup efm32
  24. * @{
  25. ******************************************************************************/
  26. /* Includes ------------------------------------------------------------------*/
  27. #include "board.h"
  28. /* Private typedef -----------------------------------------------------------*/
  29. /* Private define ------------------------------------------------------------*/
  30. #define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == RAM_MEM_BASE) || \
  31. ((VECTTAB) == FLASH_MEM_BASE))
  32. #define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
  33. /***************************************************************************//**
  34. * @addtogroup SysTick_clock_source
  35. * @{
  36. ******************************************************************************/
  37. #define SysTick_CLKSource_MASK ((rt_uint32_t)0x00000004)
  38. #define SysTick_CLKSource_RTC ((rt_uint32_t)0x00000000)
  39. #define SysTick_CLKSource_HFCORECLK ((rt_uint32_t)0x00000004)
  40. #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_RTC) || \
  41. ((SOURCE) == SysTick_CLKSource_HFCORECLK))
  42. /***************************************************************************//**
  43. * @}
  44. ******************************************************************************/
  45. /* Private macro -------------------------------------------------------------*/
  46. /* Private variables ---------------------------------------------------------*/
  47. /* Private function prototypes -----------------------------------------------*/
  48. /* Private functions ---------------------------------------------------------*/
  49. /***************************************************************************//**
  50. * @brief
  51. * Set the allocation and offset of the vector table
  52. *
  53. * @details
  54. *
  55. * @note
  56. *
  57. * @param[in] NVIC_VectTab
  58. * Indicate the vector table is allocated in RAM or ROM
  59. *
  60. * @param[in] Offset
  61. * The vector table offset
  62. ******************************************************************************/
  63. static void NVIC_SetVectorTable(
  64. rt_uint32_t NVIC_VectTab,
  65. rt_uint32_t Offset)
  66. {
  67. /* Check the parameters */
  68. RT_ASSERT(IS_NVIC_VECTTAB(NVIC_VectTab));
  69. RT_ASSERT(IS_NVIC_OFFSET(Offset));
  70. SCB->VTOR = NVIC_VectTab | (Offset & (rt_uint32_t)0x1FFFFF80);
  71. }
  72. /***************************************************************************//**
  73. * @brief
  74. * Configure the address of vector table
  75. *
  76. * @details
  77. *
  78. * @note
  79. *
  80. ******************************************************************************/
  81. static void NVIC_Configuration(void)
  82. {
  83. #ifdef VECT_TAB_RAM
  84. /* Set the vector table allocated at 0x20000000 */
  85. NVIC_SetVectorTable(RAM_MEM_BASE, 0x0);
  86. #else /* VECT_TAB_FLASH */
  87. /* Set the vector table allocated at 0x00000000 */
  88. NVIC_SetVectorTable(FLASH_MEM_BASE, 0x0);
  89. #endif
  90. /* Set NVIC Preemption Priority Bits: 0 bit for pre-emption, 4 bits for
  91. subpriority */
  92. NVIC_SetPriorityGrouping(0x7UL);
  93. /* Set Base Priority Mask Register */
  94. __set_BASEPRI(EFM32_BASE_PRI_DEFAULT);
  95. }
  96. /***************************************************************************//**
  97. * @brief
  98. * Configure the SysTick clock source
  99. *
  100. * @details
  101. *
  102. * @note
  103. *
  104. * @param[in] SysTick_CLKSource
  105. * Specifies the SysTick clock source.
  106. *
  107. * @arg SysTick_CLKSource_HCLK_Div8
  108. * AHB clock divided by 8 selected as SysTick clock source.
  109. *
  110. * @arg SysTick_CLKSource_HCLK
  111. * AHB clock selected as SysTick clock source.
  112. ******************************************************************************/
  113. static void SysTick_CLKSourceConfig(rt_uint32_t SysTick_CLKSource)
  114. {
  115. /* Check the parameters */
  116. RT_ASSERT(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
  117. rt_uint32_t ctrl = SysTick->CTRL;
  118. ctrl &= ~SysTick_CLKSource_MASK;
  119. ctrl |= SysTick_CLKSource;
  120. SysTick->CTRL = ctrl;
  121. }
  122. /***************************************************************************//**
  123. * @brief
  124. * Configure the SysTick for OS tick.
  125. *
  126. * @details
  127. *
  128. * @note
  129. *
  130. ******************************************************************************/
  131. static void SysTick_Configuration(void)
  132. {
  133. #if defined(EFM32_USING_LFXO)
  134. /* LETIMER0 configurations */
  135. const LETIMER_Init_TypeDef letimerInit =
  136. {
  137. .enable = true, /* Start counting when init completed. */
  138. .debugRun = false, /* Counter shall not keep running during debug halt. */
  139. .rtcComp0Enable = false, /* Don't start counting on RTC COMP0 match. */
  140. .rtcComp1Enable = false, /* Don't start counting on RTC COMP1 match. */
  141. .comp0Top = true, /* Load COMP0 register into CNT when counter underflows. COMP is used as TOP */
  142. .bufTop = false, /* Don't load COMP1 into COMP0 when REP0 reaches 0. */
  143. .out0Pol = 0, /* Idle value for output 0. */
  144. .out1Pol = 0, /* Idle value for output 1. */
  145. .ufoa0 = letimerUFOANone, /* No output on output 0. */
  146. .ufoa1 = letimerUFOANone, /* No output on output 1. */
  147. .repMode = letimerRepeatFree /* Count until stopped by SW. */
  148. };
  149. CMU_ClockDivSet(cmuClock_LETIMER0, cmuClkDiv_8);
  150. CMU_ClockEnable(cmuClock_LETIMER0, true);
  151. LETIMER_CompareSet(LETIMER0, 0,
  152. EFM32_LETIMER_TOP_100HZ * RT_TICK_PER_SECOND / 100);
  153. /* Enable underflow interrupt */
  154. LETIMER_IntClear(LETIMER0, LETIMER_IF_UF);
  155. LETIMER_IntEnable(LETIMER0, LETIMER_IF_UF);
  156. /* Enable LETIMER0 interrupt vector in NVIC */
  157. NVIC_ClearPendingIRQ(LETIMER0_IRQn);
  158. NVIC_SetPriority(LETIMER0_IRQn, EFM32_IRQ_PRI_DEFAULT);
  159. NVIC_EnableIRQ(LETIMER0_IRQn);
  160. /* Start LETIMER0 */
  161. LETIMER_Init(LETIMER0, &letimerInit);
  162. #else
  163. rt_uint32_t coreClk;
  164. rt_uint32_t cnts;
  165. coreClk = SystemCoreClockGet();
  166. cnts = coreClk / RT_TICK_PER_SECOND;
  167. SysTick_Config(cnts);
  168. SysTick_CLKSourceConfig(SysTick_CLKSource_HFCORECLK);
  169. #endif
  170. }
  171. /***************************************************************************//**
  172. * @brief
  173. * Enable SWO.
  174. *
  175. * @details
  176. *
  177. * @note
  178. *
  179. ******************************************************************************/
  180. void Swo_Configuration(void)
  181. {
  182. rt_uint32_t *dwt_ctrl = (rt_uint32_t *) 0xE0001000;
  183. rt_uint32_t *tpiu_prescaler = (rt_uint32_t *) 0xE0040010;
  184. rt_uint32_t *tpiu_protocol = (rt_uint32_t *) 0xE00400F0;
  185. CMU->HFPERCLKEN0 |= CMU_HFPERCLKEN0_GPIO;
  186. /* Enable Serial wire output pin */
  187. GPIO->ROUTE |= GPIO_ROUTE_SWOPEN;
  188. #if defined(_EFM32_GIANT_FAMILY)
  189. /* Set location 0 */
  190. GPIO->ROUTE = (GPIO->ROUTE & ~(_GPIO_ROUTE_SWLOCATION_MASK)) | GPIO_ROUTE_SWLOCATION_LOC0;
  191. /* Enable output on pin - GPIO Port F, Pin 2 */
  192. GPIO->P[5].MODEL &= ~(_GPIO_P_MODEL_MODE2_MASK);
  193. GPIO->P[5].MODEL |= GPIO_P_MODEL_MODE2_PUSHPULL;
  194. #else
  195. /* Set location 1 */
  196. GPIO->ROUTE = (GPIO->ROUTE & ~(_GPIO_ROUTE_SWLOCATION_MASK)) | GPIO_ROUTE_SWLOCATION_LOC1;
  197. /* Enable output on pin */
  198. GPIO->P[2].MODEH &= ~(_GPIO_P_MODEH_MODE15_MASK);
  199. GPIO->P[2].MODEH |= GPIO_P_MODEH_MODE15_PUSHPULL;
  200. #endif
  201. /* Enable debug clock AUXHFRCO */
  202. CMU->OSCENCMD = CMU_OSCENCMD_AUXHFRCOEN;
  203. while(!(CMU->STATUS & CMU_STATUS_AUXHFRCORDY));
  204. /* Enable trace in core debug */
  205. CoreDebug->DHCSR |= 1;
  206. CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
  207. /* Enable PC and IRQ sampling output */
  208. *dwt_ctrl = 0x400113FF;
  209. /* Set TPIU prescaler to 16. */
  210. *tpiu_prescaler = 0xf;
  211. /* Set protocol to NRZ */
  212. *tpiu_protocol = 2;
  213. /* Unlock ITM and output data */
  214. ITM->LAR = 0xC5ACCE55;
  215. ITM->TCR = 0x10009;
  216. }
  217. /***************************************************************************//**
  218. * @brief
  219. * Initialize the board.
  220. *
  221. * @details
  222. *
  223. * @note
  224. *
  225. ******************************************************************************/
  226. void rt_hw_board_init(void)
  227. {
  228. /* Chip errata */
  229. CHIP_Init();
  230. /* Initialize DVK board register access */
  231. #if defined(EFM32_GXXX_DK)
  232. DVK_init();
  233. #elif defined(EFM32GG_DK3750)
  234. DVK_init(DVK_Init_EBI);
  235. /* Disable all DVK interrupts */
  236. DVK_disableInterrupt(BC_INTEN_MASK);
  237. DVK_clearInterruptFlags(BC_INTFLAG_MASK);
  238. #endif
  239. /* config NVIC Configuration */
  240. NVIC_Configuration();
  241. #if defined(EFM32_USING_HFXO)
  242. /* Configure external oscillator */
  243. SystemHFXOClockSet(EFM32_HFXO_FREQUENCY);
  244. /* Switching the CPU clock source to HFXO */
  245. CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFXO);
  246. /* Turning off the high frequency RC Oscillator (HFRCO) */
  247. CMU_OscillatorEnable(cmuOsc_HFRCO, false, false);
  248. #endif
  249. #if defined(EFM32_USING_LFXO)
  250. CMU_ClockSelectSet(cmuClock_LFA,cmuSelect_LFXO);
  251. CMU_ClockSelectSet(cmuClock_LFB, cmuSelect_LFXO);
  252. #endif
  253. #if defined(EFM32_SWO_ENABLE)
  254. /* Enable SWO */
  255. Swo_Configuration();
  256. #endif
  257. /* Enable high frequency peripheral clock */
  258. CMU_ClockEnable(cmuClock_HFPER, true);
  259. /* Enabling clock to the interface of the low energy modules */
  260. CMU_ClockEnable(cmuClock_CORELE, true);
  261. /* Enable GPIO clock */
  262. CMU_ClockEnable(cmuClock_GPIO, true);
  263. /* Configure the SysTick */
  264. SysTick_Configuration();
  265. }
  266. /***************************************************************************//**
  267. * @brief
  268. * Initialize the hardware drivers.
  269. *
  270. * @details
  271. *
  272. * @note
  273. *
  274. ******************************************************************************/
  275. void rt_hw_driver_init(void)
  276. {
  277. /* Initialize DMA */
  278. rt_hw_dma_init();
  279. /* Select LFXO for specified module (and wait for it to stabilize) */
  280. #if (!defined(EFM32_USING_LFXO) && defined(RT_USING_RTC))
  281. #error "Low frequency clock source is needed for using RTC"
  282. #endif
  283. #if (!defined(EFM32_USING_LFXO )&& \
  284. (defined(RT_USING_LEUART0) || defined(RT_USING_LEUART1)))
  285. #error "Low frequency clock source is needed for using LEUART"
  286. #endif
  287. /* Initialize USART */
  288. #if (defined(RT_USING_USART0) || defined(RT_USING_USART1) || \
  289. defined(RT_USING_USART2) || defined(RT_USING_UART0) || \
  290. defined(RT_USING_UART1))
  291. rt_hw_usart_init();
  292. #endif
  293. /* Initialize LEUART */
  294. #if (defined(RT_USING_LEUART0) || defined(RT_USING_LEUART1))
  295. rt_hw_leuart_init();
  296. #endif
  297. /* Setup Console */
  298. #if defined(EFM32_GXXX_DK)
  299. DVK_enablePeripheral(DVK_RS232A);
  300. DVK_enablePeripheral(DVK_SPI);
  301. #elif defined(EFM32GG_DK3750)
  302. #if (RT_CONSOLE_DEVICE == EFM_UART1)
  303. DVK_enablePeripheral(DVK_RS232_UART);
  304. #elif (RT_CONSOLE_DEVICE == EFM_LEUART1)
  305. DVK_enablePeripheral(DVK_RS232_LEUART);
  306. #endif
  307. #endif
  308. rt_console_set_device(CONSOLE_DEVICE);
  309. /* Initialize Timer */
  310. #if (defined(RT_USING_TIMER0) || defined(RT_USING_TIMER1) || defined(RT_USING_TIMER2))
  311. rt_hw_timer_init();
  312. #endif
  313. /* Initialize ADC */
  314. #if defined(RT_USING_ADC0)
  315. rt_hw_adc_init();
  316. #endif
  317. /* Initialize ACMP */
  318. #if (defined(RT_USING_ACMP0) || defined(RT_USING_ACMP1))
  319. rt_hw_acmp_init();
  320. #endif
  321. /* Initialize IIC */
  322. #if (defined(RT_USING_IIC0) || defined(RT_USING_IIC1))
  323. rt_hw_iic_init();
  324. #endif
  325. /* Initialize RTC */
  326. #if defined(RT_USING_RTC)
  327. rt_hw_rtc_init();
  328. #endif
  329. /* Enable SPI access to MicroSD card */
  330. #if defined(EFM32_USING_SPISD)
  331. #if defined(EFM32_GXXX_DK)
  332. DVK_writeRegister(BC_SPI_CFG, 1);
  333. #elif defined(EFM32GG_DK3750)
  334. DVK_enablePeripheral(DVK_MICROSD);
  335. #endif
  336. #endif
  337. /* Enable SPI access to Ethernet */
  338. #if defined(EFM32_USING_ETHERNET)
  339. #if defined(EFM32GG_DK3750)
  340. DVK_enablePeripheral(DVK_ETH);
  341. #endif
  342. #endif
  343. /* Initialize LCD */
  344. #if defined(EFM32_USING_LCD)
  345. efm32_spiLcd_init();
  346. #endif
  347. /* Initialize Keys */
  348. #if defined(EFM32_USING_KEYS)
  349. #if defined(EFM32GG_DK3750)
  350. efm32_hw_keys_init();
  351. #endif
  352. #endif
  353. }
  354. /***************************************************************************//**
  355. * @}
  356. ******************************************************************************/