hpm_ov7725.c 9.3 KB

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  1. /*
  2. * Copyright (c) 2021 HPMicro
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. *
  6. */
  7. #include "hpm_ov7725.h"
  8. static const uint8_t ov7725_default_regs[][2] = {
  9. {COM4, 0x41}, /* bypass PLL */
  10. /*
  11. * VGA Window Size
  12. */
  13. {HSTART, 0x22},
  14. {HSIZE, 0xa4},
  15. {VSTART, 0x07},
  16. {VSIZE, 0xf0},
  17. {HREF, 0x00},
  18. /*
  19. * Scale down to VGA Resolution
  20. */
  21. {HOUTSIZE, 0xA0},
  22. {VOUTSIZE, 0xF0},
  23. {COM12, 0x03},
  24. {EXHCH, 0x00},
  25. {TGT_B, 0x7F},
  26. {FIXGAIN, 0x09},
  27. {AWB_CTRL0, 0xE0},
  28. {DSP_CTRL1, 0xFF},
  29. {DSP_CTRL2, 0x20},
  30. {DSP_CTRL3, 0x00},
  31. {DSP_CTRL4, 0x00},
  32. {COM8, 0xF8},
  33. {COM6, 0xC5},
  34. {COM9, 0x11},
  35. {COM10, COM10_VSYNC_NEG | COM10_PCLK_MASK}, /* Invert VSYNC and MASK PCLK */
  36. {BDBASE, 0x7F},
  37. {DBSTEP, 0x03},
  38. {AEW, 0x70},
  39. {AEB, 0x43},
  40. {VPT, 0xA1},
  41. {EXHCL, 0x00},
  42. {AWB_CTRL3, 0xAA},
  43. {COM8, 0xFF},
  44. /*
  45. * Gamma
  46. */
  47. {GAM1, 0x0C},
  48. {GAM2, 0x16},
  49. {GAM3, 0x2A},
  50. {GAM4, 0x4E},
  51. {GAM5, 0x61},
  52. {GAM6, 0x6F},
  53. {GAM7, 0x7B},
  54. {GAM8, 0x86},
  55. {GAM9, 0x8E},
  56. {GAM10, 0x97},
  57. {GAM11, 0xA4},
  58. {GAM12, 0xAF},
  59. {GAM13, 0xC5},
  60. {GAM14, 0xD7},
  61. {GAM15, 0xE8},
  62. {SLOP, 0x20},
  63. {EDGE1, 0x05},
  64. {EDGE2, 0x03},
  65. {EDGE3, 0x00},
  66. {DNSOFF, 0x01},
  67. {MTX1, 0xB0},
  68. {MTX2, 0x9D},
  69. {MTX3, 0x13},
  70. {MTX4, 0x16},
  71. {MTX5, 0x7B},
  72. {MTX6, 0x91},
  73. {MTX_CTRL, 0x1E},
  74. {BRIGHTNESS, 0x08},
  75. {CONTRAST, 0x20},
  76. {UVADJ0, 0x81},
  77. {SDE, (SDE_CONT_BRIGHT_EN | SDE_SATURATION_EN)},
  78. /*
  79. * For 30 fps/60Hz
  80. */
  81. {DM_LNL, 0x00},
  82. {DM_LNH, 0x00},
  83. {BDBASE, 0x7F},
  84. {DBSTEP, 0x03},
  85. /*
  86. * Lens Correction, should be tuned with real camera module
  87. */
  88. {LC_RADI, 0x10},
  89. {LC_COEF, 0x10},
  90. {LC_COEFB, 0x14},
  91. {LC_COEFR, 0x17},
  92. {LC_CTR, 0x05},
  93. {COM5, 0x65},
  94. };
  95. static const uint8_t ov7725_default_yuv_regs[][2] = {
  96. {COM12, 0x03},
  97. {HSTART, 0x22},
  98. {HSIZE, 0xa4},
  99. {VSTART, 0x07},
  100. {VSIZE, 0xf0},
  101. {HREF, 0x00},
  102. {HOUTSIZE, 0xa0},
  103. {VOUTSIZE, 0xf0},
  104. {EXHCH, 0x00},
  105. {CLKRC, 0x01},
  106. {TGT_B, 0x7f},
  107. {FIXGAIN, 0x09},
  108. {AWB_CTRL0, 0xe0},
  109. {DSP_CTRL1, 0xff},
  110. {DSP_CTRL2, 0x20},
  111. {DSP_CTRL3, 0x00},
  112. {DSP_CTRL4, 0x48},
  113. {COM8, 0xf0},
  114. {COM4, 0x41}, /* 0x51/ 0x61/ 0x71 for different AEC/AGC window */
  115. {COM6, 0xc5},
  116. {COM9, 0x11},
  117. {BDBASE, 0x7f},
  118. {DBSTEP, 0x03},
  119. {AEW, 0x40},
  120. {AEB, 0x30},
  121. {VPT, 0xa1},
  122. {EXHCL, 0x00},
  123. {AWB_CTRL3, 0xaa},
  124. {COM8, 0xff},
  125. {EDGE1, 0x05},
  126. {DNSOFF, 0x01},
  127. {EDGE2, 0x03},
  128. {EDGE3, 0x00},
  129. {MTX1, 0xb0},
  130. {MTX2, 0x9d},
  131. {MTX3, 0x13},
  132. {MTX4, 0x16},
  133. {MTX5, 0x7b},
  134. {MTX6, 0x91},
  135. {MTX_CTRL, 0x1e},
  136. {BRIGHTNESS, 0x08},
  137. {CONTRAST, 0x20},
  138. {UVADJ0, 0x81},
  139. {SDE, 0x06},
  140. /* Gamma */
  141. {GAM1, 0x0c},
  142. {GAM2, 0x16},
  143. {GAM3, 0x2a},
  144. {GAM4, 0x4e},
  145. {GAM5, 0x61},
  146. {GAM6, 0x6f},
  147. {GAM7, 0x7b},
  148. {GAM8, 0x86},
  149. {GAM9, 0x8e},
  150. {GAM10, 0x97},
  151. {GAM11, 0xa4},
  152. {GAM12, 0xaf},
  153. {GAM13, 0xc5},
  154. {GAM14, 0xd7},
  155. {GAM15, 0xe8},
  156. {SLOP, 0x20},
  157. /* for 30 fps,0Hz */
  158. {DM_LNL, 0x00},
  159. {BDBASE, 0x7f},
  160. {DBSTEP, 0x03},
  161. /* Lens Correcon, should be tuned with real camera module */
  162. {LC_RADI, 0x10},
  163. {LC_COEF, 0x10},
  164. {LC_COEFB, 0x14},
  165. {LC_COEFR, 0x17},
  166. {LC_CTR, 0x05},
  167. {COM5, 0x65},
  168. };
  169. hpm_stat_t ov7725_read_register(camera_context_t *context, uint8_t reg, uint8_t *buf)
  170. {
  171. hpm_stat_t stat = i2c_master_write(context->ptr, context->i2c_device_addr, &reg, 1);
  172. if (stat != status_success) {
  173. return stat;
  174. }
  175. return i2c_master_read(context->ptr, context->i2c_device_addr, buf, 1);
  176. }
  177. hpm_stat_t ov7725_write_register(camera_context_t *context, uint8_t reg, uint8_t val)
  178. {
  179. return i2c_master_address_write(context->ptr, context->i2c_device_addr, &reg, 1, &val, 1);
  180. }
  181. hpm_stat_t ov7725_load_settings(camera_context_t *context, uint8_t *reg_values, uint32_t count)
  182. {
  183. hpm_stat_t stat = status_success;
  184. for (uint32_t i = 0, j = 0; i < count; i++, j += 2) {
  185. stat = ov7725_write_register(context, reg_values[j], reg_values[j+1]);
  186. if (stat != status_success) {
  187. break;
  188. }
  189. }
  190. return stat;
  191. }
  192. hpm_stat_t ov7725_software_reset(camera_context_t *context)
  193. {
  194. hpm_stat_t stat = status_success;
  195. stat = ov7725_write_register(context, COM7, COM7_RESET);
  196. if (stat != status_success) {
  197. return stat;
  198. }
  199. return stat;
  200. }
  201. hpm_stat_t ov7725_check_chip_id(camera_context_t *context)
  202. {
  203. hpm_stat_t stat = status_success;
  204. uint8_t val_h = 0;
  205. uint8_t val_l = 0;
  206. HPM_CHECK_RET(ov7725_read_register(context, OV7725_CHIP_ID_HIGH_BYTE_ADDR, &val_h));
  207. HPM_CHECK_RET(ov7725_read_register(context, OV7725_CHIP_ID_LOW_BYTE_ADDR, &val_l));
  208. if (val_h != OV7725_CHIP_ID_HIGH_BYTE_VALUE) {
  209. return status_fail;
  210. }
  211. if (val_l != OV7725_CHIP_ID_LOW_BYTE_VALUE) {
  212. return status_fail;
  213. }
  214. return stat;
  215. }
  216. static hpm_stat_t ov7725_set_framesize(camera_context_t *context, uint16_t width, uint16_t height)
  217. {
  218. hpm_stat_t stat = status_success;
  219. uint32_t hstart = 0x22U << 2;
  220. uint32_t vstart = 0x7U << 1;
  221. uint32_t hsize = width + 16;
  222. stat |= ov7725_write_register(context, HSTART, hstart >> 2);
  223. stat |= ov7725_write_register(context, HSIZE, hsize >> 2);
  224. stat |= ov7725_write_register(context, VSTART, vstart >> 1);
  225. stat |= ov7725_write_register(context, VSIZE, height >> 1);
  226. stat |= ov7725_write_register(context, HOUTSIZE, width >> 2);
  227. stat |= ov7725_write_register(context, VOUTSIZE, height >> 1);
  228. stat |= ov7725_write_register(context, HREF,
  229. ((vstart & 1) << 6) | ((hstart & 3) << 4) | ((height & 1) << 2) | ((hsize & 3) << 0));
  230. stat = ov7725_write_register(context, EXHCH, ((height & 0x1) << 2) | (width & 0x3));
  231. if (stat != status_success) {
  232. return stat;
  233. }
  234. return stat;
  235. }
  236. hpm_stat_t ov7725_set_pixel_format(camera_context_t *context, display_pixel_format_t pixel_format)
  237. {
  238. hpm_stat_t stat = status_success;
  239. uint8_t val = 0;
  240. stat |= ov7725_read_register(context, COM7, &val);
  241. val &= ~0x1F;
  242. switch (pixel_format) {
  243. case display_pixel_format_rgb565:
  244. val |= COM7_FMT_RGB565;
  245. break;
  246. case display_pixel_format_rgb444:
  247. val |= COM7_FMT_RGB444;
  248. break;
  249. case display_pixel_format_yuv422:
  250. case display_pixel_format_y8:
  251. val |= COM7_FMT_YUV;
  252. break;
  253. case display_pixel_format_raw8:
  254. stat |= ov7725_write_register(context, DSP_CTRL4, DSP_CTRL4_RAW8);
  255. val |= COM7_FMT_R_BAYER;
  256. break;
  257. default:
  258. stat = status_invalid_argument;
  259. break;
  260. }
  261. if (stat != status_success) {
  262. return stat;
  263. }
  264. stat |= ov7725_write_register(context, COM7, val);
  265. if (stat != status_success) {
  266. return stat;
  267. }
  268. return stat;
  269. }
  270. hpm_stat_t ov7725_init(camera_context_t *context, camera_config_t *ov_config)
  271. {
  272. hpm_stat_t stat = status_success;
  273. switch (ov_config->pixel_format) {
  274. case display_pixel_format_yuv422:
  275. case display_pixel_format_y8:
  276. ov7725_load_settings(context, (uint8_t *) ov7725_default_yuv_regs, ARRAY_SIZE(ov7725_default_yuv_regs));
  277. break;
  278. default:
  279. ov7725_load_settings(context, (uint8_t *) ov7725_default_regs, ARRAY_SIZE(ov7725_default_regs));
  280. stat |= ov7725_write_register(context, COM7, COM7_RES_VGA | COM7_FMT_RGB565);
  281. stat |= ov7725_write_register(context, COM10, 0);
  282. stat |= ov7725_write_register(context, COM3, 0);
  283. break;
  284. }
  285. stat |= ov7725_write_register(context, CLKRC, 0x2);
  286. stat |= ov7725_write_register(context, COM4, 0x41);
  287. stat |= ov7725_set_framesize(context, ov_config->width, ov_config->height);
  288. stat |= ov7725_set_pixel_format(context, ov_config->pixel_format);
  289. if (stat != status_success) {
  290. return stat;
  291. }
  292. return stat;
  293. }
  294. void ov7725_power_up(camera_context_t *context)
  295. {
  296. assert(context->delay_ms != NULL);
  297. if (context->write_rst) {
  298. context->write_rst(OV7725_RST_ACTIVE);
  299. }
  300. if (context->write_pwdn) {
  301. context->write_pwdn(OV7725_PWDN_ACTIVE);
  302. }
  303. context->delay_ms(5);
  304. if (context->write_pwdn) {
  305. context->write_pwdn(OV7725_PWDN_INACTIVE);
  306. }
  307. context->delay_ms(2);
  308. if (context->write_rst) {
  309. context->write_rst(OV7725_RST_INACTIVE);
  310. }
  311. context->delay_ms(20);
  312. }