drv_smc911x.c 15 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2020/12/31 Bernard Add license info
  9. */
  10. #include <board.h>
  11. #include <rtthread.h>
  12. #include <rtdevice.h>
  13. #include <automac.h>
  14. #include <netif/ethernetif.h>
  15. #include <lwipopts.h>
  16. #include "delay.h"
  17. #include "mmu.h"
  18. #include "drv_smc911x.h"
  19. #define MAX_ADDR_LEN 6
  20. #define SMC911X_EMAC_DEVICE(eth) (struct eth_device_smc911x*)(eth)
  21. #define DRIVERNAME "EMAC"
  22. #define DBG_LVL DBG_LOG
  23. #define DBG_TAG "EMAC"
  24. #include <rtdbg.h>
  25. struct eth_device_smc911x
  26. {
  27. /* inherit from Ethernet device */
  28. struct eth_device parent;
  29. /* interface address info. */
  30. rt_uint8_t enetaddr[MAX_ADDR_LEN]; /* MAC address */
  31. uint32_t iobase;
  32. uint32_t irqno;
  33. };
  34. static struct eth_device_smc911x _emac;
  35. #if defined (CONFIG_SMC911X_32_BIT)
  36. rt_inline uint32_t smc911x_reg_read(struct eth_device_smc911x *dev, uint32_t offset)
  37. {
  38. return *(volatile uint32_t *)(dev->iobase + offset);
  39. }
  40. rt_inline void smc911x_reg_write(struct eth_device_smc911x *dev, uint32_t offset, uint32_t val)
  41. {
  42. *(volatile uint32_t *)(dev->iobase + offset) = val;
  43. }
  44. #elif defined (CONFIG_SMC911X_16_BIT)
  45. rt_inline uint32_t smc911x_reg_read(struct eth_device_smc911x *dev, uint32_t offset)
  46. {
  47. volatile uint16_t *addr_16 = (uint16_t *)(dev->iobase + offset);
  48. return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16));
  49. }
  50. rt_inline void smc911x_reg_write(struct eth_device_smc911x *dev, uint32_t offset, uint32_t val)
  51. {
  52. *(volatile uint16_t *)(dev->iobase + offset) = (uint16_t)val;
  53. *(volatile uint16_t *)(dev->iobase + offset + 2) = (uint16_t)(val >> 16);
  54. }
  55. #else
  56. #error "SMC911X: undefined bus width"
  57. #endif /* CONFIG_SMC911X_16_BIT */
  58. struct chip_id
  59. {
  60. uint16_t id;
  61. char *name;
  62. };
  63. static const struct chip_id chip_ids[] =
  64. {
  65. { LAN9118_ID_89218, "LAN89218" },
  66. { LAN9118_ID_9115, "LAN9115" },
  67. { LAN9118_ID_9116, "LAN9116" },
  68. { LAN9118_ID_9117, "LAN9117" },
  69. { LAN9118_ID_9118, "LAN9118" },
  70. { LAN9210_ID_9211, "LAN9211" },
  71. { LAN9218_ID_9215, "LAN9215" },
  72. { LAN9218_ID_9216, "LAN9216" },
  73. { LAN9218_ID_9217, "LAN9217" },
  74. { LAN9218_ID_9218, "LAN9218" },
  75. { LAN9220_ID_9220, "LAN9220" },
  76. { LAN9220_ID_9221, "LAN9221" },
  77. { 0, RT_NULL },
  78. };
  79. static uint32_t smc911x_get_mac_csr(struct eth_device_smc911x *dev, uint8_t reg)
  80. {
  81. while (smc911x_reg_read(dev, LAN9118_MAC_CSR_CMD) & LAN9118_MAC_CSR_CMD_BUSY) ;
  82. smc911x_reg_write(dev, LAN9118_MAC_CSR_CMD, LAN9118_MAC_CSR_CMD_BUSY | LAN9118_MAC_CSR_CMD_R | reg);
  83. while (smc911x_reg_read(dev, LAN9118_MAC_CSR_CMD) & LAN9118_MAC_CSR_CMD_BUSY) ;
  84. return smc911x_reg_read(dev, LAN9118_MAC_CSR_DATA);
  85. }
  86. static void smc911x_set_mac_csr(struct eth_device_smc911x *dev, uint8_t reg, uint32_t data)
  87. {
  88. while (smc911x_reg_read(dev, LAN9118_MAC_CSR_CMD) & LAN9118_MAC_CSR_CMD_BUSY) ;
  89. smc911x_reg_write(dev, LAN9118_MAC_CSR_DATA, data);
  90. smc911x_reg_write(dev, LAN9118_MAC_CSR_CMD, LAN9118_MAC_CSR_CMD_BUSY | reg);
  91. while (smc911x_reg_read(dev, LAN9118_MAC_CSR_CMD) & LAN9118_MAC_CSR_CMD_BUSY) ;
  92. }
  93. static int smc911x_detect_chip(struct eth_device_smc911x *dev)
  94. {
  95. unsigned long val, i;
  96. val = smc911x_reg_read(dev, LAN9118_BYTE_TEST);
  97. if (val == 0xffffffff)
  98. {
  99. /* Special case -- no chip present */
  100. return -1;
  101. }
  102. else if (val != 0x87654321)
  103. {
  104. LOG_E("Invalid chip endian 0x%08lx\n", val);
  105. return -1;
  106. }
  107. val = smc911x_reg_read(dev, LAN9118_ID_REV) >> 16;
  108. for (i = 0; chip_ids[i].id != 0; i++)
  109. {
  110. if (chip_ids[i].id == val) break;
  111. }
  112. if (!chip_ids[i].id)
  113. {
  114. rt_kprintf(DRIVERNAME ": Unknown chip ID %04lx\n", val);
  115. return -1;
  116. }
  117. return 0;
  118. }
  119. static void smc911x_reset(struct eth_device_smc911x *dev)
  120. {
  121. int timeout;
  122. /*
  123. * Take out of PM setting first
  124. * Device is already wake up if LAN9118_PMT_CTRL_READY bit is set
  125. */
  126. if ((smc911x_reg_read(dev, LAN9118_PMT_CTRL) & LAN9118_PMT_CTRL_READY) == 0)
  127. {
  128. /* Write to the bytetest will take out of powerdown */
  129. smc911x_reg_write(dev, LAN9118_BYTE_TEST, 0x0);
  130. timeout = 10;
  131. while (timeout-- && !(smc911x_reg_read(dev, LAN9118_PMT_CTRL) & LAN9118_PMT_CTRL_READY))
  132. udelay(10);
  133. if (timeout < 0)
  134. {
  135. rt_kprintf(DRIVERNAME
  136. ": timeout waiting for PM restore\n");
  137. return;
  138. }
  139. }
  140. /* Disable interrupts */
  141. smc911x_reg_write(dev, LAN9118_INT_EN, 0);
  142. smc911x_reg_write(dev, LAN9118_HW_CFG, LAN9118_HW_CFG_SRST);
  143. timeout = 1000;
  144. while (timeout-- && smc911x_reg_read(dev, LAN9118_E2P_CMD) & LAN9118_E2P_CMD)
  145. udelay(10);
  146. if (timeout < 0)
  147. {
  148. rt_kprintf(DRIVERNAME ": reset timeout\n");
  149. return;
  150. }
  151. /* Reset the FIFO level and flow control settings */
  152. smc911x_set_mac_csr(dev, LAN9118_FLOW, LAN9118_FLOW_FCPT(0xffff) | LAN9118_FLOW_FCEN);
  153. smc911x_reg_write(dev, LAN9118_AFC_CFG, 0x0050287F);
  154. /* Set to LED outputs */
  155. smc911x_reg_write(dev, LAN9118_GPIO_CFG, 0x70070000);
  156. }
  157. static void smc911x_handle_mac_address(struct eth_device_smc911x *dev)
  158. {
  159. unsigned long addrh, addrl;
  160. uint8_t *m = dev->enetaddr;
  161. addrl = m[0] | (m[1] << 8) | (m[2] << 16) | (m[3] << 24);
  162. addrh = m[4] | (m[5] << 8);
  163. smc911x_set_mac_csr(dev, LAN9118_ADDRL, addrl);
  164. smc911x_set_mac_csr(dev, LAN9118_ADDRH, addrh);
  165. }
  166. static int smc911x_eth_phy_read(struct eth_device_smc911x *dev,
  167. uint8_t phy, uint8_t reg, uint16_t *val)
  168. {
  169. while (smc911x_get_mac_csr(dev, LAN9118_MII_ACC) & LAN9118_MII_ACC_MIIBZY) ;
  170. smc911x_set_mac_csr(dev, LAN9118_MII_ACC, phy << 11 | reg << 6 | LAN9118_MII_ACC_MIIBZY);
  171. while (smc911x_get_mac_csr(dev, LAN9118_MII_ACC) & LAN9118_MII_ACC_MIIBZY) ;
  172. *val = smc911x_get_mac_csr(dev, LAN9118_MII_DATA);
  173. return 0;
  174. }
  175. static int smc911x_eth_phy_write(struct eth_device_smc911x *dev,
  176. uint8_t phy, uint8_t reg, uint16_t val)
  177. {
  178. while (smc911x_get_mac_csr(dev, LAN9118_MII_ACC) & LAN9118_MII_ACC_MIIBZY)
  179. ;
  180. smc911x_set_mac_csr(dev, LAN9118_MII_DATA, val);
  181. smc911x_set_mac_csr(dev, LAN9118_MII_ACC,
  182. phy << 11 | reg << 6 | LAN9118_MII_ACC_MIIBZY | LAN9118_MII_ACC_MIIWNR);
  183. while (smc911x_get_mac_csr(dev, LAN9118_MII_ACC) & LAN9118_MII_ACC_MIIBZY)
  184. ;
  185. return 0;
  186. }
  187. static int smc911x_phy_reset(struct eth_device_smc911x *dev)
  188. {
  189. uint32_t reg;
  190. reg = smc911x_reg_read(dev, LAN9118_PMT_CTRL);
  191. reg &= ~0xfffff030;
  192. reg |= LAN9118_PMT_CTRL_PHY_RST;
  193. smc911x_reg_write(dev, LAN9118_PMT_CTRL, reg);
  194. mdelay(100);
  195. return 0;
  196. }
  197. static void smc911x_phy_configure(struct eth_device_smc911x *dev)
  198. {
  199. int timeout;
  200. uint16_t status;
  201. smc911x_phy_reset(dev);
  202. smc911x_eth_phy_write(dev, 1, LAN9118_MII_BMCR, LAN9118_BMCR_RESET);
  203. mdelay(1);
  204. smc911x_eth_phy_write(dev, 1, LAN9118_MII_ADVERTISE, 0x01e1);
  205. smc911x_eth_phy_write(dev, 1, LAN9118_MII_BMCR, LAN9118_BMCR_ANENABLE | LAN9118_BMCR_ANRESTART);
  206. timeout = 5000;
  207. do
  208. {
  209. mdelay(1);
  210. if ((timeout--) == 0)
  211. goto err_out;
  212. if (smc911x_eth_phy_read(dev, 1, LAN9118_MII_BMSR, &status) != 0)
  213. goto err_out;
  214. }
  215. while (!(status & LAN9118_BMSR_LSTATUS));
  216. return;
  217. err_out:
  218. rt_kprintf(DRIVERNAME ": autonegotiation timed out\n");
  219. }
  220. static void smc911x_enable(struct eth_device_smc911x *dev)
  221. {
  222. /* Enable TX */
  223. smc911x_reg_write(dev, LAN9118_HW_CFG, 8 << 16 | LAN9118_HW_CFG_SF);
  224. smc911x_reg_write(dev, LAN9118_GPT_CFG, LAN9118_GPT_CFG_TIMER_EN | 10000);
  225. smc911x_reg_write(dev, LAN9118_TX_CFG, LAN9118_TX_CFG_TX_ON);
  226. /* no padding to start of packets */
  227. smc911x_reg_write(dev, LAN9118_RX_CFG, 0);
  228. smc911x_set_mac_csr(dev, LAN9118_MAC_CR, LAN9118_MAC_CR_TXEN | LAN9118_MAC_CR_RXEN |
  229. LAN9118_MAC_CR_HBDIS);
  230. }
  231. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  232. /* wrapper for smc911x_eth_phy_read */
  233. static int smc911x_miiphy_read(struct mii_dev *bus, int phy, int devad,
  234. int reg)
  235. {
  236. uint16_t val = 0;
  237. struct eth_device_smc911x *dev = eth_get_dev_by_name(bus->name);
  238. if (dev)
  239. {
  240. int retval = smc911x_eth_phy_read(dev, phy, reg, &val);
  241. if (retval < 0)
  242. return retval;
  243. return val;
  244. }
  245. return -ENODEV;
  246. }
  247. /* wrapper for smc911x_eth_phy_write */
  248. static int smc911x_miiphy_write(struct mii_dev *bus, int phy, int devad,
  249. int reg, uint16_t val)
  250. {
  251. struct eth_device_smc911x *dev = eth_get_dev_by_name(bus->name);
  252. if (dev)
  253. return smc911x_eth_phy_write(dev, phy, reg, val);
  254. return -ENODEV;
  255. }
  256. #endif
  257. static void smc911x_isr(int vector, void *param)
  258. {
  259. uint32_t status;
  260. struct eth_device_smc911x *emac;
  261. emac = SMC911X_EMAC_DEVICE(param);
  262. status = smc911x_reg_read(emac, LAN9118_INT_STS);
  263. if (status & LAN9118_INT_STS_RSFL)
  264. {
  265. eth_device_ready(&emac->parent);
  266. }
  267. smc911x_reg_write(emac, LAN9118_INT_STS, status);
  268. return ;
  269. }
  270. static rt_err_t smc911x_emac_init(rt_device_t dev)
  271. {
  272. // uint32_t value;
  273. struct eth_device_smc911x *emac;
  274. emac = SMC911X_EMAC_DEVICE(dev);
  275. RT_ASSERT(emac != RT_NULL);
  276. smc911x_reset(emac);
  277. /* Configure the PHY, initialize the link state */
  278. smc911x_phy_configure(emac);
  279. smc911x_handle_mac_address(emac);
  280. /* Turn on Tx + Rx */
  281. smc911x_enable(emac);
  282. /* Interrupt on every received packet */
  283. smc911x_reg_write(emac, LAN9118_FIFO_INT, 0x01 << 8);
  284. smc911x_reg_write(emac, LAN9118_INT_EN, LAN9118_INT_EN_RDFL_EN | LAN9118_INT_RSFL);
  285. /* enable interrupt */
  286. smc911x_reg_write(emac, LAN9118_IRQ_CFG, LAN9118_IRQ_CFG_IRQ_EN | LAN9118_IRQ_CFG_IRQ_POL | LAN9118_IRQ_CFG_IRQ_TYPE);
  287. rt_hw_interrupt_install(emac->irqno, smc911x_isr, emac, "smc911x");
  288. rt_hw_interrupt_umask(emac->irqno);
  289. return RT_EOK;
  290. }
  291. static rt_err_t smc911x_emac_control(rt_device_t dev, int cmd, void *args)
  292. {
  293. struct eth_device_smc911x *emac;
  294. emac = SMC911X_EMAC_DEVICE(dev);
  295. RT_ASSERT(emac != RT_NULL);
  296. switch (cmd)
  297. {
  298. case NIOCTL_GADDR:
  299. /* get MAC address */
  300. if (args) rt_memcpy(args, emac->enetaddr, 6);
  301. else return -RT_ERROR;
  302. break;
  303. default :
  304. break;
  305. }
  306. return RT_EOK;
  307. }
  308. /* Ethernet device interface */
  309. /* transmit packet. */
  310. static uint8_t tx_buf[2048];
  311. rt_err_t smc911x_emac_tx(rt_device_t dev, struct pbuf *p)
  312. {
  313. struct eth_device_smc911x *emac;
  314. uint32_t *data;
  315. uint32_t tmplen;
  316. uint32_t status;
  317. uint32_t length;
  318. emac = SMC911X_EMAC_DEVICE(dev);
  319. RT_ASSERT(emac != RT_NULL);
  320. /* copy pbuf to a whole ETH frame */
  321. pbuf_copy_partial(p, tx_buf, p->tot_len, 0);
  322. /* send it out */
  323. data = (uint32_t *)tx_buf;
  324. length = p->tot_len;
  325. smc911x_reg_write(emac, LAN9118_TXDFIFOP, LAN9118_TXC_A_FS | LAN9118_TXC_A_LS | length);
  326. smc911x_reg_write(emac, LAN9118_TXDFIFOP, length);
  327. tmplen = (length + 3) / 4;
  328. while (tmplen--)
  329. {
  330. smc911x_reg_write(emac, LAN9118_TXDFIFOP, *data++);
  331. }
  332. /* wait for transmission */
  333. while (!(LAN9118_TX_FIFO_INF_TXSUSED(smc911x_reg_read(emac, LAN9118_TX_FIFO_INF))));
  334. /* get status. Ignore 'no carrier' error, it has no meaning for
  335. * full duplex operation
  336. */
  337. status = smc911x_reg_read(emac, LAN9118_TXSFIFOP) &
  338. (LAN9118_TXS_LOC | LAN9118_TXS_LCOL | LAN9118_TXS_ECOL |
  339. LAN9118_TXS_ED | LAN9118_TX_STS_UNDERRUN);
  340. if (!status) return 0;
  341. LOG_E(DRIVERNAME ": failed to send packet: %s%s%s%s%s\n",
  342. status & LAN9118_TXS_LOC ? "LAN9118_TXS_LOC " : "",
  343. status & LAN9118_TXS_LCOL ? "LAN9118_TXS_LCOL " : "",
  344. status & LAN9118_TXS_ECOL ? "LAN9118_TXS_ECOL " : "",
  345. status & LAN9118_TXS_ED ? "LAN9118_TXS_ED " : "",
  346. status & LAN9118_TX_STS_UNDERRUN ? "LAN9118_TX_STS_UNDERRUN" : "");
  347. return -RT_EIO;
  348. }
  349. /* reception packet. */
  350. struct pbuf *smc911x_emac_rx(rt_device_t dev)
  351. {
  352. struct pbuf *p = RT_NULL;
  353. struct eth_device_smc911x *emac;
  354. emac = SMC911X_EMAC_DEVICE(dev);
  355. RT_ASSERT(emac != RT_NULL);
  356. /* take the emac buffer to the pbuf */
  357. if (LAN9118_RX_FIFO_INF_RXSUSED(smc911x_reg_read(emac, LAN9118_RX_FIFO_INF)))
  358. {
  359. uint32_t status;
  360. uint32_t pktlen, tmplen;
  361. status = smc911x_reg_read(emac, LAN9118_RXSFIFOP);
  362. /* get frame length */
  363. pktlen = (status & LAN9118_RX_STS_PKT_LEN) >> 16;
  364. smc911x_reg_write(emac, LAN9118_RX_CFG, 0);
  365. tmplen = (pktlen + 3) / 4;
  366. /* allocate pbuf */
  367. p = pbuf_alloc(PBUF_RAW, tmplen * 4, PBUF_RAM);
  368. if (p)
  369. {
  370. uint32_t *data = (uint32_t *)p->payload;
  371. while (tmplen--)
  372. {
  373. *data++ = smc911x_reg_read(emac, LAN9118_RXDFIFOP);
  374. }
  375. }
  376. if (status & LAN9118_RXS_ES)
  377. {
  378. rt_kprintf(DRIVERNAME ": dropped bad packet. Status: 0x%08x\n", status);
  379. }
  380. }
  381. return p;
  382. }
  383. #ifdef RT_USING_DEVICE_OPS
  384. const static struct rt_device_ops smc911x_emac_ops =
  385. {
  386. smc911x_emac_init,
  387. RT_NULL,
  388. RT_NULL,
  389. RT_NULL,
  390. RT_NULL,
  391. smc911x_emac_control
  392. };
  393. #endif
  394. int smc911x_emac_hw_init(void)
  395. {
  396. rt_memset(&_emac, 0x0, sizeof(_emac));
  397. _emac.iobase = VEXPRESS_ETH_BASE;
  398. #ifdef RT_USING_SMART
  399. _emac.iobase = (uint32_t)rt_ioremap((void*)VEXPRESS_ETH_BASE, 0x1000);
  400. #endif
  401. _emac.irqno = IRQ_VEXPRESS_A9_ETH;
  402. if (smc911x_detect_chip(&_emac))
  403. {
  404. rt_kprintf("no smc911x network interface found!\n");
  405. return -1;
  406. }
  407. /* set INT CFG */
  408. smc911x_reg_write(&_emac, LAN9118_IRQ_CFG, LAN9118_IRQ_CFG_IRQ_POL | LAN9118_IRQ_CFG_IRQ_TYPE);
  409. /* test MAC address */
  410. _emac.enetaddr[0] = AUTOMAC0;
  411. _emac.enetaddr[1] = AUTOMAC1;
  412. _emac.enetaddr[2] = AUTOMAC2;
  413. _emac.enetaddr[3] = AUTOMAC3;
  414. _emac.enetaddr[4] = AUTOMAC4;
  415. _emac.enetaddr[5] = AUTOMAC5;
  416. #ifdef RT_USING_DEVICE_OPS
  417. _emac.parent.parent.ops = &smc911x_emac_ops;
  418. #else
  419. _emac.parent.parent.init = smc911x_emac_init;
  420. _emac.parent.parent.open = RT_NULL;
  421. _emac.parent.parent.close = RT_NULL;
  422. _emac.parent.parent.read = RT_NULL;
  423. _emac.parent.parent.write = RT_NULL;
  424. _emac.parent.parent.control = smc911x_emac_control;
  425. #endif
  426. _emac.parent.parent.user_data = RT_NULL;
  427. _emac.parent.eth_rx = smc911x_emac_rx;
  428. _emac.parent.eth_tx = smc911x_emac_tx;
  429. /* register ETH device */
  430. eth_device_init(&(_emac.parent), "e0");
  431. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  432. {
  433. int retval;
  434. struct mii_dev *mdiodev = mdio_alloc();
  435. if (!mdiodev)
  436. return -ENOMEM;
  437. strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
  438. mdiodev->read = smc911x_miiphy_read;
  439. mdiodev->write = smc911x_miiphy_write;
  440. retval = mdio_register(mdiodev);
  441. if (retval < 0)
  442. return retval;
  443. }
  444. #endif
  445. eth_device_linkchange(&_emac.parent, RT_TRUE);
  446. return 0;
  447. }
  448. INIT_APP_EXPORT(smc911x_emac_hw_init);