drv_gpio.c 1.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869
  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2021-01-28 flybreak first version
  9. */
  10. #include "drv_gpio.h"
  11. #include <hardware/gpio.h>
  12. #include <hardware/platform_defs.h>
  13. static void pico_pin_mode(struct rt_device *dev, rt_base_t pin, rt_uint8_t mode)
  14. {
  15. RT_ASSERT((0 <= pin) && (pin < NUM_BANK0_GPIOS));
  16. gpio_init(pin);
  17. switch (mode)
  18. {
  19. case PIN_MODE_OUTPUT:
  20. gpio_set_dir(pin, GPIO_OUT);
  21. break;
  22. case PIN_MODE_INPUT:
  23. gpio_set_dir(pin, GPIO_IN);
  24. break;
  25. case PIN_MODE_INPUT_PULLUP:
  26. gpio_pull_up(pin);
  27. break;
  28. case PIN_MODE_INPUT_PULLDOWN:
  29. gpio_pull_down(pin);
  30. break;
  31. case PIN_MODE_OUTPUT_OD:
  32. gpio_disable_pulls(pin);
  33. break;
  34. }
  35. }
  36. static void pico_pin_write(struct rt_device *dev, rt_base_t pin, rt_uint8_t value)
  37. {
  38. RT_ASSERT((0 <= pin) && (pin < NUM_BANK0_GPIOS));
  39. gpio_put(pin, value);
  40. }
  41. static rt_ssize_t pico_pin_read(struct rt_device *device, rt_base_t pin)
  42. {
  43. RT_ASSERT((0 <= pin) && (pin < NUM_BANK0_GPIOS));
  44. return (gpio_get(pin)? PIN_HIGH : PIN_LOW);
  45. }
  46. static const struct rt_pin_ops ops =
  47. {
  48. pico_pin_mode,
  49. pico_pin_write,
  50. pico_pin_read,
  51. RT_NULL,
  52. RT_NULL,
  53. RT_NULL,
  54. RT_NULL,
  55. };
  56. int rt_hw_gpio_init(void)
  57. {
  58. rt_device_pin_register("gpio", &ops, RT_NULL);
  59. return 0;
  60. }
  61. INIT_DEVICE_EXPORT(rt_hw_gpio_init);