mailbox-pic.c 6.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292
  1. /*
  2. * Copyright (c) 2006-2023, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2023-09-23 GuEe-GUI first version
  9. */
  10. #include <rtthread.h>
  11. #include <rtdevice.h>
  12. #define DBG_TAG "mailbox.pic"
  13. #define DBG_LVL DBG_INFO
  14. #include <rtdbg.h>
  15. /*
  16. * RT-Thread PIC Mailbox device driver
  17. *
  18. * The mailbox device(s) may be instantiated in one of three equivalent way:
  19. *
  20. * Device Tree node, eg.:
  21. *
  22. * interrupt-controller@0 {
  23. * interrupt-controller;
  24. * #interrupt-cells = <1>;
  25. * };
  26. *
  27. * pic_mailbox@10000 {
  28. * compatible = "rt-thread,pic-mailbox";
  29. * reg = <0x10000 0x100>;
  30. * position = <0>;
  31. * interrupts = <34>;
  32. * peer-interrupts = <35>;
  33. * uid = <0>;
  34. * #mbox-cells = <1>;
  35. * };
  36. */
  37. #define MAILBOX_IMASK 0x00
  38. #define MAILBOX_ISTATE 0x04
  39. #define MAILBOX_MSG(n) (0x08 + (n) * 4)
  40. struct pic_mbox
  41. {
  42. struct rt_mbox_controller parent;
  43. void *regs;
  44. void *peer_regs;
  45. int position;
  46. int chans_nr;
  47. int irq;
  48. int peer_hwirq;
  49. struct rt_pic *pic;
  50. struct rt_spinlock lock;
  51. };
  52. #define raw_to_pic_mbox(raw) rt_container_of(raw, struct pic_mbox, parent)
  53. static rt_err_t pic_mbox_request(struct rt_mbox_chan *chan)
  54. {
  55. int index = chan - chan->ctrl->chans;
  56. struct pic_mbox *pic_mbox = raw_to_pic_mbox(chan->ctrl);
  57. HWREG32(pic_mbox->regs + MAILBOX_IMASK) &= ~RT_BIT(index);
  58. HWREG32(pic_mbox->regs + MAILBOX_ISTATE) = 0;
  59. return RT_EOK;
  60. }
  61. static void pic_mbox_release(struct rt_mbox_chan *chan)
  62. {
  63. int index = chan - chan->ctrl->chans;
  64. struct pic_mbox *pic_mbox = raw_to_pic_mbox(chan->ctrl);
  65. HWREG32(pic_mbox->regs + MAILBOX_IMASK) |= RT_BIT(index);
  66. }
  67. static rt_err_t pic_mbox_send(struct rt_mbox_chan *chan, const void *data)
  68. {
  69. rt_ubase_t level;
  70. int index = chan - chan->ctrl->chans;
  71. struct pic_mbox *pic_mbox = raw_to_pic_mbox(chan->ctrl);
  72. while (HWREG32(pic_mbox->peer_regs + MAILBOX_ISTATE) & RT_BIT(index))
  73. {
  74. rt_thread_yield();
  75. }
  76. if (HWREG32(pic_mbox->peer_regs + MAILBOX_IMASK) & RT_BIT(index))
  77. {
  78. return -RT_ERROR;
  79. }
  80. level = rt_spin_lock_irqsave(&pic_mbox->lock);
  81. HWREG32(pic_mbox->regs + MAILBOX_MSG(index)) = *(rt_uint32_t *)data;
  82. HWREG32(pic_mbox->peer_regs + MAILBOX_ISTATE) |= RT_BIT(index);
  83. rt_hw_wmb();
  84. rt_pic_irq_set_state_raw(pic_mbox->pic, pic_mbox->peer_hwirq,
  85. RT_IRQ_STATE_PENDING, RT_TRUE);
  86. rt_spin_unlock_irqrestore(&pic_mbox->lock, level);
  87. return RT_EOK;
  88. }
  89. static const struct rt_mbox_controller_ops pic_mbox_ops =
  90. {
  91. .request = pic_mbox_request,
  92. .release = pic_mbox_release,
  93. .send = pic_mbox_send,
  94. };
  95. static void pic_mbox_isr(int irqno, void *param)
  96. {
  97. rt_uint32_t isr;
  98. struct pic_mbox *pic_mbox = param;
  99. isr = HWREG32(pic_mbox->regs + MAILBOX_ISTATE);
  100. for (int idx = 0; idx < 32; ++idx)
  101. {
  102. rt_uint32_t msg;
  103. if (!(RT_BIT(idx) & isr))
  104. {
  105. continue;
  106. }
  107. rt_hw_rmb();
  108. msg = HWREG32(pic_mbox->peer_regs + MAILBOX_MSG(idx));
  109. rt_mbox_recv(&pic_mbox->parent.chans[idx], &msg);
  110. }
  111. HWREG32(pic_mbox->regs + MAILBOX_ISTATE) &= ~isr;
  112. }
  113. static void pic_mbox_free_resource(struct pic_mbox *pic_mbox)
  114. {
  115. if (pic_mbox->regs && pic_mbox->peer_regs)
  116. {
  117. if (pic_mbox->peer_regs > pic_mbox->regs)
  118. {
  119. rt_iounmap(pic_mbox->regs);
  120. }
  121. else
  122. {
  123. rt_iounmap(pic_mbox->peer_regs);
  124. }
  125. }
  126. rt_free(pic_mbox);
  127. }
  128. static rt_err_t pic_mbox_probe(struct rt_platform_device *pdev)
  129. {
  130. rt_err_t err;
  131. rt_uint64_t size;
  132. rt_uint32_t value;
  133. char dev_name[RT_NAME_MAX];
  134. struct rt_ofw_node *pic_np;
  135. struct rt_device *dev = &pdev->parent;
  136. struct pic_mbox *pic_mbox = rt_calloc(1, sizeof(*pic_mbox));
  137. if (!pic_mbox)
  138. {
  139. return -RT_ENOMEM;
  140. }
  141. if ((err = rt_dm_dev_get_address(dev, 0, RT_NULL, &size)))
  142. {
  143. goto _fail;
  144. }
  145. if ((err = rt_dm_dev_prop_read_u32(dev, "position", &value)))
  146. {
  147. goto _fail;
  148. }
  149. if (!value)
  150. {
  151. pic_mbox->regs = rt_dm_dev_iomap(dev, 0);
  152. if (!pic_mbox->regs)
  153. {
  154. goto _fail;
  155. }
  156. pic_mbox->peer_regs = pic_mbox->regs + size / 2;
  157. /* Init by the captain */
  158. HWREG32(pic_mbox->regs + MAILBOX_IMASK) = 0xffffffff;
  159. HWREG32(pic_mbox->regs + MAILBOX_ISTATE) = 0;
  160. HWREG32(pic_mbox->peer_regs + MAILBOX_IMASK) = 0xffffffff;
  161. HWREG32(pic_mbox->peer_regs + MAILBOX_ISTATE) = 0;
  162. }
  163. else
  164. {
  165. pic_mbox->peer_regs = rt_dm_dev_iomap(dev, 0);
  166. if (!pic_mbox->peer_regs)
  167. {
  168. goto _fail;
  169. }
  170. pic_mbox->regs = pic_mbox->peer_regs + size / 2;
  171. }
  172. pic_mbox->irq = rt_dm_dev_get_irq(dev, 0);
  173. if (pic_mbox->irq < 0)
  174. {
  175. err = pic_mbox->irq;
  176. goto _fail;
  177. }
  178. if ((err = rt_dm_dev_prop_read_u32(dev, "peer-interrupts", &value)))
  179. {
  180. goto _fail;
  181. }
  182. pic_mbox->peer_hwirq = value;
  183. if ((err = rt_dm_dev_prop_read_u32(dev, "uid", &value)))
  184. {
  185. goto _fail;
  186. }
  187. if (!(pic_np = rt_ofw_find_irq_parent(dev->ofw_node, RT_NULL)))
  188. {
  189. goto _fail;
  190. }
  191. pic_mbox->pic = rt_ofw_data(pic_np);
  192. rt_ofw_node_put(pic_np);
  193. rt_spin_lock_init(&pic_mbox->lock);
  194. pic_mbox->parent.dev = dev;
  195. pic_mbox->parent.num_chans = 32;
  196. pic_mbox->parent.ops = &pic_mbox_ops;
  197. if ((err = rt_mbox_controller_register(&pic_mbox->parent)))
  198. {
  199. goto _fail;
  200. }
  201. rt_snprintf(dev_name, sizeof(dev_name), "pic-mbox%d", value);
  202. rt_hw_interrupt_install(pic_mbox->irq, pic_mbox_isr, pic_mbox, dev_name);
  203. rt_hw_interrupt_umask(pic_mbox->irq);
  204. return RT_EOK;
  205. _fail:
  206. pic_mbox_free_resource(pic_mbox);
  207. return err;
  208. }
  209. static rt_err_t pic_mbox_remove(struct rt_platform_device *pdev)
  210. {
  211. struct pic_mbox *pic_mbox = pdev->parent.user_data;
  212. rt_pic_detach_irq(pic_mbox->irq, pic_mbox);
  213. rt_mbox_controller_unregister(&pic_mbox->parent);
  214. pic_mbox_free_resource(pic_mbox);
  215. return RT_EOK;
  216. }
  217. static const struct rt_ofw_node_id pic_mbox_ofw_ids[] =
  218. {
  219. { .compatible = "rt-thread,pic-mailbox" },
  220. { /* sentinel */ }
  221. };
  222. static struct rt_platform_driver pic_mbox_driver =
  223. {
  224. .name = "mailbox-pic",
  225. .ids = pic_mbox_ofw_ids,
  226. .probe = pic_mbox_probe,
  227. .remove = pic_mbox_remove,
  228. };
  229. RT_PLATFORM_DRIVER_EXPORT(pic_mbox_driver);