usb_hc_ehci.c 44 KB

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  1. /*
  2. * Copyright (c) 2022, sakumisu
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. #include "usb_hc_ehci.h"
  7. #ifdef CONFIG_USB_EHCI_WITH_OHCI
  8. #include "usb_hc_ohci.h"
  9. #endif
  10. #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
  11. #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
  12. #define EHCI_TUNE_RL_TT 0
  13. #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
  14. #define EHCI_TUNE_MULT_TT 1
  15. struct ehci_hcd g_ehci_hcd[CONFIG_USBHOST_MAX_BUS];
  16. USB_NOCACHE_RAM_SECTION struct ehci_qh_hw ehci_qh_pool[CONFIG_USBHOST_MAX_BUS][CONFIG_USB_EHCI_QH_NUM];
  17. USB_NOCACHE_RAM_SECTION struct ehci_qtd_hw ehci_qtd_pool[CONFIG_USBHOST_MAX_BUS][CONFIG_USB_EHCI_QTD_NUM];
  18. /* The head of the asynchronous queue */
  19. USB_NOCACHE_RAM_SECTION struct ehci_qh_hw g_async_qh_head[CONFIG_USBHOST_MAX_BUS];
  20. /* The head of the periodic queue */
  21. USB_NOCACHE_RAM_SECTION struct ehci_qh_hw g_periodic_qh_head[CONFIG_USBHOST_MAX_BUS];
  22. /* The frame list */
  23. USB_NOCACHE_RAM_SECTION uint32_t g_framelist[CONFIG_USBHOST_MAX_BUS][USB_ALIGN_UP(CONFIG_USB_EHCI_FRAME_LIST_SIZE, 1024)] __attribute__((aligned(4096)));
  24. static struct ehci_qtd_hw *ehci_qtd_alloc(struct usbh_bus *bus)
  25. {
  26. struct ehci_qtd_hw *qtd;
  27. size_t flags;
  28. flags = usb_osal_enter_critical_section();
  29. for (uint32_t i = 0; i < CONFIG_USB_EHCI_QTD_NUM; i++) {
  30. qtd = &ehci_qtd_pool[bus->hcd.hcd_id][i];
  31. if (!qtd->inuse) {
  32. qtd->inuse = true;
  33. usb_osal_leave_critical_section(flags);
  34. memset(&qtd->hw, 0, sizeof(struct ehci_qtd));
  35. qtd->hw.next_qtd = QTD_LIST_END;
  36. qtd->hw.alt_next_qtd = QTD_LIST_END;
  37. qtd->hw.token = QTD_TOKEN_STATUS_HALTED;
  38. qtd->urb = NULL;
  39. qtd->bufaddr = 0;
  40. qtd->length = 0;
  41. return qtd;
  42. }
  43. }
  44. usb_osal_leave_critical_section(flags);
  45. return NULL;
  46. }
  47. static void ehci_qtd_free(struct usbh_bus *bus, struct ehci_qtd_hw *qtd)
  48. {
  49. size_t flags;
  50. (void)bus;
  51. flags = usb_osal_enter_critical_section();
  52. qtd->inuse = false;
  53. qtd->urb = NULL;
  54. usb_osal_leave_critical_section(flags);
  55. }
  56. static struct ehci_qh_hw *ehci_qh_alloc(struct usbh_bus *bus)
  57. {
  58. struct ehci_qh_hw *qh;
  59. size_t flags;
  60. flags = usb_osal_enter_critical_section();
  61. for (uint32_t i = 0; i < CONFIG_USB_EHCI_QH_NUM; i++) {
  62. qh = &ehci_qh_pool[bus->hcd.hcd_id][i];
  63. if (!qh->inuse) {
  64. qh->inuse = true;
  65. usb_osal_leave_critical_section(flags);
  66. memset(&qh->hw, 0, sizeof(struct ehci_qh));
  67. qh->hw.hlp = QTD_LIST_END;
  68. qh->hw.overlay.next_qtd = QTD_LIST_END;
  69. qh->hw.overlay.alt_next_qtd = QTD_LIST_END;
  70. qh->urb = NULL;
  71. qh->first_qtd = QTD_LIST_END;
  72. qh->remove_in_iaad = 0;
  73. return qh;
  74. }
  75. }
  76. usb_osal_leave_critical_section(flags);
  77. return NULL;
  78. }
  79. static void ehci_qh_free(struct usbh_bus *bus, struct ehci_qh_hw *qh)
  80. {
  81. struct ehci_qtd_hw *qtd;
  82. size_t flags;
  83. flags = usb_osal_enter_critical_section();
  84. if (qh->urb) {
  85. qh->urb->hcpriv = NULL;
  86. qh->urb = NULL;
  87. }
  88. qtd = EHCI_ADDR2QTD(qh->first_qtd);
  89. while (qtd) {
  90. ehci_qtd_free(bus, qtd);
  91. qtd = EHCI_ADDR2QTD(qtd->hw.next_qtd);
  92. }
  93. qh->inuse = false;
  94. qh->first_qtd = QTD_LIST_END;
  95. usb_osal_leave_critical_section(flags);
  96. }
  97. #if defined(CONFIG_USB_EHCI_DESC_DCACHE_ENABLE)
  98. static inline void usb_ehci_qh_qtd_flush(struct ehci_qh_hw *qh)
  99. {
  100. struct ehci_qtd_hw *qtd;
  101. qtd = EHCI_ADDR2QTD(qh->first_qtd);
  102. while (qtd) {
  103. usb_dcache_clean((uintptr_t)&qtd->hw, CONFIG_USB_EHCI_ALIGN_SIZE);
  104. qtd = EHCI_ADDR2QTD(qtd->hw.next_qtd);
  105. }
  106. usb_dcache_clean((uintptr_t)&qh->hw, CONFIG_USB_EHCI_ALIGN_SIZE);
  107. }
  108. #else
  109. #define usb_ehci_qh_qtd_flush(qh)
  110. #endif
  111. static inline void ehci_qh_add_head(struct ehci_qh_hw *head, struct ehci_qh_hw *n)
  112. {
  113. n->hw.hlp = head->hw.hlp;
  114. usb_ehci_qh_qtd_flush(n);
  115. usb_dcache_flush((uintptr_t)n->urb->transfer_buffer, USB_ALIGN_UP(n->urb->transfer_buffer_length, CONFIG_USB_ALIGN_SIZE));
  116. head->hw.hlp = QH_HLP_QH(n);
  117. #if defined(CONFIG_USB_EHCI_DESC_DCACHE_ENABLE)
  118. usb_dcache_clean((uintptr_t)&head->hw, CONFIG_USB_EHCI_ALIGN_SIZE);
  119. #endif
  120. }
  121. static inline void ehci_qh_remove(struct ehci_qh_hw *head, struct ehci_qh_hw *n)
  122. {
  123. struct ehci_qh_hw *tmp = head;
  124. while (EHCI_ADDR2QH(tmp->hw.hlp) && EHCI_ADDR2QH(tmp->hw.hlp) != n) {
  125. tmp = EHCI_ADDR2QH(tmp->hw.hlp);
  126. }
  127. if (tmp) {
  128. tmp->hw.hlp = n->hw.hlp;
  129. #if defined(CONFIG_USB_EHCI_DESC_DCACHE_ENABLE)
  130. usb_dcache_clean((uintptr_t)&tmp->hw, CONFIG_USB_EHCI_ALIGN_SIZE);
  131. #endif
  132. }
  133. }
  134. static int ehci_caculate_smask(int binterval)
  135. {
  136. int order, interval;
  137. interval = 1;
  138. while (binterval > 1) {
  139. interval *= 2;
  140. binterval--;
  141. }
  142. if (interval < 2) /* interval 1 */
  143. return 0xFF;
  144. if (interval < 4) /* interval 2 */
  145. return 0x55;
  146. if (interval < 8) /* interval 4 */
  147. return 0x22;
  148. for (order = 0; (interval > 1); order++) {
  149. interval >>= 1;
  150. }
  151. return (0x1 << (order % 8));
  152. }
  153. static void ehci_qh_fill(struct ehci_qh_hw *qh,
  154. uint8_t dev_addr,
  155. uint8_t ep_addr,
  156. uint8_t ep_type,
  157. uint16_t ep_mps,
  158. uint8_t ep_mult,
  159. uint8_t ep_interval,
  160. uint8_t speed,
  161. uint8_t hubaddr,
  162. uint8_t hubport)
  163. {
  164. uint32_t epchar = 0;
  165. uint32_t epcap = 0;
  166. /* QH endpoint characteristics:
  167. *
  168. * FIELD DESCRIPTION
  169. * -------- -------------------------------
  170. * DEVADDR Device address
  171. * I Inactivate on Next Transaction
  172. * ENDPT Endpoint number
  173. * EPS Endpoint speed
  174. * DTC Data toggle control
  175. * MAXPKT Max packet size
  176. * C Control endpoint
  177. * RL NAK count reloaded
  178. */
  179. /* QH endpoint capabilities
  180. *
  181. * FIELD DESCRIPTION
  182. * -------- -------------------------------
  183. * SSMASK Interrupt Schedule Mask
  184. * SCMASK Split Completion Mask
  185. * HUBADDR Hub Address
  186. * PORT Port number
  187. * MULT High band width multiplier
  188. */
  189. epchar |= ((ep_addr & 0xf) << QH_EPCHAR_ENDPT_SHIFT);
  190. epchar |= (dev_addr << QH_EPCHAR_DEVADDR_SHIFT);
  191. epchar |= (ep_mps << QH_EPCHAR_MAXPKT_SHIFT);
  192. if (ep_type == USB_ENDPOINT_TYPE_CONTROL) {
  193. epchar |= QH_EPCHAR_DTC; /* toggle from qtd */
  194. }
  195. switch (speed) {
  196. case USB_SPEED_LOW:
  197. epchar |= QH_EPCHAR_EPS_LOW;
  198. __attribute__((fallthrough));
  199. case USB_SPEED_FULL:
  200. if (ep_type == USB_ENDPOINT_TYPE_CONTROL) {
  201. epchar |= QH_EPCHAR_C; /* for TT */
  202. }
  203. if (ep_type != USB_ENDPOINT_TYPE_INTERRUPT) {
  204. epchar |= (EHCI_TUNE_RL_TT << QH_EPCHAR_RL_SHIFT);
  205. }
  206. epcap |= QH_EPCAPS_MULT(EHCI_TUNE_MULT_TT);
  207. epcap |= QH_EPCAPS_HUBADDR(hubaddr);
  208. epcap |= QH_EPCAPS_PORT(hubport);
  209. if (ep_type == USB_ENDPOINT_TYPE_INTERRUPT) {
  210. epcap |= QH_EPCAPS_SSMASK(2);
  211. epcap |= QH_EPCAPS_SCMASK(0x78);
  212. }
  213. break;
  214. case USB_SPEED_HIGH:
  215. epchar |= QH_EPCHAR_EPS_HIGH;
  216. if (ep_type == USB_ENDPOINT_TYPE_CONTROL) {
  217. epchar |= (EHCI_TUNE_RL_HS << QH_EPCHAR_RL_SHIFT);
  218. epcap |= QH_EPCAPS_MULT(EHCI_TUNE_MULT_HS);
  219. } else if (ep_type == USB_ENDPOINT_TYPE_BULK) {
  220. epcap |= QH_EPCAPS_MULT(EHCI_TUNE_MULT_HS);
  221. } else {
  222. /* only for interrupt ep */
  223. epcap |= QH_EPCAPS_MULT(ep_mult);
  224. epcap |= ehci_caculate_smask(ep_interval);
  225. }
  226. break;
  227. default:
  228. break;
  229. }
  230. qh->hw.epchar = epchar;
  231. qh->hw.epcap = epcap;
  232. }
  233. static void ehci_qtd_bpl_fill(struct ehci_qtd_hw *qtd, uint32_t bufaddr, size_t buflen)
  234. {
  235. uint32_t rest;
  236. qtd->hw.bpl[0] = bufaddr;
  237. rest = 0x1000 - (bufaddr & 0xfff);
  238. if (buflen < rest) {
  239. rest = buflen;
  240. } else {
  241. bufaddr += 0x1000;
  242. bufaddr &= ~0x0fff;
  243. for (int i = 1; rest < buflen && i < 5; i++) {
  244. qtd->hw.bpl[i] = bufaddr;
  245. bufaddr += 0x1000;
  246. if ((rest + 0x1000) < buflen) {
  247. rest += 0x1000;
  248. } else {
  249. rest = buflen;
  250. }
  251. }
  252. }
  253. }
  254. static void ehci_qtd_fill(struct ehci_qtd_hw *qtd, uint32_t bufaddr, size_t buflen, uint32_t token)
  255. {
  256. /* qTD token
  257. *
  258. * FIELD DESCRIPTION
  259. * -------- -------------------------------
  260. * STATUS Status
  261. * PID PID Code
  262. * CERR Error Counter
  263. * CPAGE Current Page
  264. * IOC Interrupt on complete
  265. * NBYTES Total Bytes to Transfer
  266. * TOGGLE Data Toggle
  267. */
  268. qtd->hw.token = token;
  269. ehci_qtd_bpl_fill(qtd, usb_phyaddr2ramaddr(bufaddr), buflen);
  270. qtd->bufaddr = bufaddr;
  271. qtd->length = buflen;
  272. }
  273. static struct ehci_qh_hw *ehci_control_urb_init(struct usbh_bus *bus, struct usbh_urb *urb, struct usb_setup_packet *setup, uint8_t *buffer, uint32_t buflen)
  274. {
  275. struct ehci_qh_hw *qh = NULL;
  276. struct ehci_qtd_hw *qtd_setup = NULL;
  277. struct ehci_qtd_hw *qtd_data = NULL;
  278. struct ehci_qtd_hw *qtd_status = NULL;
  279. uint32_t token;
  280. size_t flags;
  281. qh = ehci_qh_alloc(bus);
  282. if (qh == NULL) {
  283. return NULL;
  284. }
  285. qtd_setup = ehci_qtd_alloc(bus);
  286. qtd_status = ehci_qtd_alloc(bus);
  287. USB_ASSERT_MSG(qtd_setup && qtd_status, "ctrl qtd alloc failed");
  288. ehci_qh_fill(qh,
  289. urb->hport->dev_addr,
  290. urb->ep->bEndpointAddress,
  291. USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes),
  292. USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize),
  293. 0,
  294. 0,
  295. urb->hport->speed,
  296. urb->hport->parent->hub_addr,
  297. urb->hport->port);
  298. /* fill setup qtd */
  299. token = QTD_TOKEN_STATUS_ACTIVE |
  300. QTD_TOKEN_PID_SETUP |
  301. ((uint32_t)EHCI_TUNE_CERR << QTD_TOKEN_CERR_SHIFT) |
  302. ((uint32_t)8 << QTD_TOKEN_NBYTES_SHIFT);
  303. ehci_qtd_fill(qtd_setup, (uintptr_t)setup, 8, token);
  304. qtd_setup->urb = urb;
  305. /* fill data qtd */
  306. if (setup->wLength > 0) {
  307. qtd_data = ehci_qtd_alloc(bus);
  308. USB_ASSERT_MSG(qtd_data, "ctrl qtd alloc failed");
  309. if ((setup->bmRequestType & 0x80) == 0x80) {
  310. token = QTD_TOKEN_PID_IN;
  311. } else {
  312. token = QTD_TOKEN_PID_OUT;
  313. }
  314. token |= QTD_TOKEN_STATUS_ACTIVE |
  315. QTD_TOKEN_PID_OUT |
  316. QTD_TOKEN_TOGGLE |
  317. ((uint32_t)EHCI_TUNE_CERR << QTD_TOKEN_CERR_SHIFT) |
  318. ((uint32_t)buflen << QTD_TOKEN_NBYTES_SHIFT);
  319. ehci_qtd_fill(qtd_data, (uintptr_t)buffer, buflen, token);
  320. qtd_data->urb = urb;
  321. qtd_setup->hw.next_qtd = EHCI_PTR2ADDR(qtd_data);
  322. qtd_data->hw.next_qtd = EHCI_PTR2ADDR(qtd_status);
  323. } else {
  324. qtd_setup->hw.next_qtd = EHCI_PTR2ADDR(qtd_status);
  325. }
  326. /* fill status qtd */
  327. if ((setup->bmRequestType & 0x80) == 0x80) {
  328. token = QTD_TOKEN_PID_OUT;
  329. } else {
  330. token = QTD_TOKEN_PID_IN;
  331. }
  332. token |= QTD_TOKEN_STATUS_ACTIVE |
  333. QTD_TOKEN_TOGGLE |
  334. QTD_TOKEN_IOC |
  335. ((uint32_t)EHCI_TUNE_CERR << QTD_TOKEN_CERR_SHIFT) |
  336. ((uint32_t)0 << QTD_TOKEN_NBYTES_SHIFT);
  337. ehci_qtd_fill(qtd_status, 0, 0, token);
  338. qtd_status->urb = urb;
  339. qtd_status->hw.next_qtd = QTD_LIST_END;
  340. /* update qh first qtd */
  341. qh->hw.curr_qtd = EHCI_PTR2ADDR(qtd_setup);
  342. qh->hw.overlay.next_qtd = EHCI_PTR2ADDR(qtd_setup);
  343. /* record qh first qtd */
  344. qh->first_qtd = EHCI_PTR2ADDR(qtd_setup);
  345. flags = usb_osal_enter_critical_section();
  346. qh->urb = urb;
  347. urb->hcpriv = qh;
  348. /* add qh into async list */
  349. ehci_qh_add_head(&g_async_qh_head[bus->hcd.hcd_id], qh);
  350. EHCI_HCOR->usbcmd |= EHCI_USBCMD_ASEN;
  351. usb_osal_leave_critical_section(flags);
  352. return qh;
  353. }
  354. static struct ehci_qh_hw *ehci_bulk_urb_init(struct usbh_bus *bus, struct usbh_urb *urb, uint8_t *buffer, uint32_t buflen)
  355. {
  356. struct ehci_qh_hw *qh = NULL;
  357. struct ehci_qtd_hw *qtd = NULL;
  358. struct ehci_qtd_hw *first_qtd = NULL;
  359. struct ehci_qtd_hw *prev_qtd = NULL;
  360. uint32_t xfer_len = 0;
  361. uint32_t token;
  362. size_t flags;
  363. qh = ehci_qh_alloc(bus);
  364. if (qh == NULL) {
  365. return NULL;
  366. }
  367. ehci_qh_fill(qh,
  368. urb->hport->dev_addr,
  369. urb->ep->bEndpointAddress,
  370. USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes),
  371. USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize),
  372. 0,
  373. 0,
  374. urb->hport->speed,
  375. urb->hport->parent->hub_addr,
  376. urb->hport->port);
  377. while (1) {
  378. qtd = ehci_qtd_alloc(bus);
  379. USB_ASSERT_MSG(qtd, "bulk qtd alloc failed");
  380. if (buflen > 0x4000) {
  381. xfer_len = 0x4000;
  382. buflen -= 0x4000;
  383. } else {
  384. xfer_len = buflen;
  385. buflen = 0;
  386. }
  387. if (urb->ep->bEndpointAddress & 0x80) {
  388. token = QTD_TOKEN_PID_IN;
  389. } else {
  390. token = QTD_TOKEN_PID_OUT;
  391. }
  392. token |= QTD_TOKEN_STATUS_ACTIVE |
  393. ((uint32_t)EHCI_TUNE_CERR << QTD_TOKEN_CERR_SHIFT) |
  394. ((uint32_t)xfer_len << QTD_TOKEN_NBYTES_SHIFT);
  395. if (buflen == 0) {
  396. token |= QTD_TOKEN_IOC;
  397. }
  398. ehci_qtd_fill(qtd, (uintptr_t)buffer, xfer_len, token);
  399. qtd->urb = urb;
  400. qtd->hw.next_qtd = QTD_LIST_END;
  401. buffer += xfer_len;
  402. if (prev_qtd) {
  403. prev_qtd->hw.next_qtd = EHCI_PTR2ADDR(qtd);
  404. } else {
  405. first_qtd = qtd;
  406. }
  407. prev_qtd = qtd;
  408. if (buflen == 0) {
  409. break;
  410. }
  411. }
  412. /* update qh first qtd */
  413. qh->hw.curr_qtd = EHCI_PTR2ADDR(first_qtd);
  414. qh->hw.overlay.next_qtd = EHCI_PTR2ADDR(first_qtd);
  415. /* update data toggle */
  416. if (urb->data_toggle) {
  417. qh->hw.overlay.token = QTD_TOKEN_TOGGLE;
  418. } else {
  419. qh->hw.overlay.token = 0;
  420. }
  421. /* record qh first qtd */
  422. qh->first_qtd = EHCI_PTR2ADDR(first_qtd);
  423. flags = usb_osal_enter_critical_section();
  424. qh->urb = urb;
  425. urb->hcpriv = qh;
  426. /* add qh into async list */
  427. ehci_qh_add_head(&g_async_qh_head[bus->hcd.hcd_id], qh);
  428. EHCI_HCOR->usbcmd |= EHCI_USBCMD_ASEN;
  429. usb_osal_leave_critical_section(flags);
  430. return qh;
  431. }
  432. static struct ehci_qh_hw *ehci_intr_urb_init(struct usbh_bus *bus, struct usbh_urb *urb, uint8_t *buffer, uint32_t buflen)
  433. {
  434. struct ehci_qh_hw *qh = NULL;
  435. struct ehci_qtd_hw *qtd = NULL;
  436. struct ehci_qtd_hw *first_qtd = NULL;
  437. struct ehci_qtd_hw *prev_qtd = NULL;
  438. uint32_t xfer_len = 0;
  439. uint32_t token;
  440. size_t flags;
  441. qh = ehci_qh_alloc(bus);
  442. if (qh == NULL) {
  443. return NULL;
  444. }
  445. ehci_qh_fill(qh,
  446. urb->hport->dev_addr,
  447. urb->ep->bEndpointAddress,
  448. USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes),
  449. USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize),
  450. USB_GET_MULT(urb->ep->wMaxPacketSize) + 1,
  451. urb->ep->bInterval,
  452. urb->hport->speed,
  453. urb->hport->parent->hub_addr,
  454. urb->hport->port);
  455. while (1) {
  456. qtd = ehci_qtd_alloc(bus);
  457. USB_ASSERT_MSG(qtd, "intr qtd alloc failed");
  458. if (buflen > 0x4000) {
  459. xfer_len = 0x4000;
  460. buflen -= 0x4000;
  461. } else {
  462. xfer_len = buflen;
  463. buflen = 0;
  464. }
  465. if (urb->ep->bEndpointAddress & 0x80) {
  466. token = QTD_TOKEN_PID_IN;
  467. } else {
  468. token = QTD_TOKEN_PID_OUT;
  469. }
  470. token |= QTD_TOKEN_STATUS_ACTIVE |
  471. ((uint32_t)EHCI_TUNE_CERR << QTD_TOKEN_CERR_SHIFT) |
  472. ((uint32_t)xfer_len << QTD_TOKEN_NBYTES_SHIFT);
  473. if (buflen == 0) {
  474. token |= QTD_TOKEN_IOC;
  475. }
  476. ehci_qtd_fill(qtd, (uintptr_t)buffer, xfer_len, token);
  477. qtd->urb = urb;
  478. qtd->hw.next_qtd = QTD_LIST_END;
  479. buffer += xfer_len;
  480. if (prev_qtd) {
  481. prev_qtd->hw.next_qtd = EHCI_PTR2ADDR(qtd);
  482. } else {
  483. first_qtd = qtd;
  484. }
  485. prev_qtd = qtd;
  486. if (buflen == 0) {
  487. break;
  488. }
  489. }
  490. /* update qh first qtd */
  491. qh->hw.curr_qtd = EHCI_PTR2ADDR(first_qtd);
  492. qh->hw.overlay.next_qtd = EHCI_PTR2ADDR(first_qtd);
  493. /* update data toggle */
  494. if (urb->data_toggle) {
  495. qh->hw.overlay.token = QTD_TOKEN_TOGGLE;
  496. } else {
  497. qh->hw.overlay.token = 0;
  498. }
  499. /* record qh first qtd */
  500. qh->first_qtd = EHCI_PTR2ADDR(first_qtd);
  501. flags = usb_osal_enter_critical_section();
  502. qh->urb = urb;
  503. urb->hcpriv = qh;
  504. /* add qh into periodic list */
  505. ehci_qh_add_head(&g_periodic_qh_head[bus->hcd.hcd_id], qh);
  506. EHCI_HCOR->usbcmd |= EHCI_USBCMD_PSEN;
  507. usb_osal_leave_critical_section(flags);
  508. return qh;
  509. }
  510. static void ehci_urb_waitup(struct usbh_bus *bus, struct usbh_urb *urb)
  511. {
  512. struct ehci_qh_hw *qh;
  513. qh = (struct ehci_qh_hw *)urb->hcpriv;
  514. qh->remove_in_iaad = 0;
  515. if (urb->timeout) {
  516. usb_osal_sem_give(qh->waitsem);
  517. } else {
  518. ehci_qh_free(bus, qh);
  519. }
  520. if (urb->complete) {
  521. if (urb->errorcode < 0) {
  522. urb->complete(urb->arg, urb->errorcode);
  523. } else {
  524. urb->complete(urb->arg, urb->actual_length);
  525. }
  526. }
  527. }
  528. static void ehci_qh_scan_qtds(struct usbh_bus *bus, struct ehci_qh_hw *qhead, struct ehci_qh_hw *qh)
  529. {
  530. struct ehci_qtd_hw *qtd;
  531. (void)bus;
  532. ehci_qh_remove(qhead, qh);
  533. qtd = EHCI_ADDR2QTD(qh->first_qtd);
  534. while (qtd) {
  535. qtd->urb->actual_length += (qtd->length - ((qtd->hw.token & QTD_TOKEN_NBYTES_MASK) >> QTD_TOKEN_NBYTES_SHIFT));
  536. qtd = EHCI_ADDR2QTD(qtd->hw.next_qtd);
  537. }
  538. }
  539. static void ehci_check_qh(struct usbh_bus *bus, struct ehci_qh_hw *qhead, struct ehci_qh_hw *qh)
  540. {
  541. struct usbh_urb *urb;
  542. struct ehci_qtd_hw *qtd;
  543. uint32_t token;
  544. qtd = EHCI_ADDR2QTD(qh->first_qtd);
  545. if (qtd == NULL) {
  546. return;
  547. }
  548. while (qtd) {
  549. #if defined(CONFIG_USB_EHCI_DESC_DCACHE_ENABLE)
  550. usb_dcache_invalidate((uintptr_t)&qtd->hw, CONFIG_USB_EHCI_ALIGN_SIZE);
  551. #endif
  552. token = qtd->hw.token;
  553. if (token & QTD_TOKEN_STATUS_ERRORS) {
  554. break;
  555. } else if (token & QTD_TOKEN_STATUS_ACTIVE) {
  556. return;
  557. }
  558. qtd = EHCI_ADDR2QTD(qtd->hw.next_qtd);
  559. }
  560. urb = qh->urb;
  561. if ((token & QTD_TOKEN_STATUS_ERRORS) == 0) {
  562. if (token & QTD_TOKEN_TOGGLE) {
  563. urb->data_toggle = true;
  564. } else {
  565. urb->data_toggle = false;
  566. }
  567. urb->errorcode = 0;
  568. } else {
  569. if (token & QTD_TOKEN_STATUS_BABBLE) {
  570. urb->errorcode = -USB_ERR_BABBLE;
  571. urb->data_toggle = 0;
  572. } else if (token & QTD_TOKEN_STATUS_HALTED) {
  573. urb->errorcode = -USB_ERR_STALL;
  574. urb->data_toggle = 0;
  575. } else if (token & (QTD_TOKEN_STATUS_DBERR | QTD_TOKEN_STATUS_XACTERR)) {
  576. urb->errorcode = -USB_ERR_IO;
  577. }
  578. }
  579. ehci_qh_scan_qtds(bus, qhead, qh);
  580. if (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_INTERRUPT) {
  581. ehci_urb_waitup(bus, urb);
  582. } else {
  583. qh->remove_in_iaad = 1;
  584. EHCI_HCOR->usbcmd |= EHCI_USBCMD_IAAD;
  585. }
  586. }
  587. static void ehci_kill_qh(struct usbh_bus *bus, struct ehci_qh_hw *qhead, struct ehci_qh_hw *qh)
  588. {
  589. (void)bus;
  590. ehci_qh_remove(qhead, qh);
  591. }
  592. static int usbh_reset_port(struct usbh_bus *bus, const uint8_t port)
  593. {
  594. volatile uint32_t timeout = 0;
  595. uint32_t regval;
  596. #if defined(CONFIG_USB_EHCI_HPMICRO) && CONFIG_USB_EHCI_HPMICRO
  597. if ((*(volatile uint32_t *)(bus->hcd.reg_base + 0x224) & 0xc0) == (2 << 6)) { /* Hardcode for hpm */
  598. EHCI_HCOR->portsc[port - 1] |= (1 << 29);
  599. } else {
  600. EHCI_HCOR->portsc[port - 1] &= ~(1 << 29);
  601. }
  602. #endif
  603. regval = EHCI_HCOR->portsc[port - 1];
  604. regval &= ~EHCI_PORTSC_PE;
  605. regval |= EHCI_PORTSC_RESET;
  606. EHCI_HCOR->portsc[port - 1] = regval;
  607. usb_osal_msleep(55);
  608. EHCI_HCOR->portsc[port - 1] &= ~EHCI_PORTSC_RESET;
  609. while ((EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_RESET) != 0) {
  610. usb_osal_msleep(1);
  611. timeout++;
  612. if (timeout > 100) {
  613. return -USB_ERR_TIMEOUT;
  614. }
  615. }
  616. return 0;
  617. }
  618. __WEAK void usb_hc_low_level_init(struct usbh_bus *bus)
  619. {
  620. (void)bus;
  621. }
  622. __WEAK void usb_hc_low_level2_init(struct usbh_bus *bus)
  623. {
  624. (void)bus;
  625. }
  626. __WEAK void usb_hc_low_level_deinit(struct usbh_bus *bus)
  627. {
  628. (void)bus;
  629. }
  630. int usb_hc_init(struct usbh_bus *bus)
  631. {
  632. struct ehci_qh_hw *qh;
  633. struct ehci_qtd_hw *qtd;
  634. volatile uint32_t timeout = 0;
  635. uint32_t regval;
  636. memset(&g_ehci_hcd[bus->hcd.hcd_id], 0, sizeof(struct ehci_hcd));
  637. memset(ehci_qh_pool[bus->hcd.hcd_id], 0, sizeof(struct ehci_qh_hw) * CONFIG_USB_EHCI_QH_NUM);
  638. memset(ehci_qtd_pool[bus->hcd.hcd_id], 0, sizeof(struct ehci_qtd_hw) * CONFIG_USB_EHCI_QTD_NUM);
  639. for (uint8_t index = 0; index < CONFIG_USB_EHCI_QH_NUM; index++) {
  640. qh = &ehci_qh_pool[bus->hcd.hcd_id][index];
  641. if ((uint32_t)&qh->hw % 32) {
  642. USB_LOG_ERR("struct ehci_qh_hw is not align 32\r\n");
  643. return -USB_ERR_INVAL;
  644. }
  645. }
  646. for (uint8_t index = 0; index < CONFIG_USB_EHCI_QTD_NUM; index++) {
  647. qtd = &ehci_qtd_pool[bus->hcd.hcd_id][index];
  648. if ((uint32_t)&qtd->hw % 32) {
  649. USB_LOG_ERR("struct ehci_qtd_hw is not align 32\r\n");
  650. return -USB_ERR_INVAL;
  651. }
  652. }
  653. for (uint8_t index = 0; index < CONFIG_USB_EHCI_QH_NUM; index++) {
  654. qh = &ehci_qh_pool[bus->hcd.hcd_id][index];
  655. qh->waitsem = usb_osal_sem_create(0);
  656. }
  657. memset(&g_async_qh_head[bus->hcd.hcd_id], 0, sizeof(struct ehci_qh_hw));
  658. g_async_qh_head[bus->hcd.hcd_id].hw.hlp = QH_HLP_QH(&g_async_qh_head[bus->hcd.hcd_id]);
  659. g_async_qh_head[bus->hcd.hcd_id].hw.epchar = QH_EPCHAR_H;
  660. g_async_qh_head[bus->hcd.hcd_id].hw.overlay.next_qtd = QTD_LIST_END;
  661. g_async_qh_head[bus->hcd.hcd_id].hw.overlay.alt_next_qtd = QTD_LIST_END;
  662. g_async_qh_head[bus->hcd.hcd_id].hw.overlay.token = QTD_TOKEN_STATUS_HALTED;
  663. g_async_qh_head[bus->hcd.hcd_id].first_qtd = QTD_LIST_END;
  664. memset(g_framelist[bus->hcd.hcd_id], 0, sizeof(uint32_t) * CONFIG_USB_EHCI_FRAME_LIST_SIZE);
  665. memset(&g_periodic_qh_head[bus->hcd.hcd_id], 0, sizeof(struct ehci_qh_hw));
  666. g_periodic_qh_head[bus->hcd.hcd_id].hw.hlp = QH_HLP_END;
  667. g_periodic_qh_head[bus->hcd.hcd_id].hw.epchar = QH_EPCAPS_SSMASK(1);
  668. g_periodic_qh_head[bus->hcd.hcd_id].hw.overlay.next_qtd = QTD_LIST_END;
  669. g_periodic_qh_head[bus->hcd.hcd_id].hw.overlay.alt_next_qtd = QTD_LIST_END;
  670. g_periodic_qh_head[bus->hcd.hcd_id].hw.overlay.token = QTD_TOKEN_STATUS_HALTED;
  671. g_periodic_qh_head[bus->hcd.hcd_id].first_qtd = QTD_LIST_END;
  672. for (uint32_t i = 0; i < CONFIG_USB_EHCI_FRAME_LIST_SIZE; i++) {
  673. g_framelist[bus->hcd.hcd_id][i] = QH_HLP_QH(&g_periodic_qh_head[bus->hcd.hcd_id]);
  674. }
  675. #if defined(CONFIG_USB_EHCI_DESC_DCACHE_ENABLE)
  676. usb_dcache_clean((uintptr_t)&g_async_qh_head[bus->hcd.hcd_id].hw, CONFIG_USB_EHCI_ALIGN_SIZE);
  677. usb_dcache_clean((uintptr_t)&g_periodic_qh_head[bus->hcd.hcd_id].hw, CONFIG_USB_EHCI_ALIGN_SIZE);
  678. usb_dcache_clean((uintptr_t)g_framelist[bus->hcd.hcd_id], sizeof(uint32_t) * CONFIG_USB_EHCI_FRAME_LIST_SIZE);
  679. #endif
  680. usb_hc_low_level_init(bus);
  681. USB_LOG_INFO("EHCI HCIVERSION:0x%04x\r\n", (unsigned int)EHCI_HCCR->hciversion);
  682. USB_LOG_INFO("EHCI HCSPARAMS:0x%06x\r\n", (unsigned int)EHCI_HCCR->hcsparams);
  683. USB_LOG_INFO("EHCI HCCPARAMS:0x%04x\r\n", (unsigned int)EHCI_HCCR->hccparams);
  684. g_ehci_hcd[bus->hcd.hcd_id].ppc = (EHCI_HCCR->hcsparams & EHCI_HCSPARAMS_PPC) ? true : false;
  685. g_ehci_hcd[bus->hcd.hcd_id].n_ports = (EHCI_HCCR->hcsparams & EHCI_HCSPARAMS_NPORTS_MASK) >> EHCI_HCSPARAMS_NPORTS_SHIFT;
  686. g_ehci_hcd[bus->hcd.hcd_id].n_cc = (EHCI_HCCR->hcsparams & EHCI_HCSPARAMS_NCC_MASK) >> EHCI_HCSPARAMS_NCC_SHIFT;
  687. g_ehci_hcd[bus->hcd.hcd_id].n_pcc = (EHCI_HCCR->hcsparams & EHCI_HCSPARAMS_NPCC_MASK) >> EHCI_HCSPARAMS_NPCC_SHIFT;
  688. g_ehci_hcd[bus->hcd.hcd_id].has_tt = g_ehci_hcd[bus->hcd.hcd_id].n_cc ? false : true;
  689. g_ehci_hcd[bus->hcd.hcd_id].hcor_offset = EHCI_HCCR->caplength;
  690. USB_LOG_INFO("EHCI ppc:%u, n_ports:%u, n_cc:%u, n_pcc:%u\r\n",
  691. g_ehci_hcd[bus->hcd.hcd_id].ppc,
  692. g_ehci_hcd[bus->hcd.hcd_id].n_ports,
  693. g_ehci_hcd[bus->hcd.hcd_id].n_cc,
  694. g_ehci_hcd[bus->hcd.hcd_id].n_pcc);
  695. EHCI_HCOR->usbcmd &= ~EHCI_USBCMD_RUN;
  696. usb_osal_msleep(2);
  697. EHCI_HCOR->usbcmd |= EHCI_USBCMD_HCRESET;
  698. while (EHCI_HCOR->usbcmd & EHCI_USBCMD_HCRESET) {
  699. usb_osal_msleep(1);
  700. timeout++;
  701. if (timeout > 100) {
  702. return -USB_ERR_TIMEOUT;
  703. }
  704. }
  705. EHCI_HCOR->usbintr = 0;
  706. EHCI_HCOR->usbsts = EHCI_HCOR->usbsts;
  707. usb_hc_low_level2_init(bus);
  708. /* Set the Current Asynchronous List Address. */
  709. EHCI_HCOR->asynclistaddr = EHCI_PTR2ADDR(&g_async_qh_head[bus->hcd.hcd_id]);
  710. /* Set the Periodic Frame List Base Address. */
  711. EHCI_HCOR->periodiclistbase = EHCI_PTR2ADDR(g_framelist[bus->hcd.hcd_id]);
  712. regval = EHCI_HCOR->usbcmd;
  713. regval &= ~(EHCI_USBCMD_ITHRE_MASK | EHCI_USBCMD_FLSIZE_MASK);
  714. #if CONFIG_USB_EHCI_FRAME_LIST_SIZE == 1024
  715. regval |= EHCI_USBCMD_FLSIZE_1024;
  716. #elif CONFIG_USB_EHCI_FRAME_LIST_SIZE == 512
  717. regval |= EHCI_USBCMD_FLSIZE_512;
  718. #elif CONFIG_USB_EHCI_FRAME_LIST_SIZE == 256
  719. regval |= EHCI_USBCMD_FLSIZE_256;
  720. #else
  721. #error Unsupported frame size list size
  722. #endif
  723. #if !defined(CONFIG_USB_EHCI_HPMICRO) || !CONFIG_USB_EHCI_HPMICRO
  724. regval |= EHCI_USBCMD_ITHRE_1MF;
  725. #endif
  726. regval |= EHCI_USBCMD_ASEN;
  727. regval |= EHCI_USBCMD_PSEN;
  728. regval |= EHCI_USBCMD_RUN;
  729. EHCI_HCOR->usbcmd = regval;
  730. #ifdef CONFIG_USB_EHCI_CONFIGFLAG
  731. EHCI_HCOR->configflag = EHCI_CONFIGFLAG;
  732. #endif
  733. /* Wait for the EHCI to run (no longer report halted) */
  734. timeout = 0;
  735. while (EHCI_HCOR->usbsts & EHCI_USBSTS_HALTED) {
  736. usb_osal_msleep(1);
  737. timeout++;
  738. if (timeout > 100) {
  739. return -USB_ERR_TIMEOUT;
  740. }
  741. }
  742. if (g_ehci_hcd[bus->hcd.hcd_id].ppc) {
  743. for (uint8_t port = 0; port < g_ehci_hcd[bus->hcd.hcd_id].n_ports; port++) {
  744. regval = EHCI_HCOR->portsc[port];
  745. regval |= EHCI_PORTSC_PP;
  746. regval &= ~(EHCI_PORTSC_CSC | EHCI_PORTSC_PEC | EHCI_PORTSC_OCC);
  747. EHCI_HCOR->portsc[port] = regval;
  748. }
  749. }
  750. if (g_ehci_hcd[bus->hcd.hcd_id].has_tt) {
  751. #ifdef CONFIG_USB_EHCI_WITH_OHCI
  752. USB_LOG_INFO("EHCI uses tt for ls/fs device, so cannot enable this macro\r\n");
  753. return -USB_ERR_INVAL;
  754. #endif
  755. }
  756. if (g_ehci_hcd[bus->hcd.hcd_id].has_tt) {
  757. USB_LOG_INFO("EHCI uses tt for ls/fs device\r\n");
  758. } else {
  759. #ifdef CONFIG_USB_EHCI_WITH_OHCI
  760. USB_LOG_INFO("EHCI uses companion controller for ls/fs device\r\n");
  761. ohci_init(bus);
  762. #else
  763. USB_LOG_WRN("Do not enable companion controller, you should use a hub to support ls/fs device\r\n");
  764. #endif
  765. }
  766. /* Enable EHCI interrupts. */
  767. EHCI_HCOR->usbintr = EHCI_USBIE_INT | EHCI_USBIE_ERR | EHCI_USBIE_PCD | EHCI_USBIE_FATAL | EHCI_USBIE_IAA;
  768. return 0;
  769. }
  770. int usb_hc_deinit(struct usbh_bus *bus)
  771. {
  772. struct ehci_qh_hw *qh;
  773. volatile uint32_t timeout = 0;
  774. uint32_t regval;
  775. EHCI_HCOR->usbintr = 0;
  776. regval = EHCI_HCOR->usbcmd;
  777. regval &= ~EHCI_USBCMD_ASEN;
  778. regval &= ~EHCI_USBCMD_PSEN;
  779. regval &= ~EHCI_USBCMD_RUN;
  780. EHCI_HCOR->usbcmd = regval;
  781. while ((EHCI_HCOR->usbsts & (EHCI_USBSTS_PSS | EHCI_USBSTS_ASS)) || ((EHCI_HCOR->usbsts & EHCI_USBSTS_HALTED) == 0)) {
  782. usb_osal_msleep(1);
  783. timeout++;
  784. if (timeout > 100) {
  785. return -USB_ERR_TIMEOUT;
  786. }
  787. }
  788. if (g_ehci_hcd[bus->hcd.hcd_id].ppc) {
  789. for (uint8_t port = 0; port < g_ehci_hcd[bus->hcd.hcd_id].n_ports; port++) {
  790. regval = EHCI_HCOR->portsc[port];
  791. regval &= ~EHCI_PORTSC_PP;
  792. EHCI_HCOR->portsc[port] = regval;
  793. }
  794. }
  795. #ifdef CONFIG_USB_EHCI_CONFIGFLAG
  796. EHCI_HCOR->configflag = 0;
  797. #endif
  798. EHCI_HCOR->usbsts = EHCI_HCOR->usbsts;
  799. EHCI_HCOR->usbcmd |= EHCI_USBCMD_HCRESET;
  800. for (uint8_t index = 0; index < CONFIG_USB_EHCI_QH_NUM; index++) {
  801. qh = &ehci_qh_pool[bus->hcd.hcd_id][index];
  802. usb_osal_sem_delete(qh->waitsem);
  803. }
  804. #ifdef CONFIG_USB_EHCI_WITH_OHCI
  805. ohci_deinit(bus);
  806. #endif
  807. usb_hc_low_level_deinit(bus);
  808. return 0;
  809. }
  810. uint16_t usbh_get_frame_number(struct usbh_bus *bus)
  811. {
  812. #ifdef CONFIG_USB_EHCI_WITH_OHCI
  813. if (EHCI_HCOR->portsc[0] & EHCI_PORTSC_OWNER) {
  814. return ohci_get_frame_number(bus);
  815. }
  816. #endif
  817. return (((EHCI_HCOR->frindex & EHCI_FRINDEX_MASK) >> 3) & 0x3ff);
  818. }
  819. int usbh_roothub_control(struct usbh_bus *bus, struct usb_setup_packet *setup, uint8_t *buf)
  820. {
  821. uint8_t nports;
  822. uint8_t port;
  823. uint32_t temp, status;
  824. nports = g_ehci_hcd[bus->hcd.hcd_id].n_ports;
  825. port = setup->wIndex;
  826. temp = EHCI_HCOR->portsc[port - 1];
  827. #ifdef CONFIG_USB_EHCI_WITH_OHCI
  828. if (temp & EHCI_PORTSC_OWNER) {
  829. return ohci_roothub_control(bus, setup, buf);
  830. }
  831. if ((temp & EHCI_PORTSC_LSTATUS_MASK) == EHCI_PORTSC_LSTATUS_KSTATE) {
  832. EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_OWNER;
  833. while (!(EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_OWNER)) {
  834. }
  835. USB_LOG_INFO("Switch port %u to OHCI\r\n", port);
  836. return ohci_roothub_control(bus, setup, buf);
  837. }
  838. #endif
  839. if (setup->bmRequestType & USB_REQUEST_RECIPIENT_DEVICE) {
  840. switch (setup->bRequest) {
  841. case HUB_REQUEST_CLEAR_FEATURE:
  842. switch (setup->wValue) {
  843. case HUB_FEATURE_HUB_C_LOCALPOWER:
  844. break;
  845. case HUB_FEATURE_HUB_C_OVERCURRENT:
  846. break;
  847. default:
  848. return -USB_ERR_NOTSUPP;
  849. }
  850. break;
  851. case HUB_REQUEST_SET_FEATURE:
  852. switch (setup->wValue) {
  853. case HUB_FEATURE_HUB_C_LOCALPOWER:
  854. break;
  855. case HUB_FEATURE_HUB_C_OVERCURRENT:
  856. break;
  857. default:
  858. return -USB_ERR_NOTSUPP;
  859. }
  860. break;
  861. case HUB_REQUEST_GET_DESCRIPTOR:
  862. break;
  863. case HUB_REQUEST_GET_STATUS:
  864. memset(buf, 0, 4);
  865. break;
  866. default:
  867. break;
  868. }
  869. } else if (setup->bmRequestType & USB_REQUEST_RECIPIENT_OTHER) {
  870. switch (setup->bRequest) {
  871. case HUB_REQUEST_CLEAR_FEATURE:
  872. if (!port || port > nports) {
  873. return -USB_ERR_INVAL;
  874. }
  875. switch (setup->wValue) {
  876. case HUB_PORT_FEATURE_ENABLE:
  877. EHCI_HCOR->portsc[port - 1] &= ~EHCI_PORTSC_PE;
  878. break;
  879. case HUB_PORT_FEATURE_SUSPEND:
  880. EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_RESUME;
  881. usb_osal_msleep(20);
  882. EHCI_HCOR->portsc[port - 1] &= ~EHCI_PORTSC_RESUME;
  883. while (EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_RESUME) {
  884. }
  885. temp = EHCI_HCOR->usbcmd;
  886. temp |= EHCI_USBCMD_ASEN;
  887. temp |= EHCI_USBCMD_PSEN;
  888. temp |= EHCI_USBCMD_RUN;
  889. EHCI_HCOR->usbcmd = temp;
  890. while ((EHCI_HCOR->usbcmd & EHCI_USBCMD_RUN) == 0) {
  891. }
  892. case HUB_PORT_FEATURE_C_SUSPEND:
  893. break;
  894. case HUB_PORT_FEATURE_POWER:
  895. EHCI_HCOR->portsc[port - 1] &= ~EHCI_PORTSC_PP;
  896. break;
  897. case HUB_PORT_FEATURE_C_CONNECTION:
  898. EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_CSC;
  899. break;
  900. case HUB_PORT_FEATURE_C_ENABLE:
  901. EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_PEC;
  902. break;
  903. case HUB_PORT_FEATURE_C_OVER_CURREN:
  904. EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_OCC;
  905. break;
  906. case HUB_PORT_FEATURE_C_RESET:
  907. break;
  908. default:
  909. return -USB_ERR_NOTSUPP;
  910. }
  911. break;
  912. case HUB_REQUEST_SET_FEATURE:
  913. if (!port || port > nports) {
  914. return -USB_ERR_INVAL;
  915. }
  916. switch (setup->wValue) {
  917. case HUB_PORT_FEATURE_SUSPEND:
  918. temp = EHCI_HCOR->usbcmd;
  919. temp &= ~EHCI_USBCMD_ASEN;
  920. temp &= ~EHCI_USBCMD_PSEN;
  921. temp &= ~EHCI_USBCMD_RUN;
  922. EHCI_HCOR->usbcmd = temp;
  923. while (EHCI_HCOR->usbcmd & EHCI_USBCMD_RUN) {
  924. }
  925. EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_SUSPEND;
  926. while ((EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_SUSPEND) == 0) {
  927. }
  928. break;
  929. case HUB_PORT_FEATURE_POWER:
  930. EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_PP;
  931. break;
  932. case HUB_PORT_FEATURE_RESET:
  933. usbh_reset_port(bus, port);
  934. #ifdef CONFIG_USB_EHCI_WITH_OHCI
  935. if (!(EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_PE)) {
  936. EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_OWNER;
  937. while (!(EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_OWNER)) {
  938. }
  939. USB_LOG_INFO("Switch port %u to OHCI\r\n", port);
  940. return -USB_ERR_NOTSUPP;
  941. }
  942. #endif
  943. break;
  944. default:
  945. return -USB_ERR_NOTSUPP;
  946. }
  947. break;
  948. case HUB_REQUEST_GET_STATUS:
  949. if (!port || port > nports) {
  950. return -USB_ERR_INVAL;
  951. }
  952. temp = EHCI_HCOR->portsc[port - 1];
  953. status = 0;
  954. if (temp & EHCI_PORTSC_CSC) {
  955. status |= (1 << HUB_PORT_FEATURE_C_CONNECTION);
  956. }
  957. if (temp & EHCI_PORTSC_PEC) {
  958. status |= (1 << HUB_PORT_FEATURE_C_ENABLE);
  959. }
  960. if (temp & EHCI_PORTSC_OCC) {
  961. status |= (1 << HUB_PORT_FEATURE_C_OVER_CURREN);
  962. }
  963. if (temp & EHCI_PORTSC_CCS) {
  964. status |= (1 << HUB_PORT_FEATURE_CONNECTION);
  965. }
  966. if (temp & EHCI_PORTSC_PE) {
  967. status |= (1 << HUB_PORT_FEATURE_ENABLE);
  968. if (usbh_get_port_speed(bus, port) == USB_SPEED_LOW) {
  969. status |= (1 << HUB_PORT_FEATURE_LOWSPEED);
  970. } else if (usbh_get_port_speed(bus, port) == USB_SPEED_HIGH) {
  971. status |= (1 << HUB_PORT_FEATURE_HIGHSPEED);
  972. }
  973. }
  974. if (temp & EHCI_PORTSC_SUSPEND) {
  975. status |= (1 << HUB_PORT_FEATURE_SUSPEND);
  976. }
  977. if (temp & EHCI_PORTSC_OCA) {
  978. status |= (1 << HUB_PORT_FEATURE_OVERCURRENT);
  979. }
  980. if (temp & EHCI_PORTSC_RESET) {
  981. status |= (1 << HUB_PORT_FEATURE_RESET);
  982. }
  983. if (temp & EHCI_PORTSC_PP || !(EHCI_HCCR->hcsparams & EHCI_HCSPARAMS_PPC)) {
  984. status |= (1 << HUB_PORT_FEATURE_POWER);
  985. }
  986. memcpy(buf, &status, 4);
  987. break;
  988. default:
  989. break;
  990. }
  991. }
  992. return 0;
  993. }
  994. int usbh_submit_urb(struct usbh_urb *urb)
  995. {
  996. struct ehci_qh_hw *qh = NULL;
  997. size_t flags;
  998. int ret = 0;
  999. struct usbh_hub *hub;
  1000. struct usbh_hubport *hport;
  1001. struct usbh_bus *bus;
  1002. if (!urb || !urb->hport || !urb->ep || !urb->hport->bus) {
  1003. return -USB_ERR_INVAL;
  1004. }
  1005. #ifdef CONFIG_USB_DCACHE_ENABLE
  1006. USB_ASSERT_MSG(!((uintptr_t)urb->setup % CONFIG_USB_ALIGN_SIZE) &&
  1007. !((uintptr_t)urb->transfer_buffer % CONFIG_USB_ALIGN_SIZE),
  1008. "urb->setup or urb->transfer_buffer is not aligned %d", CONFIG_USB_ALIGN_SIZE);
  1009. #endif
  1010. bus = urb->hport->bus;
  1011. /* find active hubport in roothub */
  1012. hport = urb->hport;
  1013. hub = urb->hport->parent;
  1014. while (!hub->is_roothub) {
  1015. hport = hub->parent;
  1016. hub = hub->parent->parent;
  1017. }
  1018. #ifdef CONFIG_USB_EHCI_WITH_OHCI
  1019. if (EHCI_HCOR->portsc[hport->port - 1] & EHCI_PORTSC_OWNER) {
  1020. return ohci_submit_urb(urb);
  1021. }
  1022. #endif
  1023. if (!urb->hport->connected || !(EHCI_HCOR->portsc[hport->port - 1] & EHCI_PORTSC_CCS)) {
  1024. return -USB_ERR_NOTCONN;
  1025. }
  1026. if (urb->errorcode == -USB_ERR_BUSY) {
  1027. return -USB_ERR_BUSY;
  1028. }
  1029. flags = usb_osal_enter_critical_section();
  1030. urb->hcpriv = NULL;
  1031. urb->errorcode = -USB_ERR_BUSY;
  1032. urb->actual_length = 0;
  1033. usb_osal_leave_critical_section(flags);
  1034. switch (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes)) {
  1035. case USB_ENDPOINT_TYPE_CONTROL:
  1036. qh = ehci_control_urb_init(bus, urb, urb->setup, urb->transfer_buffer, urb->transfer_buffer_length);
  1037. if (qh == NULL) {
  1038. return -USB_ERR_NOMEM;
  1039. }
  1040. break;
  1041. case USB_ENDPOINT_TYPE_BULK:
  1042. qh = ehci_bulk_urb_init(bus, urb, urb->transfer_buffer, urb->transfer_buffer_length);
  1043. if (qh == NULL) {
  1044. return -USB_ERR_NOMEM;
  1045. }
  1046. break;
  1047. case USB_ENDPOINT_TYPE_INTERRUPT:
  1048. qh = ehci_intr_urb_init(bus, urb, urb->transfer_buffer, urb->transfer_buffer_length);
  1049. if (qh == NULL) {
  1050. return -USB_ERR_NOMEM;
  1051. }
  1052. break;
  1053. case USB_ENDPOINT_TYPE_ISOCHRONOUS:
  1054. #ifdef CONFIG_USB_EHCI_ISO
  1055. ret = ehci_iso_urb_init(bus, urb);
  1056. #endif
  1057. break;
  1058. default:
  1059. break;
  1060. }
  1061. if (urb->timeout > 0) {
  1062. /* wait until timeout or sem give */
  1063. ret = usb_osal_sem_take(qh->waitsem, urb->timeout);
  1064. if (ret < 0) {
  1065. goto errout_timeout;
  1066. }
  1067. urb->timeout = 0;
  1068. ret = urb->errorcode;
  1069. /* we can free qh when waitsem is done */
  1070. ehci_qh_free(bus, qh);
  1071. }
  1072. return ret;
  1073. errout_timeout:
  1074. urb->timeout = 0;
  1075. usbh_kill_urb(urb);
  1076. return ret;
  1077. }
  1078. int usbh_kill_urb(struct usbh_urb *urb)
  1079. {
  1080. struct ehci_qh_hw *qh;
  1081. struct usbh_bus *bus;
  1082. size_t flags;
  1083. bool remove_in_iaad = false;
  1084. if (!urb || !urb->hport || !urb->hcpriv || !urb->hport->bus) {
  1085. return -USB_ERR_INVAL;
  1086. }
  1087. bus = urb->hport->bus;
  1088. #ifdef CONFIG_USB_EHCI_WITH_OHCI
  1089. if (EHCI_HCOR->portsc[urb->hport->port - 1] & EHCI_PORTSC_OWNER) {
  1090. return ohci_kill_urb(urb);
  1091. }
  1092. #endif
  1093. flags = usb_osal_enter_critical_section();
  1094. EHCI_HCOR->usbcmd &= ~(EHCI_USBCMD_PSEN | EHCI_USBCMD_ASEN);
  1095. if ((USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_CONTROL) || (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_BULK)) {
  1096. qh = EHCI_ADDR2QH(g_async_qh_head[bus->hcd.hcd_id].hw.hlp);
  1097. while ((qh != &g_async_qh_head[bus->hcd.hcd_id]) && qh) {
  1098. if (qh->urb == urb) {
  1099. remove_in_iaad = true;
  1100. ehci_kill_qh(bus, &g_async_qh_head[bus->hcd.hcd_id], qh);
  1101. }
  1102. qh = EHCI_ADDR2QH(qh->hw.hlp);
  1103. }
  1104. } else if (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_INTERRUPT) {
  1105. qh = EHCI_ADDR2QH(g_periodic_qh_head[bus->hcd.hcd_id].hw.hlp);
  1106. while (qh) {
  1107. if (qh->urb == urb) {
  1108. ehci_kill_qh(bus, &g_periodic_qh_head[bus->hcd.hcd_id], qh);
  1109. }
  1110. qh = EHCI_ADDR2QH(qh->hw.hlp);
  1111. }
  1112. } else {
  1113. #ifdef CONFIG_USB_EHCI_ISO
  1114. ehci_kill_iso_urb(bus, urb);
  1115. EHCI_HCOR->usbcmd |= (EHCI_USBCMD_PSEN | EHCI_USBCMD_ASEN);
  1116. usb_osal_leave_critical_section(flags);
  1117. return 0;
  1118. #endif
  1119. }
  1120. EHCI_HCOR->usbcmd |= (EHCI_USBCMD_PSEN | EHCI_USBCMD_ASEN);
  1121. qh = (struct ehci_qh_hw *)urb->hcpriv;
  1122. urb->errorcode = -USB_ERR_SHUTDOWN;
  1123. if (urb->timeout) {
  1124. usb_osal_sem_give(qh->waitsem);
  1125. } else {
  1126. ehci_qh_free(bus, qh);
  1127. }
  1128. if (remove_in_iaad) {
  1129. volatile uint32_t timeout = 0;
  1130. EHCI_HCOR->usbcmd |= EHCI_USBCMD_IAAD;
  1131. while (!(EHCI_HCOR->usbsts & EHCI_USBSTS_IAA)) {
  1132. timeout++;
  1133. if (timeout > 200000) {
  1134. USB_LOG_ERR("iaad timeout\r\n");
  1135. usb_osal_leave_critical_section(flags);
  1136. return -USB_ERR_TIMEOUT;
  1137. }
  1138. }
  1139. EHCI_HCOR->usbsts = EHCI_USBSTS_IAA;
  1140. }
  1141. if (urb->complete) {
  1142. urb->complete(urb->arg, urb->errorcode);
  1143. }
  1144. usb_osal_leave_critical_section(flags);
  1145. return 0;
  1146. }
  1147. static void ehci_scan_async_list(struct usbh_bus *bus)
  1148. {
  1149. struct ehci_qh_hw *qh;
  1150. qh = EHCI_ADDR2QH(g_async_qh_head[bus->hcd.hcd_id].hw.hlp);
  1151. while ((qh != &g_async_qh_head[bus->hcd.hcd_id]) && qh) {
  1152. if (qh->urb) {
  1153. ehci_check_qh(bus, &g_async_qh_head[bus->hcd.hcd_id], qh);
  1154. }
  1155. qh = EHCI_ADDR2QH(qh->hw.hlp);
  1156. }
  1157. }
  1158. static void ehci_scan_periodic_list(struct usbh_bus *bus)
  1159. {
  1160. struct ehci_qh_hw *qh;
  1161. qh = EHCI_ADDR2QH(g_periodic_qh_head[bus->hcd.hcd_id].hw.hlp);
  1162. while (qh) {
  1163. if (qh->urb) {
  1164. ehci_check_qh(bus, &g_periodic_qh_head[bus->hcd.hcd_id], qh);
  1165. }
  1166. qh = EHCI_ADDR2QH(qh->hw.hlp);
  1167. }
  1168. }
  1169. void USBH_IRQHandler(uint8_t busid)
  1170. {
  1171. uint32_t usbsts;
  1172. struct usbh_bus *bus;
  1173. bus = &g_usbhost_bus[busid];
  1174. usbsts = EHCI_HCOR->usbsts & EHCI_HCOR->usbintr;
  1175. EHCI_HCOR->usbsts = usbsts;
  1176. if (usbsts & EHCI_USBSTS_INT) {
  1177. ehci_scan_async_list(bus);
  1178. ehci_scan_periodic_list(bus);
  1179. #ifdef CONFIG_USB_EHCI_ISO
  1180. ehci_scan_isochronous_list(bus);
  1181. #endif
  1182. }
  1183. if (usbsts & EHCI_USBSTS_ERR) {
  1184. ehci_scan_async_list(bus);
  1185. ehci_scan_periodic_list(bus);
  1186. #ifdef CONFIG_USB_EHCI_ISO
  1187. ehci_scan_isochronous_list(bus);
  1188. #endif
  1189. }
  1190. if (usbsts & EHCI_USBSTS_PCD) {
  1191. for (int port = 0; port < g_ehci_hcd[bus->hcd.hcd_id].n_ports; port++) {
  1192. uint32_t portsc = EHCI_HCOR->portsc[port];
  1193. if (portsc & EHCI_PORTSC_CSC) {
  1194. if ((portsc & EHCI_PORTSC_CCS) == EHCI_PORTSC_CCS) {
  1195. } else {
  1196. #if defined(CONFIG_USB_EHCI_NXP)
  1197. /* kUSB_ControllerEhci0 and kUSB_ControllerEhci1*/
  1198. extern void USB_EhcihostPhyDisconnectDetectCmd(uint8_t controllerId, uint8_t enable);
  1199. USB_EhcihostPhyDisconnectDetectCmd(2 + busid, 0);
  1200. #endif
  1201. }
  1202. bus->hcd.roothub.int_buffer[0] |= (1 << (port + 1));
  1203. usbh_hub_thread_wakeup(&bus->hcd.roothub);
  1204. }
  1205. }
  1206. }
  1207. if (usbsts & EHCI_USBSTS_IAA) {
  1208. for (uint8_t index = 0; index < CONFIG_USB_EHCI_QH_NUM; index++) {
  1209. struct ehci_qh_hw *qh = &ehci_qh_pool[bus->hcd.hcd_id][index];
  1210. if (qh->remove_in_iaad) {
  1211. ehci_urb_waitup(bus, qh->urb);
  1212. }
  1213. }
  1214. }
  1215. if (usbsts & EHCI_USBSTS_FATAL) {
  1216. }
  1217. }