usb_dc_fsdev.c 18 KB

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  1. /*
  2. * Copyright (c) 2022, sakumisu
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. #include "usbd_core.h"
  7. #if (CONFIG_USB_DBG_LEVEL >= USB_DBG_LOG)
  8. #error "fsdev cannot enable USB_DBG_LOG"
  9. #endif
  10. #ifndef CONFIG_USBDEV_FSDEV_PMA_ACCESS
  11. #error "please define CONFIG_USBDEV_FSDEV_PMA_ACCESS in usb_config.h"
  12. #endif
  13. #define PMA_ACCESS CONFIG_USBDEV_FSDEV_PMA_ACCESS
  14. #include "usb_fsdev_reg.h"
  15. #ifndef CONFIG_USB_FSDEV_RAM_SIZE
  16. #define CONFIG_USB_FSDEV_RAM_SIZE 512
  17. #endif
  18. #undef CONFIG_USBDEV_EP_NUM
  19. #define CONFIG_USBDEV_EP_NUM 8
  20. #define USB ((USB_TypeDef *)g_usbdev_bus[0].reg_base)
  21. #define USB_BTABLE_SIZE (8 * CONFIG_USBDEV_EP_NUM)
  22. static void fsdev_write_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
  23. static void fsdev_read_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
  24. /* Endpoint state */
  25. struct fsdev_ep_state {
  26. uint16_t ep_mps; /* Endpoint max packet size */
  27. uint8_t ep_type; /* Endpoint type */
  28. uint8_t ep_stalled; /* Endpoint stall flag */
  29. uint8_t ep_enable; /* Endpoint enable */
  30. uint16_t ep_pma_buf_len; /* Previously allocated buffer size */
  31. uint16_t ep_pma_addr; /* ep pmd allocated addr */
  32. uint8_t *xfer_buf;
  33. uint32_t xfer_len;
  34. uint32_t actual_xfer_len;
  35. };
  36. /* Driver state */
  37. struct fsdev_udc {
  38. struct usb_setup_packet setup;
  39. volatile uint8_t dev_addr; /*!< USB Address */
  40. volatile uint32_t pma_offset; /*!< pma offset */
  41. struct fsdev_ep_state in_ep[CONFIG_USBDEV_EP_NUM]; /*!< IN endpoint parameters*/
  42. struct fsdev_ep_state out_ep[CONFIG_USBDEV_EP_NUM]; /*!< OUT endpoint parameters */
  43. } g_fsdev_udc;
  44. __WEAK void usb_dc_low_level_init(void)
  45. {
  46. }
  47. __WEAK void usb_dc_low_level_deinit(void)
  48. {
  49. }
  50. int usb_dc_init(uint8_t busid)
  51. {
  52. usb_dc_low_level_init();
  53. /* Init Device */
  54. /* CNTR_FRES = 1 */
  55. USB->CNTR = (uint16_t)USB_CNTR_FRES;
  56. /* CNTR_FRES = 0 */
  57. USB->CNTR = 0U;
  58. /* Clear pending interrupts */
  59. USB->ISTR = 0U;
  60. /*Set Btable Address*/
  61. USB->BTABLE = BTABLE_ADDRESS;
  62. uint32_t winterruptmask;
  63. /* Set winterruptmask variable */
  64. winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
  65. USB_CNTR_SUSPM | USB_CNTR_ERRM |
  66. USB_CNTR_ESOFM | USB_CNTR_RESETM;
  67. #ifdef CONFIG_USBDEV_SOF_ENABLE
  68. winterruptmask |= USB_CNTR_SOFM;
  69. #endif
  70. /* Set interrupt mask */
  71. USB->CNTR = (uint16_t)winterruptmask;
  72. /* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */
  73. USB->BCDR |= (uint16_t)USB_BCDR_DPPU;
  74. return 0;
  75. }
  76. int usb_dc_deinit(uint8_t busid)
  77. {
  78. /* disable all interrupts and force USB reset */
  79. USB->CNTR = (uint16_t)USB_CNTR_FRES;
  80. /* clear interrupt status register */
  81. USB->ISTR = 0U;
  82. /* switch-off device */
  83. USB->CNTR = (uint16_t)(USB_CNTR_FRES | USB_CNTR_PDWN);
  84. usb_dc_low_level_deinit();
  85. return 0;
  86. }
  87. int usbd_set_address(uint8_t busid, const uint8_t addr)
  88. {
  89. if (addr == 0U) {
  90. /* set device address and enable function */
  91. USB->DADDR = (uint16_t)USB_DADDR_EF;
  92. }
  93. g_fsdev_udc.dev_addr = addr;
  94. return 0;
  95. }
  96. int usbd_set_remote_wakeup(uint8_t busid)
  97. {
  98. return -1;
  99. }
  100. uint8_t usbd_get_port_speed(uint8_t busid)
  101. {
  102. return USB_SPEED_FULL;
  103. }
  104. int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep)
  105. {
  106. uint8_t ep_idx = USB_EP_GET_IDX(ep->bEndpointAddress);
  107. USB_ASSERT_MSG(ep_idx < CONFIG_USBDEV_EP_NUM, "Ep addr %02x overflow", ep->bEndpointAddress);
  108. USB_ASSERT_MSG(USB_GET_ENDPOINT_TYPE(ep->bmAttributes) != USB_ENDPOINT_TYPE_ISOCHRONOUS, "iso endpoint not support in fsdev");
  109. uint16_t wEpRegVal;
  110. /* initialize Endpoint */
  111. switch (USB_GET_ENDPOINT_TYPE(ep->bmAttributes)) {
  112. case USB_ENDPOINT_TYPE_CONTROL:
  113. wEpRegVal = USB_EP_CONTROL;
  114. break;
  115. case USB_ENDPOINT_TYPE_BULK:
  116. wEpRegVal = USB_EP_BULK;
  117. break;
  118. case USB_ENDPOINT_TYPE_INTERRUPT:
  119. wEpRegVal = USB_EP_INTERRUPT;
  120. break;
  121. case USB_ENDPOINT_TYPE_ISOCHRONOUS:
  122. wEpRegVal = USB_EP_ISOCHRONOUS;
  123. break;
  124. default:
  125. return -1;
  126. }
  127. PCD_SET_EPTYPE(USB, ep_idx, wEpRegVal);
  128. PCD_SET_EP_ADDRESS(USB, ep_idx, ep_idx);
  129. if (USB_EP_DIR_IS_OUT(ep->bEndpointAddress)) {
  130. g_fsdev_udc.out_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
  131. g_fsdev_udc.out_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes);
  132. g_fsdev_udc.out_ep[ep_idx].ep_enable = true;
  133. if (g_fsdev_udc.out_ep[ep_idx].ep_mps > g_fsdev_udc.out_ep[ep_idx].ep_pma_buf_len) {
  134. USB_ASSERT_MSG((g_fsdev_udc.pma_offset + g_fsdev_udc.out_ep[ep_idx].ep_mps) <= CONFIG_USB_FSDEV_RAM_SIZE,
  135. "Ep pma %02x overflow", ep->bEndpointAddress);
  136. g_fsdev_udc.out_ep[ep_idx].ep_pma_buf_len = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
  137. g_fsdev_udc.out_ep[ep_idx].ep_pma_addr = g_fsdev_udc.pma_offset;
  138. /*Set the endpoint Receive buffer address */
  139. PCD_SET_EP_RX_ADDRESS(USB, ep_idx, g_fsdev_udc.pma_offset);
  140. g_fsdev_udc.pma_offset += USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
  141. }
  142. /*Set the endpoint Receive buffer counter*/
  143. PCD_SET_EP_RX_CNT(USB, ep_idx, USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize));
  144. PCD_CLEAR_RX_DTOG(USB, ep_idx);
  145. } else {
  146. g_fsdev_udc.in_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
  147. g_fsdev_udc.in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes);
  148. g_fsdev_udc.in_ep[ep_idx].ep_enable = true;
  149. if (g_fsdev_udc.in_ep[ep_idx].ep_mps > g_fsdev_udc.in_ep[ep_idx].ep_pma_buf_len) {
  150. USB_ASSERT_MSG((g_fsdev_udc.pma_offset + g_fsdev_udc.in_ep[ep_idx].ep_mps) <= CONFIG_USB_FSDEV_RAM_SIZE,
  151. "Ep pma %02x overflow", ep->bEndpointAddress);
  152. g_fsdev_udc.in_ep[ep_idx].ep_pma_buf_len = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
  153. g_fsdev_udc.in_ep[ep_idx].ep_pma_addr = g_fsdev_udc.pma_offset;
  154. /*Set the endpoint Transmit buffer address */
  155. PCD_SET_EP_TX_ADDRESS(USB, ep_idx, g_fsdev_udc.pma_offset);
  156. g_fsdev_udc.pma_offset += USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
  157. }
  158. PCD_CLEAR_TX_DTOG(USB, ep_idx);
  159. if (USB_GET_ENDPOINT_TYPE(ep->bmAttributes) != USB_ENDPOINT_TYPE_ISOCHRONOUS) {
  160. /* Configure NAK status for the Endpoint */
  161. PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_NAK);
  162. } else {
  163. /* Configure TX Endpoint to disabled state */
  164. PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_DIS);
  165. }
  166. }
  167. return 0;
  168. }
  169. int usbd_ep_close(uint8_t busid, const uint8_t ep)
  170. {
  171. uint8_t ep_idx = USB_EP_GET_IDX(ep);
  172. if (USB_EP_DIR_IS_OUT(ep)) {
  173. PCD_CLEAR_RX_DTOG(USB, ep_idx);
  174. /* Configure DISABLE status for the Endpoint*/
  175. PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_DIS);
  176. } else {
  177. PCD_CLEAR_TX_DTOG(USB, ep_idx);
  178. /* Configure DISABLE status for the Endpoint*/
  179. PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_DIS);
  180. }
  181. return 0;
  182. }
  183. int usbd_ep_set_stall(uint8_t busid, const uint8_t ep)
  184. {
  185. uint8_t ep_idx = USB_EP_GET_IDX(ep);
  186. if (USB_EP_DIR_IS_OUT(ep)) {
  187. PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_STALL);
  188. } else {
  189. PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_STALL);
  190. }
  191. return 0;
  192. }
  193. int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep)
  194. {
  195. uint8_t ep_idx = USB_EP_GET_IDX(ep);
  196. if (USB_EP_DIR_IS_OUT(ep)) {
  197. PCD_CLEAR_RX_DTOG(USB, ep_idx);
  198. /* Configure VALID status for the Endpoint */
  199. PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_VALID);
  200. } else {
  201. PCD_CLEAR_TX_DTOG(USB, ep_idx);
  202. if (g_fsdev_udc.in_ep[ep_idx].ep_type != USB_ENDPOINT_TYPE_ISOCHRONOUS) {
  203. /* Configure NAK status for the Endpoint */
  204. PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_NAK);
  205. }
  206. }
  207. return 0;
  208. }
  209. int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled)
  210. {
  211. uint8_t ep_idx = USB_EP_GET_IDX(ep);
  212. if (USB_EP_DIR_IS_OUT(ep)) {
  213. if (PCD_GET_EP_RX_STATUS(USB, ep_idx) & USB_EP_RX_STALL) {
  214. *stalled = 1;
  215. } else {
  216. *stalled = 0;
  217. }
  218. } else {
  219. if (PCD_GET_EP_TX_STATUS(USB, ep_idx) & USB_EP_TX_STALL) {
  220. *stalled = 1;
  221. } else {
  222. *stalled = 0;
  223. }
  224. }
  225. return 0;
  226. }
  227. int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, uint32_t data_len)
  228. {
  229. uint8_t ep_idx = USB_EP_GET_IDX(ep);
  230. if (!data && data_len) {
  231. return -1;
  232. }
  233. if (!g_fsdev_udc.in_ep[ep_idx].ep_enable) {
  234. return -2;
  235. }
  236. g_fsdev_udc.in_ep[ep_idx].xfer_buf = (uint8_t *)data;
  237. g_fsdev_udc.in_ep[ep_idx].xfer_len = data_len;
  238. g_fsdev_udc.in_ep[ep_idx].actual_xfer_len = 0;
  239. data_len = MIN(data_len, g_fsdev_udc.in_ep[ep_idx].ep_mps);
  240. fsdev_write_pma(USB, (uint8_t *)data, g_fsdev_udc.in_ep[ep_idx].ep_pma_addr, (uint16_t)data_len);
  241. PCD_SET_EP_TX_CNT(USB, ep_idx, (uint16_t)data_len);
  242. PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_VALID);
  243. return 0;
  244. }
  245. int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t data_len)
  246. {
  247. uint8_t ep_idx = USB_EP_GET_IDX(ep);
  248. if (!data && data_len) {
  249. return -1;
  250. }
  251. if (!g_fsdev_udc.out_ep[ep_idx].ep_enable) {
  252. return -2;
  253. }
  254. g_fsdev_udc.out_ep[ep_idx].xfer_buf = data;
  255. g_fsdev_udc.out_ep[ep_idx].xfer_len = data_len;
  256. g_fsdev_udc.out_ep[ep_idx].actual_xfer_len = 0;
  257. PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_VALID);
  258. return 0;
  259. }
  260. void USBD_IRQHandler(uint8_t busid)
  261. {
  262. uint16_t wIstr, wEPVal;
  263. uint8_t ep_idx;
  264. uint8_t read_count;
  265. uint16_t write_count;
  266. uint16_t store_ep[8];
  267. wIstr = USB->ISTR;
  268. if (wIstr & USB_ISTR_CTR) {
  269. while ((USB->ISTR & USB_ISTR_CTR) != 0U) {
  270. wIstr = USB->ISTR;
  271. /* extract highest priority endpoint number */
  272. ep_idx = (uint8_t)(wIstr & USB_ISTR_EP_ID);
  273. if (ep_idx == 0U) {
  274. if ((wIstr & USB_ISTR_DIR) == 0U) {
  275. PCD_CLEAR_TX_EP_CTR(USB, ep_idx);
  276. write_count = PCD_GET_EP_TX_CNT(USB, ep_idx);
  277. g_fsdev_udc.in_ep[ep_idx].xfer_buf += write_count;
  278. g_fsdev_udc.in_ep[ep_idx].xfer_len -= write_count;
  279. g_fsdev_udc.in_ep[ep_idx].actual_xfer_len += write_count;
  280. usbd_event_ep_in_complete_handler(0, ep_idx | 0x80, g_fsdev_udc.in_ep[ep_idx].actual_xfer_len);
  281. if (g_fsdev_udc.setup.wLength == 0) {
  282. /* In status, start reading setup */
  283. usbd_ep_start_read(0, 0x00, NULL, 0);
  284. } else if (g_fsdev_udc.setup.wLength && ((g_fsdev_udc.setup.bmRequestType & USB_REQUEST_DIR_MASK) == USB_REQUEST_DIR_OUT)) {
  285. /* In status, start reading setup */
  286. usbd_ep_start_read(0, 0x00, NULL, 0);
  287. }
  288. if ((g_fsdev_udc.dev_addr > 0U) && (write_count == 0U)) {
  289. USB->DADDR = ((uint16_t)g_fsdev_udc.dev_addr | USB_DADDR_EF);
  290. g_fsdev_udc.dev_addr = 0U;
  291. }
  292. } else {
  293. wEPVal = PCD_GET_ENDPOINT(USB, ep_idx);
  294. if ((wEPVal & USB_EP_SETUP) != 0U) {
  295. PCD_CLEAR_RX_EP_CTR(USB, ep_idx);
  296. read_count = PCD_GET_EP_RX_CNT(USB, ep_idx);
  297. fsdev_read_pma(USB, (uint8_t *)&g_fsdev_udc.setup, g_fsdev_udc.out_ep[ep_idx].ep_pma_addr, (uint16_t)read_count);
  298. usbd_event_ep0_setup_complete_handler(0, (uint8_t *)&g_fsdev_udc.setup);
  299. } else if ((wEPVal & USB_EP_CTR_RX) != 0U) {
  300. PCD_CLEAR_RX_EP_CTR(USB, ep_idx);
  301. read_count = PCD_GET_EP_RX_CNT(USB, ep_idx);
  302. fsdev_read_pma(USB, g_fsdev_udc.out_ep[ep_idx].xfer_buf, g_fsdev_udc.out_ep[ep_idx].ep_pma_addr, (uint16_t)read_count);
  303. g_fsdev_udc.out_ep[ep_idx].xfer_buf += read_count;
  304. g_fsdev_udc.out_ep[ep_idx].xfer_len -= read_count;
  305. g_fsdev_udc.out_ep[ep_idx].actual_xfer_len += read_count;
  306. usbd_event_ep_out_complete_handler(0, ep_idx, g_fsdev_udc.out_ep[ep_idx].actual_xfer_len);
  307. if (read_count == 0) {
  308. /* Out status, start reading setup */
  309. usbd_ep_start_read(0, 0x00, NULL, 0);
  310. }
  311. }
  312. }
  313. } else {
  314. wEPVal = PCD_GET_ENDPOINT(USB, ep_idx);
  315. if ((wEPVal & USB_EP_CTR_RX) != 0U) {
  316. PCD_CLEAR_RX_EP_CTR(USB, ep_idx);
  317. read_count = PCD_GET_EP_RX_CNT(USB, ep_idx);
  318. fsdev_read_pma(USB, g_fsdev_udc.out_ep[ep_idx].xfer_buf, g_fsdev_udc.out_ep[ep_idx].ep_pma_addr, (uint16_t)read_count);
  319. g_fsdev_udc.out_ep[ep_idx].xfer_buf += read_count;
  320. g_fsdev_udc.out_ep[ep_idx].xfer_len -= read_count;
  321. g_fsdev_udc.out_ep[ep_idx].actual_xfer_len += read_count;
  322. if ((read_count < g_fsdev_udc.out_ep[ep_idx].ep_mps) ||
  323. (g_fsdev_udc.out_ep[ep_idx].xfer_len == 0)) {
  324. usbd_event_ep_out_complete_handler(0, ep_idx, g_fsdev_udc.out_ep[ep_idx].actual_xfer_len);
  325. } else {
  326. PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_VALID);
  327. }
  328. }
  329. if ((wEPVal & USB_EP_CTR_TX) != 0U) {
  330. PCD_CLEAR_TX_EP_CTR(USB, ep_idx);
  331. write_count = PCD_GET_EP_TX_CNT(USB, ep_idx);
  332. g_fsdev_udc.in_ep[ep_idx].xfer_buf += write_count;
  333. g_fsdev_udc.in_ep[ep_idx].xfer_len -= write_count;
  334. g_fsdev_udc.in_ep[ep_idx].actual_xfer_len += write_count;
  335. if (g_fsdev_udc.in_ep[ep_idx].xfer_len == 0) {
  336. usbd_event_ep_in_complete_handler(0, ep_idx | 0x80, g_fsdev_udc.in_ep[ep_idx].actual_xfer_len);
  337. } else {
  338. write_count = MIN(g_fsdev_udc.in_ep[ep_idx].xfer_len, g_fsdev_udc.in_ep[ep_idx].ep_mps);
  339. fsdev_write_pma(USB, g_fsdev_udc.in_ep[ep_idx].xfer_buf, g_fsdev_udc.in_ep[ep_idx].ep_pma_addr, (uint16_t)write_count);
  340. PCD_SET_EP_TX_CNT(USB, ep_idx, write_count);
  341. PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_VALID);
  342. }
  343. }
  344. }
  345. }
  346. }
  347. if (wIstr & USB_ISTR_RESET) {
  348. memset(&g_fsdev_udc, 0, sizeof(struct fsdev_udc));
  349. g_fsdev_udc.pma_offset = USB_BTABLE_SIZE;
  350. usbd_event_reset_handler(0);
  351. /* start reading setup packet */
  352. PCD_SET_EP_RX_STATUS(USB, 0, USB_EP_RX_VALID);
  353. USB->ISTR &= (uint16_t)(~USB_ISTR_RESET);
  354. }
  355. if (wIstr & USB_ISTR_PMAOVR) {
  356. USB->ISTR &= (uint16_t)(~USB_ISTR_PMAOVR);
  357. }
  358. if (wIstr & USB_ISTR_ERR) {
  359. USB->ISTR &= (uint16_t)(~USB_ISTR_ERR);
  360. }
  361. if (wIstr & USB_ISTR_WKUP) {
  362. USB->CNTR &= (uint16_t) ~(USB_CNTR_LP_MODE);
  363. USB->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
  364. USB->ISTR &= (uint16_t)(~USB_ISTR_WKUP);
  365. }
  366. if (wIstr & USB_ISTR_SUSP) {
  367. /* WA: To Clear Wakeup flag if raised with suspend signal */
  368. /* Store Endpoint register */
  369. for (uint8_t i = 0U; i < 8U; i++) {
  370. store_ep[i] = PCD_GET_ENDPOINT(USB, i);
  371. }
  372. /* FORCE RESET */
  373. USB->CNTR |= (uint16_t)(USB_CNTR_FRES);
  374. /* CLEAR RESET */
  375. USB->CNTR &= (uint16_t)(~USB_CNTR_FRES);
  376. /* wait for reset flag in ISTR */
  377. while ((USB->ISTR & USB_ISTR_RESET) == 0U) {
  378. }
  379. /* Clear Reset Flag */
  380. USB->ISTR &= (uint16_t)(~USB_ISTR_RESET);
  381. /* Restore Registre */
  382. for (uint8_t i = 0U; i < 8U; i++) {
  383. PCD_SET_ENDPOINT(USB, i, store_ep[i]);
  384. }
  385. /* Force low-power mode in the macrocell */
  386. USB->CNTR |= (uint16_t)USB_CNTR_FSUSP;
  387. /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
  388. USB->ISTR &= (uint16_t)(~USB_ISTR_SUSP);
  389. USB->CNTR |= (uint16_t)USB_CNTR_LP_MODE;
  390. }
  391. #ifdef CONFIG_USBDEV_SOF_ENABLE
  392. if (wIstr & USB_ISTR_SOF) {
  393. USB->ISTR &= (uint16_t)(~USB_ISTR_SOF);
  394. usbd_event_sof_handler(0);
  395. }
  396. #endif
  397. if (wIstr & USB_ISTR_ESOF) {
  398. USB->ISTR &= (uint16_t)(~USB_ISTR_ESOF);
  399. }
  400. }
  401. static void fsdev_write_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
  402. {
  403. uint32_t n = ((uint32_t)wNBytes + 1U) >> 1;
  404. uint32_t BaseAddr = (uint32_t)USBx;
  405. uint32_t i, temp1, temp2;
  406. __IO uint16_t *pdwVal;
  407. uint8_t *pBuf = pbUsrBuf;
  408. pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
  409. for (i = n; i != 0U; i--) {
  410. temp1 = *pBuf;
  411. pBuf++;
  412. temp2 = temp1 | ((uint16_t)((uint16_t)*pBuf << 8));
  413. *pdwVal = (uint16_t)temp2;
  414. pdwVal++;
  415. #if PMA_ACCESS > 1U
  416. pdwVal++;
  417. #endif
  418. pBuf++;
  419. }
  420. }
  421. /**
  422. * @brief Copy data from packet memory area (PMA) to user memory buffer
  423. * @param USBx USB peripheral instance register address.
  424. * @param pbUsrBuf pointer to user memory area.
  425. * @param wPMABufAddr address into PMA.
  426. * @param wNBytes no. of bytes to be copied.
  427. * @retval None
  428. */
  429. static void fsdev_read_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
  430. {
  431. uint32_t n = (uint32_t)wNBytes >> 1;
  432. uint32_t BaseAddr = (uint32_t)USBx;
  433. uint32_t i, temp;
  434. __IO uint16_t *pdwVal;
  435. uint8_t *pBuf = pbUsrBuf;
  436. pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
  437. for (i = n; i != 0U; i--) {
  438. temp = *(__IO uint16_t *)pdwVal;
  439. pdwVal++;
  440. *pBuf = (uint8_t)((temp >> 0) & 0xFFU);
  441. pBuf++;
  442. *pBuf = (uint8_t)((temp >> 8) & 0xFFU);
  443. pBuf++;
  444. #if PMA_ACCESS > 1U
  445. pdwVal++;
  446. #endif
  447. }
  448. if ((wNBytes % 2U) != 0U) {
  449. temp = *pdwVal;
  450. *pBuf = (uint8_t)((temp >> 0) & 0xFFU);
  451. }
  452. }