cpu.c 2.0 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2008-12-11 XuXinming first version
  9. * 2013-05-24 Grissiom port to RM48x50
  10. */
  11. #include <rtthread.h>
  12. /**
  13. * @addtogroup RM48x50
  14. */
  15. /*@{*/
  16. #ifdef __TI_COMPILER_VERSION__
  17. #ifdef RT_USING_CPU_FFS
  18. int __rt_ffs(int value)
  19. {
  20. if (value == 0)
  21. return value;
  22. __asm(" rsb r1, r0, #0");
  23. __asm(" and r1, r1, r0");
  24. __asm(" clz r1, r1");
  25. __asm(" rsb r0, r1, #32");
  26. }
  27. #endif
  28. void rt_hw_cpu_icache_enable()
  29. {
  30. __asm(" MRC p15, #0, r1, c1, c0, #0 ; Read SCTLR configuration data");
  31. __asm(" ORR r1, r1, #0x1 <<12 ; instruction cache enable");
  32. __asm(" MCR p15, #0, r0, c7, c5, #0 ; Invalidate entire instruction cache, r0 is ignored");
  33. __asm(" MCR p15, #0, r1, c1, c0, #0 ; enabled instruction cache");
  34. __asm(" ISB");
  35. }
  36. void rt_hw_cpu_icache_disable()
  37. {
  38. __asm(" MRC p15, #0, r1, c1, c0, #0 ; Read SCTLR configuration data");
  39. __asm(" BIC r1, r1, #0x1 <<12 ; instruction cache enable");
  40. __asm(" MCR p15, #0, r1, c1, c0, #0 ; disabled instruction cache");
  41. __asm(" ISB");
  42. }
  43. void rt_hw_cpu_dcache_enable()
  44. {
  45. __asm(" MRC p15, #0, R1, c1, c0, #0 ; Read SCTLR configuration data");
  46. __asm(" ORR R1, R1, #0x1 <<2");
  47. __asm(" DSB");
  48. __asm(" MCR p15, #0, r0, c15, c5, #0 ; Invalidate entire data cache");
  49. __asm(" MCR p15, #0, R1, c1, c0, #0 ; enabled data cache");
  50. }
  51. void rt_hw_cpu_dcache_disable()
  52. {
  53. /* FIXME: Clean entire data cache. This routine depends on the data cache
  54. * size. It can be omitted if it is known that the data cache has no dirty
  55. * data. */
  56. __asm(" MRC p15, #0, r1, c1, c0, #0 ; Read SCTLR configuration data");
  57. __asm(" BIC r1, r1, #0x1 <<2");
  58. __asm(" DSB");
  59. __asm(" MCR p15, #0, r1, c1, c0, #0 ; disabled data cache");
  60. }
  61. #elif __GNUC__
  62. #ifdef RT_USING_CPU_FFS
  63. int __rt_ffs(int value)
  64. {
  65. return __builtin_ffs(value);
  66. }
  67. #endif
  68. #endif
  69. /*@}*/