drv_spi.c 8.6 KB

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  1. /*
  2. * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2020-01-14 wangyq the first version
  9. * 2019-11-01 wangyq update libraries
  10. */
  11. #include <rtthread.h>
  12. #include <rtdevice.h>
  13. #include <string.h>
  14. #include <rthw.h>
  15. #include "board.h"
  16. #include "drv_spi.h"
  17. #include <ald_spi.h>
  18. #include <ald_gpio.h>
  19. #include <ald_cmu.h>
  20. #ifdef RT_USING_SPI
  21. #define SPITIMEOUT 0xFFFF
  22. rt_err_t spi_configure(struct rt_spi_device *device,
  23. struct rt_spi_configuration *cfg)
  24. {
  25. spi_handle_t *hspi;
  26. hspi = (spi_handle_t *)device->bus->parent.user_data;
  27. /* config spi mode */
  28. if (cfg->mode & RT_SPI_SLAVE)
  29. {
  30. hspi->init.mode = SPI_MODE_SLAVER;
  31. }
  32. else
  33. {
  34. hspi->init.mode = SPI_MODE_MASTER;
  35. }
  36. if (cfg->mode & RT_SPI_3WIRE)
  37. {
  38. hspi->init.dir = SPI_DIRECTION_1LINE;
  39. }
  40. else
  41. {
  42. hspi->init.dir = SPI_DIRECTION_2LINES;
  43. }
  44. if (cfg->data_width == 8)
  45. {
  46. hspi->init.data_size = SPI_DATA_SIZE_8;
  47. }
  48. else if (cfg->data_width == 16)
  49. {
  50. hspi->init.data_size = SPI_DATA_SIZE_16;
  51. }
  52. if (cfg->mode & RT_SPI_CPHA)
  53. {
  54. hspi->init.phase = SPI_CPHA_SECOND;
  55. }
  56. else
  57. {
  58. hspi->init.phase = SPI_CPHA_FIRST;
  59. }
  60. if (cfg->mode & RT_SPI_CPOL)
  61. {
  62. hspi->init.polarity = SPI_CPOL_HIGH;
  63. }
  64. else
  65. {
  66. hspi->init.polarity = SPI_CPOL_LOW;
  67. }
  68. if (cfg->mode & RT_SPI_NO_CS)
  69. {
  70. hspi->init.ss_en = DISABLE;
  71. }
  72. else
  73. {
  74. hspi->init.ss_en = ENABLE;
  75. }
  76. /* config spi clock */
  77. if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 2)
  78. {
  79. /* pclk1 max speed 48MHz, spi master max speed 10MHz */
  80. if (ald_cmu_get_pclk1_clock() / 2 <= 10000000)
  81. {
  82. hspi->init.baud = SPI_BAUD_2;
  83. }
  84. else if (ald_cmu_get_pclk1_clock() / 4 <= 10000000)
  85. {
  86. hspi->init.baud = SPI_BAUD_4;
  87. }
  88. else
  89. {
  90. hspi->init.baud = SPI_BAUD_8;
  91. }
  92. }
  93. else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 4)
  94. {
  95. /* pclk1 max speed 48MHz, spi master max speed 10MHz */
  96. if (ald_cmu_get_pclk1_clock() / 4 <= 10000000)
  97. {
  98. hspi->init.baud = SPI_BAUD_4;
  99. }
  100. else
  101. {
  102. hspi->init.baud = SPI_BAUD_8;
  103. }
  104. }
  105. else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 8)
  106. {
  107. hspi->init.baud = SPI_BAUD_8;
  108. }
  109. else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 16)
  110. {
  111. hspi->init.baud = SPI_BAUD_16;
  112. }
  113. else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 32)
  114. {
  115. hspi->init.baud = SPI_BAUD_32;
  116. }
  117. else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 64)
  118. {
  119. hspi->init.baud = SPI_BAUD_64;
  120. }
  121. else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 128)
  122. {
  123. hspi->init.baud = SPI_BAUD_128;
  124. }
  125. else
  126. {
  127. hspi->init.baud = SPI_BAUD_256;
  128. }
  129. hspi->init.ss_en = DISABLE;
  130. hspi->init.crc_calc = DISABLE;
  131. ald_spi_init(hspi);
  132. return RT_EOK;
  133. }
  134. static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
  135. {
  136. rt_err_t res;
  137. spi_handle_t *hspi;
  138. struct es32f3_hw_spi_cs *cs;
  139. RT_ASSERT(device != RT_NULL);
  140. RT_ASSERT(device->bus != RT_NULL);
  141. RT_ASSERT(device->bus->parent.user_data != RT_NULL);
  142. RT_ASSERT(message->send_buf != RT_NULL || message->recv_buf != RT_NULL);
  143. hspi = (spi_handle_t *)device->bus->parent.user_data;
  144. cs = device->parent.user_data;
  145. /* send & receive */
  146. if ((message->send_buf != RT_NULL) && (message->recv_buf != RT_NULL))
  147. {
  148. if (message->cs_take)
  149. {
  150. rt_pin_write(cs->pin, 0);
  151. }
  152. res = ald_spi_send_recv(hspi, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf,
  153. (rt_int32_t)message->length, SPITIMEOUT);
  154. if (message->cs_release)
  155. {
  156. rt_pin_write(cs->pin, 1);
  157. }
  158. if (res != RT_EOK)
  159. return RT_ERROR;
  160. }
  161. else
  162. {
  163. /* only send data */
  164. if (message->recv_buf == RT_NULL)
  165. {
  166. if (message->cs_take)
  167. {
  168. rt_pin_write(cs->pin, 0);
  169. }
  170. res = ald_spi_send(hspi, (rt_uint8_t *)message->send_buf, (rt_int32_t)message->length, SPITIMEOUT);
  171. if (message->cs_release)
  172. {
  173. rt_pin_write(cs->pin, 1);
  174. }
  175. if (res != RT_EOK)
  176. return RT_ERROR;
  177. }
  178. /* only receive data */
  179. if (message->send_buf == RT_NULL)
  180. {
  181. if (message->cs_take)
  182. {
  183. rt_pin_write(cs->pin, 0);
  184. }
  185. res = ald_spi_recv(hspi, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT);
  186. if (message->cs_release)
  187. {
  188. rt_pin_write(cs->pin, 1);
  189. }
  190. if (res != RT_EOK)
  191. return RT_ERROR;
  192. }
  193. }
  194. return message->length;
  195. }
  196. const struct rt_spi_ops es32f3_spi_ops =
  197. {
  198. spi_configure,
  199. spixfer,
  200. };
  201. rt_err_t es32f3_spi_device_attach(rt_uint32_t pin, const char *bus_name, const char *device_name)
  202. {
  203. /* define spi Instance */
  204. struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
  205. RT_ASSERT(spi_device != RT_NULL);
  206. struct es32f3_hw_spi_cs *cs_pin = (struct es32f3_hw_spi_cs *)rt_malloc(sizeof(struct es32f3_hw_spi_cs));
  207. RT_ASSERT(cs_pin != RT_NULL);
  208. cs_pin->pin = pin;
  209. rt_pin_mode(pin, PIN_MODE_OUTPUT);
  210. rt_pin_write(pin, 1);
  211. return rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
  212. }
  213. #ifdef BSP_USING_SPI0
  214. static struct rt_spi_bus _spi_bus0;
  215. static spi_handle_t _spi0;
  216. #endif
  217. #ifdef BSP_USING_SPI1
  218. static struct rt_spi_bus _spi_bus1;
  219. static spi_handle_t _spi1;
  220. #endif
  221. #ifdef BSP_USING_SPI2
  222. static struct rt_spi_bus _spi_bus2;
  223. static spi_handle_t _spi2;
  224. #endif
  225. int rt_hw_spi_init(void)
  226. {
  227. int result = RT_EOK;
  228. struct rt_spi_bus *spi_bus;
  229. spi_handle_t *spi;
  230. gpio_init_t gpio_instruct;
  231. #ifdef BSP_USING_SPI0
  232. _spi0.perh = SPI0;
  233. spi_bus = &_spi_bus0;
  234. spi = &_spi0;
  235. /* SPI0 gpio init */
  236. gpio_instruct.mode = GPIO_MODE_OUTPUT;
  237. gpio_instruct.odos = GPIO_PUSH_PULL;
  238. gpio_instruct.podrv = GPIO_OUT_DRIVE_1;
  239. gpio_instruct.nodrv = GPIO_OUT_DRIVE_1;
  240. gpio_instruct.func = GPIO_FUNC_4;
  241. gpio_instruct.type = GPIO_TYPE_TTL;
  242. gpio_instruct.flt = GPIO_FILTER_DISABLE;
  243. /* PB3->SPI0_SCK, PB5->SPI0_MOSI */
  244. ald_gpio_init(GPIOB, GPIO_PIN_3 | GPIO_PIN_5, &gpio_instruct);
  245. /* PB4->SPI0_MISO */
  246. gpio_instruct.mode = GPIO_MODE_INPUT;
  247. ald_gpio_init(GPIOB, GPIO_PIN_4, &gpio_instruct);
  248. spi_bus->parent.user_data = spi;
  249. result = rt_spi_bus_register(spi_bus, "spi0", &es32f3_spi_ops);
  250. if (result != RT_EOK)
  251. {
  252. return result;
  253. }
  254. #endif
  255. #ifdef BSP_USING_SPI1
  256. _spi1.perh = SPI1;
  257. spi_bus = &_spi_bus1;
  258. spi = &_spi1;
  259. /* SPI1 gpio init */
  260. gpio_instruct.mode = GPIO_MODE_OUTPUT;
  261. gpio_instruct.odos = GPIO_PUSH_PULL;
  262. gpio_instruct.podrv = GPIO_OUT_DRIVE_1;
  263. gpio_instruct.nodrv = GPIO_OUT_DRIVE_1;
  264. gpio_instruct.func = GPIO_FUNC_4;
  265. gpio_instruct.type = GPIO_TYPE_TTL;
  266. gpio_instruct.flt = GPIO_FILTER_DISABLE;
  267. /* PC01->SPI1_SCK, PC03->SPI1_MOSI */
  268. ald_gpio_init(GPIOC, GPIO_PIN_1 | GPIO_PIN_3, &gpio_instruct);
  269. /* PC02->SPI1_MISO */
  270. gpio_instruct.mode = GPIO_MODE_INPUT;
  271. ald_gpio_init(GPIOC, GPIO_PIN_2, &gpio_instruct);
  272. spi_bus->parent.user_data = spi;
  273. result = rt_spi_bus_register(spi_bus, "spi1", &es32f3_spi_ops);
  274. if (result != RT_EOK)
  275. {
  276. return result;
  277. }
  278. #endif
  279. #ifdef BSP_USING_SPI2
  280. _spi1.perh = SPI2;
  281. spi_bus = &_spi_bus2;
  282. spi = &_spi2;
  283. /* SPI2 gpio init */
  284. gpio_instruct.mode = GPIO_MODE_OUTPUT;
  285. gpio_instruct.odos = GPIO_PUSH_PULL;
  286. gpio_instruct.podrv = GPIO_OUT_DRIVE_1;
  287. gpio_instruct.nodrv = GPIO_OUT_DRIVE_1;
  288. gpio_instruct.func = GPIO_FUNC_5;
  289. gpio_instruct.type = GPIO_TYPE_TTL;
  290. gpio_instruct.flt = GPIO_FILTER_DISABLE;
  291. /* PC05->SPI1_SCK, PB01->SPI1_MOSI */
  292. ald_gpio_init(GPIOC, GPIO_PIN_5 | GPIO_PIN_1, &gpio_instruct);
  293. /* PB00->SPI1_MISO */
  294. gpio_instruct.mode = GPIO_MODE_INPUT;
  295. ald_gpio_init(GPIOB, GPIO_PIN_0, &gpio_instruct);
  296. spi_bus->parent.user_data = spi;
  297. result = rt_spi_bus_register(spi_bus, "spi2", &es32f3_spi_ops);
  298. if (result != RT_EOK)
  299. {
  300. return result;
  301. }
  302. #endif
  303. return result;
  304. }
  305. INIT_BOARD_EXPORT(rt_hw_spi_init);
  306. #endif