board.c 4.9 KB

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  1. /*
  2. * Copyright (c) 2006-2020, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2020-04-16 bigmagic first version
  9. */
  10. #include <rthw.h>
  11. #include <rtthread.h>
  12. #include "board.h"
  13. #include "drv_uart.h"
  14. #include "cp15.h"
  15. #include "mmu.h"
  16. #include "mbox.h"
  17. #ifdef RT_USING_USERSPACE
  18. #include <page.h>
  19. #include <lwp_arch.h>
  20. #endif
  21. rt_mmu_info mmu_info;
  22. extern size_t MMUTable[];
  23. size_t gpio_base_addr = GPIO_BASE_ADDR;
  24. size_t uart_base_addr = UART_BASE;
  25. size_t gic_base_addr = GIC_V2_BASE;
  26. size_t arm_timer_base = ARM_TIMER_BASE;
  27. size_t pactl_cs_base = PACTL_CS_ADDR;
  28. size_t stimer_base_addr = STIMER_BASE;
  29. size_t mmc2_base_addr = MMC2_BASE_ADDR;
  30. size_t videocore_mbox = VIDEOCORE_MBOX;
  31. size_t mbox_addr = MBOX_ADDR;
  32. size_t wdt_base_addr = WDT_BASE;
  33. uint8_t *mac_reg_base_addr = (uint8_t *)MAC_REG;
  34. uint8_t *eth_send_no_cache = (uint8_t *)SEND_DATA_NO_CACHE;
  35. uint8_t *eth_recv_no_cache = (uint8_t *)RECV_DATA_NO_CACHE;
  36. #ifdef RT_USING_USERSPACE
  37. struct mem_desc platform_mem_desc[] = {
  38. {KERNEL_VADDR_START, KERNEL_VADDR_START + 0x0fffffff, KERNEL_VADDR_START + PV_OFFSET, NORMAL_MEM}
  39. };
  40. #else
  41. struct mem_desc platform_mem_desc[] = {
  42. {0x0, 0x6400000, 0x0, NORMAL_MEM},
  43. {0xFE000000, 0xFE400000, 0xFE000000, DEVICE_MEM},//uart gpio
  44. {0xFF800000, 0xFFA00000, 0xFF800000, DEVICE_MEM} //gic
  45. };
  46. #endif
  47. const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc)/sizeof(platform_mem_desc[0]);
  48. void rt_hw_timer_isr(int vector, void *parameter)
  49. {
  50. ARM_TIMER_IRQCLR = 0;
  51. rt_tick_increase();
  52. }
  53. void rt_hw_timer_init(void)
  54. {
  55. rt_uint32_t apb_clock = 0;
  56. rt_uint32_t timer_clock = 1000000;
  57. /* timer_clock = apb_clock/(pre_divider + 1) */
  58. apb_clock = bcm271x_mbox_clock_get_rate(CORE_CLK_ID);
  59. ARM_TIMER_PREDIV = (apb_clock/timer_clock - 1);
  60. ARM_TIMER_RELOAD = 0;
  61. ARM_TIMER_LOAD = 0;
  62. ARM_TIMER_IRQCLR = 0;
  63. ARM_TIMER_CTRL = 0;
  64. ARM_TIMER_RELOAD = 1000000/RT_TICK_PER_SECOND;
  65. ARM_TIMER_LOAD = 1000000/RT_TICK_PER_SECOND;
  66. /* 23-bit counter, enable interrupt, enable timer */
  67. ARM_TIMER_CTRL = (1 << 1) | (1 << 5) | (1 << 7);
  68. rt_hw_interrupt_install(ARM_TIMER_IRQ, rt_hw_timer_isr, RT_NULL, "tick");
  69. rt_hw_interrupt_umask(ARM_TIMER_IRQ);
  70. }
  71. void idle_wfi(void)
  72. {
  73. asm volatile ("wfi");
  74. }
  75. #ifdef RT_USING_USERSPACE
  76. rt_region_t init_page_region = {
  77. (uint32_t)(KERNEL_VADDR_START + 32 * 1024 * 1024),
  78. (uint32_t)(KERNEL_VADDR_START + 64 * 1024 * 1024),
  79. };
  80. #endif
  81. /**
  82. * Initialize the Hardware related stuffs. Called from rtthread_startup()
  83. * after interrupt disabled.
  84. */
  85. void rt_hw_board_init(void)
  86. {
  87. /* io device remap */
  88. #ifdef RT_USING_USERSPACE
  89. rt_hw_mmu_map_init(&mmu_info, (void*)0xf0000000, 0x10000000, MMUTable, PV_OFFSET);
  90. rt_page_init(init_page_region);
  91. rt_hw_mmu_ioremap_init(&mmu_info, (void*)0xf0000000, 0x10000000);
  92. arch_kuser_init(&mmu_info, (void*)0xffff0000);
  93. #else
  94. rt_hw_mmu_map_init(&mmu_info, (void*)GPIO_BASE_ADDR, 0x10000000, MMUTable, 0);
  95. #endif
  96. /* map peripheral address to virtual address */
  97. #ifdef RT_USING_HEAP
  98. /* initialize memory system */
  99. rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
  100. #endif
  101. //gpio
  102. gpio_base_addr = (size_t)rt_ioremap((void*)GPIO_BASE_ADDR, 0x1000);
  103. //uart
  104. //uart_base_addr = (size_t)rt_ioremap((void*)UART_BASE, 0x1000);
  105. //aux
  106. //aux_addr = (size_t)rt_ioremap((void*)AUX_BASE_ADDR, 0x1000);
  107. //timer
  108. arm_timer_base = (size_t)rt_ioremap((void*)ARM_TIMER_BASE, 0x1000);
  109. //gic
  110. //gic_base_addr = (size_t)rt_ioremap((void*)GIC_V2_BASE, 0x10000);
  111. //pactl
  112. pactl_cs_base = (size_t)rt_ioremap((void*)PACTL_CS_ADDR, 0x1000);
  113. //stimer
  114. stimer_base_addr = (size_t)rt_ioremap((void*)STIMER_BASE, 0x1000);
  115. //mmc2_base_addr
  116. mmc2_base_addr = (size_t)rt_ioremap((void*)MMC2_BASE_ADDR, 0x1000);
  117. //mbox
  118. videocore_mbox = (size_t)rt_ioremap((void*)VIDEOCORE_MBOX, 0x1000);
  119. //mbox msg
  120. mbox_addr = (size_t)rt_ioremap((void*)MBOX_ADDR, 0x1000);
  121. mbox = (volatile unsigned int *)mbox_addr;
  122. //wdt
  123. wdt_base_addr = (size_t)rt_ioremap((void*)WDT_BASE, 0x1000);
  124. //mac
  125. mac_reg_base_addr = (void *)rt_ioremap((void*)MAC_REG, 0x80000);
  126. //eth data
  127. eth_send_no_cache = (void *)rt_ioremap((void*)SEND_DATA_NO_CACHE, 0x200000);
  128. eth_recv_no_cache = (void *)rt_ioremap((void*)RECV_DATA_NO_CACHE, 0x200000);
  129. /* initialize hardware interrupt */
  130. rt_hw_interrupt_init();
  131. /* initialize uart */
  132. rt_hw_uart_init();
  133. #ifdef RT_USING_CONSOLE
  134. /* set console device */
  135. rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
  136. #endif /* RT_USING_CONSOLE */
  137. /* initialize timer for os tick */
  138. rt_hw_timer_init();
  139. rt_thread_idle_sethook(idle_wfi);
  140. rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
  141. #ifdef RT_USING_COMPONENTS_INIT
  142. rt_components_board_init();
  143. #endif
  144. }