drv_uart.c 9.2 KB

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  1. /*
  2. * Copyright (c) 2006-2020, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2020-04-16 bigmagic first version
  9. * 2020-05-26 bigmagic add other uart
  10. */
  11. #include <rthw.h>
  12. #include <rtthread.h>
  13. #include <rtdevice.h>
  14. #include "board.h"
  15. #include "drv_uart.h"
  16. #include "drv_gpio.h"
  17. #include <mmu.h>
  18. size_t uart0_addr = 0;
  19. size_t uart3_addr = 0;
  20. size_t uart4_addr = 0;
  21. size_t uart5_addr = 0;
  22. #ifdef RT_USING_UART0
  23. static struct rt_serial_device _serial0;
  24. #endif
  25. #ifdef RT_USING_UART1
  26. static struct rt_serial_device _serial1;
  27. #endif
  28. #ifdef RT_USING_UART3
  29. static struct rt_serial_device _serial3;
  30. #endif
  31. #ifdef RT_USING_UART4
  32. static struct rt_serial_device _serial4;
  33. #endif
  34. #ifdef RT_USING_UART5
  35. static struct rt_serial_device _serial5;
  36. #endif
  37. struct hw_uart_device
  38. {
  39. rt_ubase_t hw_base;
  40. rt_uint32_t irqno;
  41. };
  42. static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
  43. {
  44. struct hw_uart_device *uart;
  45. uint32_t bauddiv = (UART_REFERENCE_CLOCK / cfg->baud_rate)* 1000 / 16;
  46. uint32_t ibrd = bauddiv / 1000;
  47. RT_ASSERT(serial != RT_NULL);
  48. uart = (struct hw_uart_device *)serial->parent.user_data;
  49. if(uart->hw_base == AUX_BASE)
  50. {
  51. prev_raspi_pin_mode(GPIO_PIN_14, ALT5);
  52. prev_raspi_pin_mode(GPIO_PIN_15, ALT5);
  53. AUX_ENABLES(uart->hw_base) = 1; /* Enable UART1 */
  54. AUX_MU_IER_REG(uart->hw_base) = 0; /* Disable interrupt */
  55. AUX_MU_CNTL_REG(uart->hw_base) = 0; /* Disable Transmitter and Receiver */
  56. AUX_MU_LCR_REG(uart->hw_base) = 3; /* Works in 8-bit mode */
  57. AUX_MU_MCR_REG(uart->hw_base) = 0; /* Disable RTS */
  58. AUX_MU_IIR_REG(uart->hw_base) = 0xC6; /* Enable FIFO, Clear FIFO */
  59. AUX_MU_BAUD_REG(uart->hw_base) = 270; /* 115200 = system clock 250MHz / (8 * (baud + 1)), baud = 270 */
  60. AUX_MU_CNTL_REG(uart->hw_base) = 3; /* Enable Transmitter and Receiver */
  61. return RT_EOK;
  62. }
  63. if(uart->hw_base == uart0_addr)
  64. {
  65. prev_raspi_pin_mode(GPIO_PIN_14, ALT0);
  66. prev_raspi_pin_mode(GPIO_PIN_15, ALT0);
  67. }
  68. if(uart->hw_base == uart3_addr)
  69. {
  70. prev_raspi_pin_mode(GPIO_PIN_4, ALT4);
  71. prev_raspi_pin_mode(GPIO_PIN_5, ALT4);
  72. }
  73. if(uart->hw_base == uart4_addr)
  74. {
  75. prev_raspi_pin_mode(GPIO_PIN_8, ALT4);
  76. prev_raspi_pin_mode(GPIO_PIN_9, ALT4);
  77. }
  78. if(uart->hw_base == uart5_addr)
  79. {
  80. prev_raspi_pin_mode(GPIO_PIN_12, ALT4);
  81. prev_raspi_pin_mode(GPIO_PIN_13, ALT4);
  82. }
  83. PL011_REG_CR(uart->hw_base) = 0;/*Clear UART setting*/
  84. PL011_REG_LCRH(uart->hw_base) = 0;/*disable FIFO*/
  85. PL011_REG_IBRD(uart->hw_base) = ibrd;
  86. PL011_REG_FBRD(uart->hw_base) = (((bauddiv - ibrd * 1000) * 64 + 500) / 1000);
  87. PL011_REG_LCRH(uart->hw_base) = PL011_LCRH_WLEN_8;/*FIFO*/
  88. PL011_REG_CR(uart->hw_base) = PL011_CR_UARTEN | PL011_CR_TXE | PL011_CR_RXE;/*art enable, TX/RX enable*/
  89. return RT_EOK;
  90. }
  91. static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
  92. {
  93. struct hw_uart_device *uart;
  94. RT_ASSERT(serial != RT_NULL);
  95. uart = (struct hw_uart_device *)serial->parent.user_data;
  96. switch (cmd)
  97. {
  98. case RT_DEVICE_CTRL_CLR_INT:
  99. break;
  100. case RT_DEVICE_CTRL_SET_INT:
  101. /* enable rx irq */
  102. if(uart->hw_base == AUX_BASE)
  103. {
  104. AUX_MU_IER_REG(uart->hw_base) = 0x1;
  105. }
  106. else
  107. {
  108. PL011_REG_IMSC(uart->hw_base) |= PL011_IMSC_RXIM;
  109. }
  110. rt_hw_interrupt_umask(uart->irqno);
  111. break;
  112. }
  113. return RT_EOK;
  114. }
  115. static int uart_putc(struct rt_serial_device *serial, char c)
  116. {
  117. struct hw_uart_device *uart;
  118. RT_ASSERT(serial != RT_NULL);
  119. uart = (struct hw_uart_device *)serial->parent.user_data;
  120. if(uart->hw_base == AUX_BASE)
  121. {
  122. while (!(AUX_MU_LSR_REG(uart->hw_base) & 0x20));
  123. AUX_MU_IO_REG(uart->hw_base) = c;
  124. }
  125. else
  126. {
  127. while ((PL011_REG_FR(uart->hw_base) & PL011_FR_TXFF));
  128. PL011_REG_DR(uart->hw_base) = (uint8_t)c;
  129. }
  130. return 1;
  131. }
  132. static int uart_getc(struct rt_serial_device *serial)
  133. {
  134. int ch = -1;
  135. struct hw_uart_device *uart;
  136. RT_ASSERT(serial != RT_NULL);
  137. uart = (struct hw_uart_device *)serial->parent.user_data;
  138. if(uart->hw_base == AUX_BASE)
  139. {
  140. if ((AUX_MU_LSR_REG(uart->hw_base) & 0x01))
  141. {
  142. ch = AUX_MU_IO_REG(uart->hw_base) & 0xff;
  143. }
  144. }
  145. else
  146. {
  147. if((PL011_REG_FR(uart->hw_base) & PL011_FR_RXFE) == 0)
  148. {
  149. ch = PL011_REG_DR(uart->hw_base) & 0xff;
  150. }
  151. }
  152. return ch;
  153. }
  154. static const struct rt_uart_ops _uart_ops =
  155. {
  156. uart_configure,
  157. uart_control,
  158. uart_putc,
  159. uart_getc,
  160. };
  161. #ifdef RT_USING_UART1
  162. static void rt_hw_aux_uart_isr(int irqno, void *param)
  163. {
  164. struct rt_serial_device *serial = (struct rt_serial_device*)param;
  165. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
  166. }
  167. #endif
  168. static void rt_hw_uart_isr(int irqno, void *param)
  169. {
  170. #ifdef RT_USING_UART0
  171. if((PACTL_CS & IRQ_UART0) == IRQ_UART0)
  172. {
  173. PACTL_CS &= ~(IRQ_UART0);
  174. rt_hw_serial_isr(&_serial0, RT_SERIAL_EVENT_RX_IND);
  175. PL011_REG_ICR(uart0_addr) = PL011_INTERRUPT_RECEIVE;
  176. }
  177. #endif
  178. #ifdef RT_USING_UART3
  179. if((PACTL_CS & IRQ_UART3) == IRQ_UART3)
  180. {
  181. PACTL_CS &= ~(IRQ_UART3);
  182. rt_hw_serial_isr(&_serial3, RT_SERIAL_EVENT_RX_IND);
  183. PL011_REG_ICR(uart3_addr) = PL011_INTERRUPT_RECEIVE;
  184. }
  185. #endif
  186. #ifdef RT_USING_UART4
  187. if((PACTL_CS & IRQ_UART4) == IRQ_UART4)
  188. {
  189. PACTL_CS &= ~(IRQ_UART4);
  190. rt_hw_serial_isr(&_serial4, RT_SERIAL_EVENT_RX_IND);
  191. PL011_REG_ICR(uart4_addr) = PL011_INTERRUPT_RECEIVE;
  192. }
  193. #endif
  194. #ifdef RT_USING_UART5
  195. if((PACTL_CS & IRQ_UART5) == IRQ_UART5)
  196. {
  197. PACTL_CS &= ~(IRQ_UART5);
  198. rt_hw_serial_isr(&_serial5, RT_SERIAL_EVENT_RX_IND);
  199. PL011_REG_ICR(uart5_addr) = PL011_INTERRUPT_RECEIVE;
  200. }
  201. #endif
  202. }
  203. #ifdef RT_USING_UART0
  204. /* UART device driver structure */
  205. static struct hw_uart_device _uart0_device =
  206. {
  207. UART0_BASE,
  208. IRQ_PL011,
  209. };
  210. #endif
  211. #ifdef RT_USING_UART1
  212. /* UART device driver structure */
  213. static struct hw_uart_device _uart1_device =
  214. {
  215. AUX_BASE,
  216. IRQ_AUX_UART,
  217. };
  218. #endif
  219. #ifdef RT_USING_UART3
  220. static struct hw_uart_device _uart3_device =
  221. {
  222. UART3_BASE,
  223. IRQ_PL011,
  224. };
  225. #endif
  226. #ifdef RT_USING_UART4
  227. static struct hw_uart_device _uart4_device =
  228. {
  229. UART4_BASE,
  230. IRQ_PL011,
  231. };
  232. #endif
  233. #ifdef RT_USING_UART5
  234. static struct hw_uart_device _uart5_device =
  235. {
  236. UART5_BASE,
  237. IRQ_PL011,
  238. };
  239. #endif
  240. int rt_hw_uart_init(void)
  241. {
  242. struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
  243. #ifdef RT_USING_UART0
  244. struct hw_uart_device *uart0;
  245. uart0 = &_uart0_device;
  246. _serial0.ops = &_uart_ops;
  247. _serial0.config = config;
  248. uart0_addr = (size_t)rt_ioremap((void*)UART0_BASE, 0x1000);
  249. uart0->hw_base = uart0_addr;
  250. /* register UART0 device */
  251. rt_hw_serial_register(&_serial0, "uart0",
  252. RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
  253. uart0);
  254. rt_hw_interrupt_install(uart0->irqno, rt_hw_uart_isr, &_serial0, "uart0");
  255. #endif
  256. #ifdef RT_USING_UART1
  257. struct hw_uart_device *uart1;
  258. uart1 = &_uart1_device;
  259. _serial1.ops = &_uart_ops;
  260. _serial1.config = config;
  261. uart1->hw_base = (size_t)rt_ioremap((void*)AUX_BASE, 0x1000);
  262. /* register UART1 device */
  263. rt_hw_serial_register(&_serial1, "uart1",
  264. RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
  265. uart1);
  266. rt_hw_interrupt_install(uart1->irqno, rt_hw_aux_uart_isr, &_serial1, "uart1");
  267. #endif
  268. #ifdef RT_USING_UART3
  269. struct hw_uart_device *uart3;
  270. uart3 = &_uart3_device;
  271. _serial3.ops = &_uart_ops;
  272. _serial3.config = config;
  273. uart3_addr = (size_t)rt_ioremap((void*)UART3_BASE, 0x1000);
  274. uart3->hw_base = uart3_addr;
  275. /* register UART3 device */
  276. rt_hw_serial_register(&_serial3, "uart3",
  277. RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
  278. uart3);
  279. rt_hw_interrupt_install(uart3->irqno, rt_hw_uart_isr, &_serial3, "uart3");
  280. #endif
  281. #ifdef RT_USING_UART4
  282. struct hw_uart_device *uart4;
  283. uart4 = &_uart4_device;
  284. _serial4.ops = &_uart_ops;
  285. _serial4.config = config;
  286. uart4_addr = (size_t)rt_ioremap((void*)UART4_BASE, 0x1000);
  287. uart4->hw_base = uart4_addr;
  288. /* register UART4 device */
  289. rt_hw_serial_register(&_serial4, "uart4",
  290. RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
  291. uart4);
  292. rt_hw_interrupt_install(uart4->irqno, rt_hw_uart_isr, &_serial4, "uart4");
  293. #endif
  294. #ifdef RT_USING_UART5
  295. struct hw_uart_device *uart5;
  296. uart5 = &_uart5_device;
  297. _serial5.ops = &_uart_ops;
  298. _serial5.config = config;
  299. uart5_addr = (size_t)rt_ioremap((void*)UART5_BASE, 0x1000);
  300. uart5->hw_base = uart5_addr;
  301. /* register UART5 device */
  302. rt_hw_serial_register(&_serial5, "uart5",
  303. RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
  304. uart5);
  305. rt_hw_interrupt_install(uart5->irqno, rt_hw_uart_isr, &_serial5, "uart5");
  306. #endif
  307. return 0;
  308. }