drv_uart.c 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561
  1. /*
  2. * Copyright (c) 2019 Winner Microelectronics Co., Ltd.
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-09-15 flyingcys 1st version
  9. */
  10. #include <rtthread.h>
  11. #include <rtdevice.h>
  12. #include "board.h"
  13. #include "wm_io.h"
  14. #include "wm_uart.h"
  15. #include "wm_gpio_afsel.h"
  16. #include "wm_type_def.h"
  17. #include "wm_cpu.h"
  18. #include "drv_uart.h"
  19. #include "pin_map.h"
  20. #define WM600_UART0 (TLS_UART_REGS_T *) HR_UART0_BASE_ADDR
  21. #define WM600_UART1 (TLS_UART_REGS_T *) HR_UART1_BASE_ADDR
  22. #define WM600_UART2 (TLS_UART_REGS_T *) HR_UART2_BASE_ADDR
  23. static void wm_uart_reg_init(TLS_UART_REGS_T *UARTx)
  24. {
  25. RT_ASSERT(UARTx == WM600_UART0 || UARTx == WM600_UART1 || UARTx == WM600_UART2);
  26. if (UARTx == WM600_UART0)
  27. {
  28. /* disable auto flow control */
  29. tls_reg_write32(HR_UART0_FLOW_CTRL, 0);
  30. /* disable dma */
  31. tls_reg_write32(HR_UART0_DMA_CTRL, 0);
  32. /* one byte tx */
  33. tls_reg_write32(HR_UART0_FIFO_CTRL, 0);
  34. /* disable interrupt */
  35. tls_reg_write32(HR_UART0_INT_MASK, 0xFF);
  36. /* enable rx/timeout interrupt */
  37. tls_reg_write32(HR_UART0_INT_MASK, ~(3 << 2));
  38. }
  39. else if (UARTx == WM600_UART1)
  40. {
  41. /* 4 byte tx, 8 bytes rx */
  42. tls_reg_write32(HR_UART1_FIFO_CTRL, (0x01 << 2) | (0x02 << 4));
  43. /* enable rx timeout, disable rx dma, disable tx dma */
  44. tls_reg_write32(HR_UART1_DMA_CTRL, (8 << 3) | (1 << 2));
  45. /* enable rx/timeout interrupt */
  46. tls_reg_write32(HR_UART1_INT_MASK, ~(3 << 2));
  47. }
  48. else if (UARTx == WM600_UART2)
  49. {
  50. /* 4 byte tx, 8 bytes rx */
  51. tls_reg_write32(HR_UART2_FIFO_CTRL, (0x01 << 2) | (0x02 << 4));
  52. /* enable rx timeout, disable rx dma, disable tx dma */
  53. tls_reg_write32(HR_UART2_DMA_CTRL, (8 << 3) | (1 << 2));
  54. /* enable rx/timeout interrupt */
  55. tls_reg_write32(HR_UART2_INT_MASK, ~(3 << 2));
  56. UARTx->UR_LC &= ~(0x1000000);
  57. }
  58. }
  59. static void wm_uart_gpio_config(TLS_UART_REGS_T *UARTx)
  60. {
  61. #if defined(BSP_USING_UART1) || defined(BSP_USING_UART2)
  62. rt_int16_t gpio_pin;
  63. #endif
  64. RT_ASSERT(UARTx == WM600_UART0 || UARTx == WM600_UART1 || UARTx == WM600_UART2);
  65. if (UARTx == WM600_UART0)
  66. {
  67. /* UART0_TX-PA04 UART0_RX-PA05 */
  68. wm_uart0_tx_config(WM_IO_PA_04);
  69. wm_uart0_rx_config(WM_IO_PA_05);
  70. }
  71. #ifdef BSP_USING_UART1
  72. else if (UARTx == WM600_UART1)
  73. {
  74. gpio_pin = wm_get_pin(WM_UART1_RX_PIN);
  75. if (gpio_pin >= 0)
  76. {
  77. wm_uart1_rx_config((enum tls_io_name)gpio_pin);
  78. }
  79. gpio_pin = wm_get_pin(WM_UART1_TX_PIN);
  80. if (gpio_pin >= 0)
  81. {
  82. wm_uart1_tx_config((enum tls_io_name)gpio_pin);
  83. }
  84. }
  85. #endif
  86. #ifdef BSP_USING_UART2
  87. else if (UARTx == WM600_UART2)
  88. {
  89. gpio_pin = wm_get_pin(WM_UART2_RX_PIN);
  90. if (gpio_pin >= 0)
  91. {
  92. wm_uart2_rx_config((enum tls_io_name)gpio_pin);
  93. }
  94. gpio_pin = wm_get_pin(WM_UART2_TX_PIN);
  95. if (gpio_pin >= 0)
  96. {
  97. wm_uart2_tx_scio_config((enum tls_io_name)gpio_pin);
  98. }
  99. }
  100. #endif
  101. }
  102. static void wm_uart_irq_config(TLS_UART_REGS_T *UARTx)
  103. {
  104. RT_ASSERT(UARTx == WM600_UART0 || UARTx == WM600_UART1 || UARTx == WM600_UART2);
  105. /* config uart interrupt register */
  106. /* clear interrupt */
  107. UARTx->UR_INTS = 0xFFFFFFFF;
  108. /* enable interupt */
  109. UARTx->UR_INTM = 0x0;
  110. UARTx->UR_DMAC = (4UL << UDMA_RX_FIFO_TIMEOUT_SHIFT) | UDMA_RX_FIFO_TIMEOUT;
  111. /* config FIFO control */
  112. UARTx->UR_FIFOC = UFC_TX_FIFO_LVL_16_BYTE | UFC_RX_FIFO_LVL_16_BYTE | UFC_TX_FIFO_RESET | UFC_RX_FIFO_RESET;
  113. UARTx->UR_LC &= ~(ULCON_TX_EN | ULCON_RX_EN);
  114. UARTx->UR_LC |= ULCON_TX_EN | ULCON_RX_EN;
  115. }
  116. static int wm_uart_baudrate_set(TLS_UART_REGS_T *UARTx, u32 baudrate)
  117. {
  118. u32 value;
  119. u32 apbclk;
  120. tls_sys_clk sysclk;
  121. RT_ASSERT(UARTx == WM600_UART0 || UARTx == WM600_UART1 || UARTx == WM600_UART2);
  122. tls_sys_clk_get(&sysclk);
  123. apbclk = sysclk.apbclk * 1000000;
  124. value = (apbclk / (16 * baudrate) - 1) |
  125. (((apbclk % (baudrate * 16)) * 16 / (baudrate * 16)) << 16);
  126. UARTx->UR_BD = value;
  127. return WM_SUCCESS;
  128. }
  129. static int wm_uart_parity_set(TLS_UART_REGS_T *UARTx, TLS_UART_PMODE_T paritytype)
  130. {
  131. RT_ASSERT(UARTx == WM600_UART0 || UARTx == WM600_UART1 || UARTx == WM600_UART2);
  132. if (paritytype == TLS_UART_PMODE_DISABLED)
  133. UARTx->UR_LC &= ~ULCON_PMD_EN;
  134. else if (paritytype == TLS_UART_PMODE_EVEN)
  135. {
  136. UARTx->UR_LC &= ~ULCON_PMD_MASK;
  137. UARTx->UR_LC |= ULCON_PMD_EVEN;
  138. }
  139. else if (paritytype == TLS_UART_PMODE_ODD)
  140. {
  141. UARTx->UR_LC &= ~ULCON_PMD_MASK;
  142. UARTx->UR_LC |= ULCON_PMD_ODD;
  143. }
  144. else
  145. return WM_FAILED;
  146. return WM_SUCCESS;
  147. }
  148. static int wm_uart_stopbits_set(TLS_UART_REGS_T *UARTx, TLS_UART_STOPBITS_T stopbits)
  149. {
  150. RT_ASSERT(UARTx == WM600_UART0 || UARTx == WM600_UART1 || UARTx == WM600_UART2);
  151. if (stopbits == TLS_UART_TWO_STOPBITS)
  152. UARTx->UR_LC |= ULCON_STOP_2;
  153. else
  154. UARTx->UR_LC &= ~ULCON_STOP_2;
  155. return WM_SUCCESS;
  156. }
  157. static int wm_uart_databits_set(TLS_UART_REGS_T *UARTx, TLS_UART_CHSIZE_T charlength)
  158. {
  159. RT_ASSERT(UARTx == WM600_UART0 || UARTx == WM600_UART1 || UARTx == WM600_UART2);
  160. UARTx->UR_LC &= ~ULCON_WL_MASK;
  161. if (charlength == TLS_UART_CHSIZE_5BIT)
  162. UARTx->UR_LC |= ULCON_WL5;
  163. else if (charlength == TLS_UART_CHSIZE_6BIT)
  164. UARTx->UR_LC |= ULCON_WL6;
  165. else if (charlength == TLS_UART_CHSIZE_7BIT)
  166. UARTx->UR_LC |= ULCON_WL7;
  167. else if (charlength == TLS_UART_CHSIZE_8BIT)
  168. UARTx->UR_LC |= ULCON_WL8;
  169. else
  170. return WM_FAILED;
  171. return WM_SUCCESS;
  172. }
  173. static int wm_uart_flow_ctrl_set(TLS_UART_REGS_T *UARTx, TLS_UART_FLOW_CTRL_MODE_T flow_ctrl)
  174. {
  175. RT_ASSERT(UARTx == WM600_UART0 || UARTx == WM600_UART1 || UARTx == WM600_UART2);
  176. switch (flow_ctrl)
  177. {
  178. case TLS_UART_FLOW_CTRL_NONE:
  179. UARTx->UR_FC = 0;
  180. break;
  181. case TLS_UART_FLOW_CTRL_HARDWARE:
  182. UARTx->UR_FC = (1UL << 0) | (6UL << 2);
  183. break;
  184. default:
  185. break;
  186. }
  187. return WM_SUCCESS;
  188. }
  189. struct device_uart
  190. {
  191. TLS_UART_REGS_T volatile *uart_device;
  192. rt_uint32_t uart_irq_no;
  193. };
  194. static rt_err_t drv_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg);
  195. static rt_err_t drv_uart_control(struct rt_serial_device *serial, int cmd, void *arg);
  196. static int drv_uart_putc(struct rt_serial_device *serial, char c);
  197. static int drv_uart_getc(struct rt_serial_device *serial);
  198. static rt_size_t drv_uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction);
  199. const struct rt_uart_ops _uart_ops =
  200. {
  201. drv_uart_configure,
  202. drv_uart_control,
  203. drv_uart_putc,
  204. drv_uart_getc,
  205. drv_uart_dma_transmit
  206. };
  207. /*
  208. * UART interface
  209. */
  210. static rt_err_t drv_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
  211. {
  212. struct device_uart *uart;
  213. u32 baud_rate;
  214. TLS_UART_PMODE_T parity;
  215. TLS_UART_STOPBITS_T stop_bits;
  216. TLS_UART_CHSIZE_T data_bits;
  217. RT_ASSERT(serial != RT_NULL && cfg != RT_NULL);
  218. serial->config = *cfg;
  219. uart = (struct device_uart *)serial->parent.user_data;
  220. RT_ASSERT(uart != RT_NULL);
  221. switch (cfg->baud_rate)
  222. {
  223. case BAUD_RATE_2000000:
  224. case BAUD_RATE_921600:
  225. case BAUD_RATE_460800:
  226. case BAUD_RATE_230400:
  227. case BAUD_RATE_115200:
  228. case BAUD_RATE_57600:
  229. case BAUD_RATE_38400:
  230. case BAUD_RATE_19200:
  231. case BAUD_RATE_9600:
  232. case BAUD_RATE_4800:
  233. case BAUD_RATE_2400:
  234. baud_rate = cfg->baud_rate;
  235. break;
  236. default:
  237. rt_kprintf("baudrate set failed... default rate:115200\r\n");
  238. baud_rate = BAUD_RATE_115200;
  239. break;
  240. }
  241. wm_uart_baudrate_set((TLS_UART_REGS_T *)uart->uart_device, baud_rate);
  242. switch (cfg->parity)
  243. {
  244. case PARITY_ODD:
  245. parity = TLS_UART_PMODE_ODD;
  246. break;
  247. case PARITY_EVEN:
  248. parity = TLS_UART_PMODE_EVEN;
  249. break;
  250. case PARITY_NONE:
  251. default:
  252. parity = TLS_UART_PMODE_DISABLED;
  253. break;
  254. }
  255. wm_uart_parity_set((TLS_UART_REGS_T *)uart->uart_device, parity);
  256. switch (cfg->stop_bits)
  257. {
  258. case STOP_BITS_2:
  259. stop_bits = TLS_UART_TWO_STOPBITS;
  260. break;
  261. case STOP_BITS_1:
  262. default:
  263. stop_bits = TLS_UART_ONE_STOPBITS;
  264. break;
  265. }
  266. wm_uart_stopbits_set((TLS_UART_REGS_T *)uart->uart_device, stop_bits);
  267. switch (cfg->data_bits)
  268. {
  269. case DATA_BITS_5:
  270. data_bits = TLS_UART_CHSIZE_5BIT;
  271. break;
  272. case DATA_BITS_6:
  273. data_bits = TLS_UART_CHSIZE_6BIT;
  274. break;
  275. case DATA_BITS_7:
  276. data_bits = TLS_UART_CHSIZE_7BIT;
  277. break;
  278. case DATA_BITS_8:
  279. default:
  280. data_bits = TLS_UART_CHSIZE_8BIT;
  281. break;
  282. }
  283. wm_uart_databits_set((TLS_UART_REGS_T *)uart->uart_device, data_bits);
  284. wm_uart_flow_ctrl_set((TLS_UART_REGS_T *)uart->uart_device, TLS_UART_FLOW_CTRL_NONE);
  285. return (RT_EOK);
  286. }
  287. static rt_err_t drv_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
  288. {
  289. struct device_uart *uart;
  290. RT_ASSERT(serial != RT_NULL);
  291. uart = (struct device_uart *)serial->parent.user_data;
  292. RT_ASSERT(uart != RT_NULL);
  293. switch (cmd)
  294. {
  295. case RT_DEVICE_CTRL_CLR_INT:
  296. /* Disable the UART Interrupt */
  297. tls_irq_disable(uart->uart_irq_no);
  298. break;
  299. case RT_DEVICE_CTRL_SET_INT:
  300. /* Enable the UART Interrupt */
  301. tls_irq_enable(uart->uart_irq_no);
  302. break;
  303. }
  304. return (RT_EOK);
  305. }
  306. static int drv_uart_putc(struct rt_serial_device *serial, char c)
  307. {
  308. struct device_uart *uart;
  309. RT_ASSERT(serial != RT_NULL);
  310. uart = (struct device_uart *)serial->parent.user_data;
  311. RT_ASSERT(uart != RT_NULL);
  312. while (uart->uart_device->UR_FIFOS & 0x3F); /* wait THR is empty */
  313. uart->uart_device->UR_TXW = (char)c;
  314. return (1);
  315. }
  316. static int drv_uart_getc(struct rt_serial_device *serial)
  317. {
  318. int ch;
  319. struct device_uart *uart;
  320. RT_ASSERT(serial != RT_NULL);
  321. uart = (struct device_uart *)serial->parent.user_data;
  322. RT_ASSERT(uart != RT_NULL);
  323. ch = -1;
  324. if (uart->uart_device->UR_FIFOS & UFS_RX_FIFO_CNT_MASK)
  325. ch = (int)uart->uart_device->UR_RXW;
  326. return ch;
  327. }
  328. static rt_size_t drv_uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
  329. {
  330. return (0);
  331. }
  332. static void drv_uart_irq_handler(struct rt_serial_device *serial)
  333. {
  334. u32 intr_src;
  335. struct device_uart *uart;
  336. RT_ASSERT(serial != RT_NULL);
  337. uart = (struct device_uart *)serial->parent.user_data;
  338. RT_ASSERT(uart != RT_NULL);
  339. /* check interrupt status */
  340. intr_src = uart->uart_device->UR_INTS;
  341. uart->uart_device->UR_INTS = intr_src;
  342. if ((intr_src & UART_RX_INT_FLAG) && (0 == (uart->uart_device->UR_INTM & UIS_RX_FIFO)))
  343. {
  344. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
  345. }
  346. if (intr_src & UART_TX_INT_FLAG)
  347. {
  348. }
  349. if (intr_src & UIS_CTS_CHNG)
  350. {
  351. }
  352. }
  353. #ifdef BSP_USING_UART0
  354. static struct rt_serial_device serial0;
  355. static struct device_uart uart0 =
  356. {
  357. WM600_UART0,
  358. UART0_INT,
  359. };
  360. void UART0_IRQHandler(void)
  361. {
  362. /* enter interrupt */
  363. rt_interrupt_enter();
  364. drv_uart_irq_handler(&serial0);
  365. /* leave interrupt */
  366. rt_interrupt_leave();
  367. }
  368. #endif
  369. #ifdef BSP_USING_UART1
  370. static struct rt_serial_device serial1;
  371. static struct device_uart uart1 =
  372. {
  373. WM600_UART1,
  374. UART1_INT,
  375. };
  376. void UART1_IRQHandler(void)
  377. {
  378. /* enter interrupt */
  379. rt_interrupt_enter();
  380. drv_uart_irq_handler(&serial1);
  381. /* leave interrupt */
  382. rt_interrupt_leave();
  383. }
  384. #endif
  385. #ifdef BSP_USING_UART2
  386. static struct rt_serial_device serial2;
  387. static struct device_uart uart2 =
  388. {
  389. WM600_UART2,
  390. UART2_INT,
  391. };
  392. void UART2_IRQHandler(void)
  393. {
  394. /* enter interrupt */
  395. rt_interrupt_enter();
  396. drv_uart_irq_handler(&serial2);
  397. /* leave interrupt */
  398. rt_interrupt_leave();
  399. }
  400. #endif
  401. /*
  402. * UART Initiation
  403. */
  404. int wm_hw_uart_init(void)
  405. {
  406. struct rt_serial_device *serial;
  407. struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
  408. struct device_uart *uart;
  409. #ifdef BSP_USING_UART0
  410. {
  411. serial = &serial0;
  412. uart = &uart0;
  413. /* Init UART Hardware */
  414. wm_uart_gpio_config((TLS_UART_REGS_T *)uart->uart_device);
  415. wm_uart_reg_init((TLS_UART_REGS_T *)uart->uart_device);
  416. wm_uart_irq_config((TLS_UART_REGS_T *)uart->uart_device);
  417. serial->ops = &_uart_ops;
  418. serial->config = config;
  419. serial->config.baud_rate = 115200;
  420. rt_hw_serial_register(serial,
  421. "uart0",
  422. RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
  423. uart);
  424. }
  425. #endif /* BSP_USING_UART0 */
  426. #ifdef BSP_USING_UART1
  427. {
  428. serial = &serial1;
  429. uart = &uart1;
  430. /* Init UART Hardware */
  431. wm_uart_gpio_config((TLS_UART_REGS_T *)uart->uart_device);
  432. wm_uart_reg_init((TLS_UART_REGS_T *)uart->uart_device);
  433. wm_uart_irq_config((TLS_UART_REGS_T *)uart->uart_device);
  434. serial->ops = &_uart_ops;
  435. serial->config = config;
  436. serial->config.baud_rate = WM_UART1_BAUDRATE;
  437. rt_hw_serial_register(serial,
  438. "uart1",
  439. RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
  440. uart);
  441. }
  442. #endif /* BSP_USING_UART1 */
  443. #ifdef BSP_USING_UART2
  444. {
  445. serial = &serial2;
  446. uart = &uart2;
  447. /* Init UART Hardware */
  448. wm_uart_gpio_config((TLS_UART_REGS_T *)uart->uart_device);
  449. wm_uart_reg_init((TLS_UART_REGS_T *)uart->uart_device);
  450. wm_uart_irq_config((TLS_UART_REGS_T *)uart->uart_device);
  451. serial->ops = &_uart_ops;
  452. serial->config = config;
  453. serial->config.baud_rate = WM_UART2_BAUDRATE;
  454. rt_hw_serial_register(serial,
  455. "uart2",
  456. RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
  457. uart);
  458. }
  459. #endif /* BSP_USING_UART2 */
  460. return 0;
  461. }
  462. INIT_BOARD_EXPORT(wm_hw_uart_init);