cpu.c 8.7 KB

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  1. /*
  2. * Copyright (c) 2006-2019, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2011-09-15 Bernard first version
  9. * 2019-07-28 zdzn add smp support
  10. */
  11. #include <rthw.h>
  12. #include <rtthread.h>
  13. #include <board.h>
  14. #include "cp15.h"
  15. #define DBG_TAG "libcpu.aarch64.cpu"
  16. #define DBG_LVL DBG_INFO
  17. #include <rtdbg.h>
  18. #include <string.h>
  19. #include "cpu.h"
  20. #include "psci_api.h"
  21. void (*system_off)(void);
  22. #ifdef RT_USING_SMP
  23. void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock)
  24. {
  25. lock->slock = 0;
  26. }
  27. #define TICKET_SHIFT 16
  28. void rt_hw_spin_lock(rt_hw_spinlock_t *lock)
  29. {
  30. unsigned int tmp;
  31. struct __arch_tickets lockval, newval;
  32. asm volatile(
  33. /* Atomically increment the next ticket. */
  34. " prfm pstl1strm, %3\n"
  35. "1: ldaxr %w0, %3\n"
  36. " add %w1, %w0, %w5\n"
  37. " stxr %w2, %w1, %3\n"
  38. " cbnz %w2, 1b\n"
  39. /* Did we get the lock? */
  40. " eor %w1, %w0, %w0, ror #16\n"
  41. " cbz %w1, 3f\n"
  42. /*
  43. * No: spin on the owner. Send a local event to avoid missing an
  44. * unlock before the exclusive load.
  45. */
  46. " sevl\n"
  47. "2: wfe\n"
  48. " ldaxrh %w2, %4\n"
  49. " eor %w1, %w2, %w0, lsr #16\n"
  50. " cbnz %w1, 2b\n"
  51. /* We got the lock. Critical section starts here. */
  52. "3:"
  53. : "=&r"(lockval), "=&r"(newval), "=&r"(tmp), "+Q"(*lock)
  54. : "Q"(lock->tickets.owner), "I"(1 << TICKET_SHIFT)
  55. : "memory");
  56. rt_hw_dmb();
  57. }
  58. void rt_hw_spin_unlock(rt_hw_spinlock_t *lock)
  59. {
  60. rt_hw_dmb();
  61. asm volatile(
  62. " stlrh %w1, %0\n"
  63. : "=Q"(lock->tickets.owner)
  64. : "r"(lock->tickets.owner + 1)
  65. : "memory");
  66. }
  67. /**
  68. * cpu_ops_tbl contains cpu_ops_t for each cpu kernel observed,
  69. * given cpu logical id 'i', its cpu_ops_t is 'cpu_ops_tbl[i]'
  70. */
  71. struct cpu_ops_t *cpu_ops_tbl[RT_CPUS_NR];
  72. // _id_to_mpidr is a table translate logical id to mpid, which is a 64-bit value
  73. rt_uint64_t rt_cpu_mpidr_early[RT_CPUS_NR] RT_WEAK = {[0 ... RT_CPUS_NR - 1] = ID_ERROR};
  74. #ifdef RT_USING_FDT
  75. #include "dtb_node.h"
  76. struct dtb_node *_cpu_node[RT_CPUS_NR];
  77. #endif /* RT_USING_FDT */
  78. #define MPIDR_AFF_MASK 0x000000FF00FFFFFFul
  79. #define REPORT_ERR(retval) LOG_E("got error code %d in %s(), %s:%d", (retval), __func__, __FILE__, __LINE__)
  80. #define CHECK_RETVAL(retval) if (retval) {REPORT_ERR(retval);}
  81. static int _cpus_init_data_hardcoded(int num_cpus, rt_uint64_t *cpu_hw_ids, struct cpu_ops_t *cpu_ops[])
  82. {
  83. // load in cpu_hw_ids in cpuid_to_hwid,
  84. // cpu_ops to cpu_ops_tbl
  85. if (num_cpus > RT_CPUS_NR)
  86. {
  87. LOG_W("num_cpus (%d) greater than RT_CPUS_NR (%d)\n", num_cpus, RT_CPUS_NR);
  88. num_cpus = RT_CPUS_NR;
  89. }
  90. for (int i = 0; i < num_cpus; i++)
  91. {
  92. set_hwid(i, cpu_hw_ids[i]);
  93. cpu_ops_tbl[i] = cpu_ops[i];
  94. }
  95. return 0;
  96. }
  97. #ifdef RT_USING_FDT
  98. /** read ('size' * 4) bytes number from start, big-endian format */
  99. static rt_uint64_t _read_be_number(void *start, int size)
  100. {
  101. rt_uint64_t buf = 0;
  102. for (; size > 0; size--)
  103. buf = (buf << 32) | fdt32_to_cpu(*(uint32_t *)start++);
  104. return buf;
  105. }
  106. /** check device-type of the node, */
  107. static bool _node_is_cpu(struct dtb_node *node)
  108. {
  109. char *device_type = dtb_node_get_dtb_node_property_value(node, "device_type", NULL);
  110. if (device_type)
  111. {
  112. return !strcmp(device_type, "cpu");
  113. }
  114. return false;
  115. }
  116. static int _read_and_set_hwid(struct dtb_node *cpu, int *id_pool, int *pcpuid)
  117. {
  118. // size/address_cells is number of elements in reg array
  119. int size;
  120. static int address_cells, size_cells;
  121. if (!address_cells && !size_cells)
  122. dtb_node_get_dtb_node_cells(cpu, &address_cells, &size_cells);
  123. void *id_start = dtb_node_get_dtb_node_property_value(cpu, "reg", &size);
  124. rt_uint64_t mpid = _read_be_number(id_start, address_cells);
  125. *pcpuid = *id_pool;
  126. *id_pool = *id_pool + 1;
  127. set_hwid(*pcpuid, mpid);
  128. LOG_I("Using MPID 0x%lx as cpu %d", mpid, *pcpuid);
  129. // setting _cpu_node for cpu_init use
  130. _cpu_node[*pcpuid] = cpu;
  131. return 0;
  132. }
  133. static int _read_and_set_cpuops(struct dtb_node *cpu, int cpuid)
  134. {
  135. char *method = dtb_node_get_dtb_node_property_value(cpu, "enable-method", NULL);
  136. if (!method)
  137. {
  138. LOG_E("Cannot read method from cpu node");
  139. return -1;
  140. }
  141. struct cpu_ops_t *cpu_ops;
  142. if (!strcmp(method, cpu_ops_psci.method))
  143. {
  144. cpu_ops = &cpu_ops_psci;
  145. }
  146. else if (!strcmp(method, cpu_ops_spin_tbl.method))
  147. {
  148. cpu_ops = &cpu_ops_spin_tbl;
  149. }
  150. else
  151. {
  152. cpu_ops = RT_NULL;
  153. LOG_E("Not supported cpu_ops: %s", method);
  154. }
  155. cpu_ops_tbl[cpuid] = cpu_ops;
  156. LOG_D("Using boot method [%s] for cpu %d", cpu_ops->method, cpuid);
  157. return 0;
  158. }
  159. static int _cpus_init_data_fdt()
  160. {
  161. // cpuid_to_hwid and cpu_ops_tbl with fdt
  162. void *root = get_dtb_node_head();
  163. int id_pool = 0;
  164. int cpuid;
  165. struct dtb_node *cpus = dtb_node_get_dtb_node_by_path(root, "/cpus");
  166. // for each cpu node (device-type is cpu), read its mpid and set its cpuid_to_hwid
  167. for_each_node_child(cpus)
  168. {
  169. if (!_node_is_cpu(cpus))
  170. {
  171. continue;
  172. }
  173. if (id_pool > RT_CPUS_NR)
  174. {
  175. LOG_W("Reading more cpus from FDT than RT_CPUS_NR"
  176. "\n Parsing will not continue and only %d cpus will be used.", RT_CPUS_NR);
  177. break;
  178. }
  179. _read_and_set_hwid(cpus, &id_pool, &cpuid);
  180. _read_and_set_cpuops(cpus, cpuid);
  181. }
  182. return 0;
  183. }
  184. #endif /* RT_USING_FDT */
  185. /** init cpu with hardcoded infomation or parsing from FDT */
  186. static int _cpus_init(int num_cpus, rt_uint64_t *cpu_hw_ids, struct cpu_ops_t *cpu_ops[])
  187. {
  188. int retval;
  189. // first setup cpu_ops_tbl and cpuid_to_hwid
  190. if (num_cpus > 0)
  191. retval = _cpus_init_data_hardcoded(num_cpus, cpu_hw_ids, cpu_ops);
  192. else
  193. {
  194. retval = -1;
  195. #ifdef RT_USING_FDT
  196. retval = _cpus_init_data_fdt();
  197. #endif
  198. }
  199. if (retval)
  200. return retval;
  201. // using cpuid_to_hwid and cpu_ops_tbl to call method_init and cpu_init
  202. // assuming that cpuid 0 has already init
  203. for (int i = 1; i < RT_CPUS_NR; i++)
  204. {
  205. if (cpuid_to_hwid(i) == ID_ERROR)
  206. {
  207. LOG_E("Failed to find hardware id of CPU %d", i);
  208. continue;
  209. }
  210. if (cpu_ops_tbl[i] && cpu_ops_tbl[i]->cpu_init)
  211. {
  212. retval = cpu_ops_tbl[i]->cpu_init(i);
  213. CHECK_RETVAL(retval);
  214. }
  215. else
  216. {
  217. LOG_E("Failed to find cpu_init for cpu %d with cpu_ops[%p], cpu_ops->cpu_init[%p]"
  218. , cpuid_to_hwid(i), cpu_ops_tbl[i], cpu_ops_tbl[i] ? cpu_ops_tbl[i]->cpu_init : NULL);
  219. }
  220. }
  221. return 0;
  222. }
  223. static void _boot_secondary(void)
  224. {
  225. for (int i = 1; i < RT_CPUS_NR; i++)
  226. {
  227. int retval = -0xbad0; // mark no support operation
  228. if (cpu_ops_tbl[i] && cpu_ops_tbl[i]->cpu_boot)
  229. retval = cpu_ops_tbl[i]->cpu_boot(i);
  230. if (retval)
  231. {
  232. LOG_E("Failed to boot secondary CPU %d, error code %d", i, retval);
  233. } else {
  234. LOG_I("Secondary CPU %d booted", i);
  235. }
  236. }
  237. }
  238. RT_WEAK void rt_hw_secondary_cpu_up(void)
  239. {
  240. _boot_secondary();
  241. }
  242. /**
  243. * @brief boot cpu with hardcoded data
  244. *
  245. * @param num_cpus number of cpus
  246. * @param cpu_hw_ids each element represents a hwid of cpu[i]
  247. * @param cpu_ops each element represents a pointer to cpu_ops of cpu[i]
  248. * @return int 0 on success,
  249. */
  250. int rt_hw_cpu_boot_secondary(int num_cpus, rt_uint64_t *cpu_hw_ids, struct cpu_ops_t *cpu_ops[])
  251. {
  252. int retval = 0;
  253. if (num_cpus < 1 || !cpu_hw_ids || !cpu_ops)
  254. return -1;
  255. retval = _cpus_init(num_cpus, cpu_hw_ids, cpu_ops);
  256. CHECK_RETVAL(retval);
  257. return retval;
  258. }
  259. #define CPU_INIT_USING_FDT 0,0,0
  260. /**
  261. * @brief Initialize cpu infomation from fdt
  262. *
  263. * @return int
  264. */
  265. int rt_hw_cpu_init()
  266. {
  267. #ifdef RT_USING_FDT
  268. return _cpus_init(CPU_INIT_USING_FDT);
  269. #else
  270. LOG_E("CPU init failed since RT_USING_FDT was not defined");
  271. return -0xa; /* no fdt support */
  272. #endif /* RT_USING_FDT */
  273. }
  274. RT_WEAK void rt_hw_secondary_cpu_idle_exec(void)
  275. {
  276. asm volatile("wfe" ::
  277. : "memory", "cc");
  278. }
  279. #endif /*RT_USING_SMP*/
  280. /**
  281. * @addtogroup ARM CPU
  282. */
  283. /*@{*/
  284. /** shutdown CPU is used as system shutdown currently */
  285. void rt_hw_cpu_shutdown()
  286. {
  287. rt_uint32_t level;
  288. rt_kprintf("shutdown...\n");
  289. if (system_off)
  290. system_off();
  291. LOG_E("system shutdown failed");
  292. level = rt_hw_interrupt_disable();
  293. while (level)
  294. {
  295. RT_ASSERT(0);
  296. }
  297. }
  298. MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_shutdown, shutdown, shutdown machine);
  299. /*@}*/