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efm32gg_dac.h

efm32gg_dac.h 85 KB
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  1. /**************************************************************************//**
    2. 

  2.  * @file
    3. 

  3.  * @brief efm32gg_dac Register and Bit Field definitions
    4. 

  4.  * @author Energy Micro AS
    5. 

  5.  * @version 3.0.0
    6. 

  6.  ******************************************************************************
    7. 

  7.  * @section License
    8. 

  8.  * <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
    9. 

  9.  ******************************************************************************
    10. 

  10.  *
    11. 

  11.  * Permission is granted to anyone to use this software for any purpose,
    12. 

  12.  * including commercial applications, and to alter it and redistribute it
    13. 

  13.  * freely, subject to the following restrictions:
    14. 

  14.  *
    15. 

  15.  * 1. The origin of this software must not be misrepresented; you must not
    16. 

  16.  *    claim that you wrote the original software.
    17. 

  17.  * 2. Altered source versions must be plainly marked as such, and must not be
    18. 

  18.  *    misrepresented as being the original software.
    19. 

  19.  * 3. This notice may not be removed or altered from any source distribution.
    20. 

  20.  *
    21. 

  21.  * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
    22. 

  22.  * obligation to support this Software. Energy Micro AS is providing the
    23. 

  23.  * Software "AS IS", with no express or implied warranties of any kind,
    24. 

  24.  * including, but not limited to, any implied warranties of merchantability
    25. 

  25.  * or fitness for any particular purpose or warranties against infringement
    26. 

  26.  * of any proprietary rights of a third party.
    27. 

  27.  *
    28. 

  28.  * Energy Micro AS will not be liable for any consequential, incidental, or
    29. 

  29.  * special damages, or any other relief, or for any claim by any third party,
    30. 

  30.  * arising from your use of this Software.
    31. 

  31.  *
    32. 

  32.  *****************************************************************************/
    33. 

  33. /**************************************************************************//**
    34. 

  34.  * @defgroup EFM32GG_DAC
    35. 

  35.  * @{
    36. 

  36.  * @brief EFM32GG_DAC Register Declaration
    37. 

  37.  *****************************************************************************/
    38. 

  38. typedef struct
    39. 

  39. {
    40. 

  40.   __IO uint32_t CTRL;         /**< Control Register  */
    41. 

  41.   __I uint32_t  STATUS;       /**< Status Register  */
    42. 

  42.   __IO uint32_t CH0CTRL;      /**< Channel 0 Control Register  */
    43. 

  43.   __IO uint32_t CH1CTRL;      /**< Channel 1 Control Register  */
    44. 

  44.   __IO uint32_t IEN;          /**< Interrupt Enable Register  */
    45. 

  45.   __I uint32_t  IF;           /**< Interrupt Flag Register  */
    46. 

  46.   __IO uint32_t IFS;          /**< Interrupt Flag Set Register  */
    47. 

  47.   __IO uint32_t IFC;          /**< Interrupt Flag Clear Register  */
    48. 

  48.   __IO uint32_t CH0DATA;      /**< Channel 0 Data Register  */
    49. 

  49.   __IO uint32_t CH1DATA;      /**< Channel 1 Data Register  */
    50. 

  50.   __IO uint32_t COMBDATA;     /**< Combined Data Register  */
    51. 

  51.   __IO uint32_t CAL;          /**< Calibration Register  */
    52. 

  52.   __IO uint32_t BIASPROG;     /**< Bias Programming Register  */
    53. 

  53.   uint32_t      RESERVED0[8]; /**< Reserved for future use **/
    54. 

  54.   __IO uint32_t OPACTRL;      /**< Operational Amplifier Control Register  */
    55. 

  55.   __IO uint32_t OPAOFFSET;    /**< Operational Amplifier Offset Register  */
    56. 

  56.   __IO uint32_t OPA0MUX;      /**< Operational Amplifier Mux Configuration Register  */
    57. 

  57.   __IO uint32_t OPA1MUX;      /**< Operational Amplifier Mux Configuration Register  */
    58. 

  58.   __IO uint32_t OPA2MUX;      /**< Operational Amplifier Mux Configuration Register  */
    59. 

  59. } DAC_TypeDef;                /** @} */
    60. 

  60. 

  61. /**************************************************************************//**
    62. 

  62.  * @defgroup EFM32GG_DAC_BitFields
    63. 

  63.  * @{
    64. 

  64.  *****************************************************************************/
    65. 

  65. 

  66. /* Bit fields for DAC CTRL */
    67. 

  67. #define _DAC_CTRL_RESETVALUE                  0x00000010UL                         /**< Default value for DAC_CTRL */
    68. 

  68. #define _DAC_CTRL_MASK                        0x0037D3FFUL                         /**< Mask for DAC_CTRL */
    69. 

  69. #define DAC_CTRL_DIFF                         (0x1UL << 0)                         /**< Differential Mode */
    70. 

  70. #define _DAC_CTRL_DIFF_SHIFT                  0                                    /**< Shift value for DAC_DIFF */
    71. 

  71. #define _DAC_CTRL_DIFF_MASK                   0x1UL                                /**< Bit mask for DAC_DIFF */
    72. 

  72. #define _DAC_CTRL_DIFF_DEFAULT                0x00000000UL                         /**< Mode DEFAULT for DAC_CTRL */
    73. 

  73. #define DAC_CTRL_DIFF_DEFAULT                 (_DAC_CTRL_DIFF_DEFAULT << 0)        /**< Shifted mode DEFAULT for DAC_CTRL */
    74. 

  74. #define DAC_CTRL_SINEMODE                     (0x1UL << 1)                         /**< Sine Mode */
    75. 

  75. #define _DAC_CTRL_SINEMODE_SHIFT              1                                    /**< Shift value for DAC_SINEMODE */
    76. 

  76. #define _DAC_CTRL_SINEMODE_MASK               0x2UL                                /**< Bit mask for DAC_SINEMODE */
    77. 

  77. #define _DAC_CTRL_SINEMODE_DEFAULT            0x00000000UL                         /**< Mode DEFAULT for DAC_CTRL */
    78. 

  78. #define DAC_CTRL_SINEMODE_DEFAULT             (_DAC_CTRL_SINEMODE_DEFAULT << 1)    /**< Shifted mode DEFAULT for DAC_CTRL */
    79. 

  79. #define _DAC_CTRL_CONVMODE_SHIFT              2                                    /**< Shift value for DAC_CONVMODE */
    80. 

  80. #define _DAC_CTRL_CONVMODE_MASK               0xCUL                                /**< Bit mask for DAC_CONVMODE */
    81. 

  81. #define _DAC_CTRL_CONVMODE_DEFAULT            0x00000000UL                         /**< Mode DEFAULT for DAC_CTRL */
    82. 

  82. #define _DAC_CTRL_CONVMODE_CONTINUOUS         0x00000000UL                         /**< Mode CONTINUOUS for DAC_CTRL */
    83. 

  83. #define _DAC_CTRL_CONVMODE_SAMPLEHOLD         0x00000001UL                         /**< Mode SAMPLEHOLD for DAC_CTRL */
    84. 

  84. #define _DAC_CTRL_CONVMODE_SAMPLEOFF          0x00000002UL                         /**< Mode SAMPLEOFF for DAC_CTRL */
    85. 

  85. #define DAC_CTRL_CONVMODE_DEFAULT             (_DAC_CTRL_CONVMODE_DEFAULT << 2)    /**< Shifted mode DEFAULT for DAC_CTRL */
    86. 

  86. #define DAC_CTRL_CONVMODE_CONTINUOUS          (_DAC_CTRL_CONVMODE_CONTINUOUS << 2) /**< Shifted mode CONTINUOUS for DAC_CTRL */
    87. 

  87. #define DAC_CTRL_CONVMODE_SAMPLEHOLD          (_DAC_CTRL_CONVMODE_SAMPLEHOLD << 2) /**< Shifted mode SAMPLEHOLD for DAC_CTRL */
    88. 

  88. #define DAC_CTRL_CONVMODE_SAMPLEOFF           (_DAC_CTRL_CONVMODE_SAMPLEOFF << 2)  /**< Shifted mode SAMPLEOFF for DAC_CTRL */
    89. 

  89. #define _DAC_CTRL_OUTMODE_SHIFT               4                                    /**< Shift value for DAC_OUTMODE */
    90. 

  90. #define _DAC_CTRL_OUTMODE_MASK                0x30UL                               /**< Bit mask for DAC_OUTMODE */
    91. 

  91. #define _DAC_CTRL_OUTMODE_DISABLE             0x00000000UL                         /**< Mode DISABLE for DAC_CTRL */
    92. 

  92. #define _DAC_CTRL_OUTMODE_DEFAULT             0x00000001UL                         /**< Mode DEFAULT for DAC_CTRL */
    93. 

  93. #define _DAC_CTRL_OUTMODE_PIN                 0x00000001UL                         /**< Mode PIN for DAC_CTRL */
    94. 

  94. #define _DAC_CTRL_OUTMODE_ADC                 0x00000002UL                         /**< Mode ADC for DAC_CTRL */
    95. 

  95. #define _DAC_CTRL_OUTMODE_PINADC              0x00000003UL                         /**< Mode PINADC for DAC_CTRL */
    96. 

  96. #define DAC_CTRL_OUTMODE_DISABLE              (_DAC_CTRL_OUTMODE_DISABLE << 4)     /**< Shifted mode DISABLE for DAC_CTRL */
    97. 

  97. #define DAC_CTRL_OUTMODE_DEFAULT              (_DAC_CTRL_OUTMODE_DEFAULT << 4)     /**< Shifted mode DEFAULT for DAC_CTRL */
    98. 

  98. #define DAC_CTRL_OUTMODE_PIN                  (_DAC_CTRL_OUTMODE_PIN << 4)         /**< Shifted mode PIN for DAC_CTRL */
    99. 

  99. #define DAC_CTRL_OUTMODE_ADC                  (_DAC_CTRL_OUTMODE_ADC << 4)         /**< Shifted mode ADC for DAC_CTRL */
    100. 

  100. #define DAC_CTRL_OUTMODE_PINADC               (_DAC_CTRL_OUTMODE_PINADC << 4)      /**< Shifted mode PINADC for DAC_CTRL */
    101. 

  101. #define DAC_CTRL_OUTENPRS                     (0x1UL << 6)                         /**< PRS Controlled Output Enable */
    102. 

  102. #define _DAC_CTRL_OUTENPRS_SHIFT              6                                    /**< Shift value for DAC_OUTENPRS */
    103. 

  103. #define _DAC_CTRL_OUTENPRS_MASK               0x40UL                               /**< Bit mask for DAC_OUTENPRS */
    104. 

  104. #define _DAC_CTRL_OUTENPRS_DEFAULT            0x00000000UL                         /**< Mode DEFAULT for DAC_CTRL */
    105. 

  105. #define DAC_CTRL_OUTENPRS_DEFAULT             (_DAC_CTRL_OUTENPRS_DEFAULT << 6)    /**< Shifted mode DEFAULT for DAC_CTRL */
    106. 

  106. #define DAC_CTRL_CH0PRESCRST                  (0x1UL << 7)                         /**< Channel 0 Start Reset Prescaler */
    107. 

  107. #define _DAC_CTRL_CH0PRESCRST_SHIFT           7                                    /**< Shift value for DAC_CH0PRESCRST */
    108. 

  108. #define _DAC_CTRL_CH0PRESCRST_MASK            0x80UL                               /**< Bit mask for DAC_CH0PRESCRST */
    109. 

  109. #define _DAC_CTRL_CH0PRESCRST_DEFAULT         0x00000000UL                         /**< Mode DEFAULT for DAC_CTRL */
    110. 

  110. #define DAC_CTRL_CH0PRESCRST_DEFAULT          (_DAC_CTRL_CH0PRESCRST_DEFAULT << 7) /**< Shifted mode DEFAULT for DAC_CTRL */
    111. 

  111. #define _DAC_CTRL_REFSEL_SHIFT                8                                    /**< Shift value for DAC_REFSEL */
    112. 

  112. #define _DAC_CTRL_REFSEL_MASK                 0x300UL                              /**< Bit mask for DAC_REFSEL */
    113. 

  113. #define _DAC_CTRL_REFSEL_DEFAULT              0x00000000UL                         /**< Mode DEFAULT for DAC_CTRL */
    114. 

  114. #define _DAC_CTRL_REFSEL_1V25                 0x00000000UL                         /**< Mode 1V25 for DAC_CTRL */
    115. 

  115. #define _DAC_CTRL_REFSEL_2V5                  0x00000001UL                         /**< Mode 2V5 for DAC_CTRL */
    116. 

  116. #define _DAC_CTRL_REFSEL_VDD                  0x00000002UL                         /**< Mode VDD for DAC_CTRL */
    117. 

  117. #define DAC_CTRL_REFSEL_DEFAULT               (_DAC_CTRL_REFSEL_DEFAULT << 8)      /**< Shifted mode DEFAULT for DAC_CTRL */
    118. 

  118. #define DAC_CTRL_REFSEL_1V25                  (_DAC_CTRL_REFSEL_1V25 << 8)         /**< Shifted mode 1V25 for DAC_CTRL */
    119. 

  119. #define DAC_CTRL_REFSEL_2V5                   (_DAC_CTRL_REFSEL_2V5 << 8)          /**< Shifted mode 2V5 for DAC_CTRL */
    120. 

  120. #define DAC_CTRL_REFSEL_VDD                   (_DAC_CTRL_REFSEL_VDD << 8)          /**< Shifted mode VDD for DAC_CTRL */
    121. 

  121. #define _DAC_CTRL_PRESC_SHIFT                 16                                   /**< Shift value for DAC_PRESC */
    122. 

  122. #define _DAC_CTRL_PRESC_MASK                  0x70000UL                            /**< Bit mask for DAC_PRESC */
    123. 

  123. #define _DAC_CTRL_PRESC_DEFAULT               0x00000000UL                         /**< Mode DEFAULT for DAC_CTRL */
    124. 

  124. #define _DAC_CTRL_PRESC_NODIVISION            0x00000000UL                         /**< Mode NODIVISION for DAC_CTRL */
    125. 

  125. #define DAC_CTRL_PRESC_DEFAULT                (_DAC_CTRL_PRESC_DEFAULT << 16)      /**< Shifted mode DEFAULT for DAC_CTRL */
    126. 

  126. #define DAC_CTRL_PRESC_NODIVISION             (_DAC_CTRL_PRESC_NODIVISION << 16)   /**< Shifted mode NODIVISION for DAC_CTRL */
    127. 

  127. #define _DAC_CTRL_REFRSEL_SHIFT               20                                   /**< Shift value for DAC_REFRSEL */
    128. 

  128. #define _DAC_CTRL_REFRSEL_MASK                0x300000UL                           /**< Bit mask for DAC_REFRSEL */
    129. 

  129. #define _DAC_CTRL_REFRSEL_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for DAC_CTRL */
    130. 

  130. #define _DAC_CTRL_REFRSEL_8CYCLES             0x00000000UL                         /**< Mode 8CYCLES for DAC_CTRL */
    131. 

  131. #define _DAC_CTRL_REFRSEL_16CYCLES            0x00000001UL                         /**< Mode 16CYCLES for DAC_CTRL */
    132. 

  132. #define _DAC_CTRL_REFRSEL_32CYCLES            0x00000002UL                         /**< Mode 32CYCLES for DAC_CTRL */
    133. 

  133. #define _DAC_CTRL_REFRSEL_64CYCLES            0x00000003UL                         /**< Mode 64CYCLES for DAC_CTRL */
    134. 

  134. #define DAC_CTRL_REFRSEL_DEFAULT              (_DAC_CTRL_REFRSEL_DEFAULT << 20)    /**< Shifted mode DEFAULT for DAC_CTRL */
    135. 

  135. #define DAC_CTRL_REFRSEL_8CYCLES              (_DAC_CTRL_REFRSEL_8CYCLES << 20)    /**< Shifted mode 8CYCLES for DAC_CTRL */
    136. 

  136. #define DAC_CTRL_REFRSEL_16CYCLES             (_DAC_CTRL_REFRSEL_16CYCLES << 20)   /**< Shifted mode 16CYCLES for DAC_CTRL */
    137. 

  137. #define DAC_CTRL_REFRSEL_32CYCLES             (_DAC_CTRL_REFRSEL_32CYCLES << 20)   /**< Shifted mode 32CYCLES for DAC_CTRL */
    138. 

  138. #define DAC_CTRL_REFRSEL_64CYCLES             (_DAC_CTRL_REFRSEL_64CYCLES << 20)   /**< Shifted mode 64CYCLES for DAC_CTRL */
    139. 

  139. 

  140. /* Bit fields for DAC STATUS */
    141. 

  141. #define _DAC_STATUS_RESETVALUE                0x00000000UL                     /**< Default value for DAC_STATUS */
    142. 

  142. #define _DAC_STATUS_MASK                      0x00000003UL                     /**< Mask for DAC_STATUS */
    143. 

  143. #define DAC_STATUS_CH0DV                      (0x1UL << 0)                     /**< Channel 0 Data Valid */
    144. 

  144. #define _DAC_STATUS_CH0DV_SHIFT               0                                /**< Shift value for DAC_CH0DV */
    145. 

  145. #define _DAC_STATUS_CH0DV_MASK                0x1UL                            /**< Bit mask for DAC_CH0DV */
    146. 

  146. #define _DAC_STATUS_CH0DV_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for DAC_STATUS */
    147. 

  147. #define DAC_STATUS_CH0DV_DEFAULT              (_DAC_STATUS_CH0DV_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_STATUS */
    148. 

  148. #define DAC_STATUS_CH1DV                      (0x1UL << 1)                     /**< Channel 1 Data Valid */
    149. 

  149. #define _DAC_STATUS_CH1DV_SHIFT               1                                /**< Shift value for DAC_CH1DV */
    150. 

  150. #define _DAC_STATUS_CH1DV_MASK                0x2UL                            /**< Bit mask for DAC_CH1DV */
    151. 

  151. #define _DAC_STATUS_CH1DV_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for DAC_STATUS */
    152. 

  152. #define DAC_STATUS_CH1DV_DEFAULT              (_DAC_STATUS_CH1DV_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_STATUS */
    153. 

  153. 

  154. /* Bit fields for DAC CH0CTRL */
    155. 

  155. #define _DAC_CH0CTRL_RESETVALUE               0x00000000UL                       /**< Default value for DAC_CH0CTRL */
    156. 

  156. #define _DAC_CH0CTRL_MASK                     0x000000F7UL                       /**< Mask for DAC_CH0CTRL */
    157. 

  157. #define DAC_CH0CTRL_EN                        (0x1UL << 0)                       /**< Channel 0 Enable */
    158. 

  158. #define _DAC_CH0CTRL_EN_SHIFT                 0                                  /**< Shift value for DAC_EN */
    159. 

  159. #define _DAC_CH0CTRL_EN_MASK                  0x1UL                              /**< Bit mask for DAC_EN */
    160. 

  160. #define _DAC_CH0CTRL_EN_DEFAULT               0x00000000UL                       /**< Mode DEFAULT for DAC_CH0CTRL */
    161. 

  161. #define DAC_CH0CTRL_EN_DEFAULT                (_DAC_CH0CTRL_EN_DEFAULT << 0)     /**< Shifted mode DEFAULT for DAC_CH0CTRL */
    162. 

  162. #define DAC_CH0CTRL_REFREN                    (0x1UL << 1)                       /**< Channel 0 Automatic Refresh Enable */
    163. 

  163. #define _DAC_CH0CTRL_REFREN_SHIFT             1                                  /**< Shift value for DAC_REFREN */
    164. 

  164. #define _DAC_CH0CTRL_REFREN_MASK              0x2UL                              /**< Bit mask for DAC_REFREN */
    165. 

  165. #define _DAC_CH0CTRL_REFREN_DEFAULT           0x00000000UL                       /**< Mode DEFAULT for DAC_CH0CTRL */
    166. 

  166. #define DAC_CH0CTRL_REFREN_DEFAULT            (_DAC_CH0CTRL_REFREN_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_CH0CTRL */
    167. 

  167. #define DAC_CH0CTRL_PRSEN                     (0x1UL << 2)                       /**< Channel 0 PRS Trigger Enable */
    168. 

  168. #define _DAC_CH0CTRL_PRSEN_SHIFT              2                                  /**< Shift value for DAC_PRSEN */
    169. 

  169. #define _DAC_CH0CTRL_PRSEN_MASK               0x4UL                              /**< Bit mask for DAC_PRSEN */
    170. 

  170. #define _DAC_CH0CTRL_PRSEN_DEFAULT            0x00000000UL                       /**< Mode DEFAULT for DAC_CH0CTRL */
    171. 

  171. #define DAC_CH0CTRL_PRSEN_DEFAULT             (_DAC_CH0CTRL_PRSEN_DEFAULT << 2)  /**< Shifted mode DEFAULT for DAC_CH0CTRL */
    172. 

  172. #define _DAC_CH0CTRL_PRSSEL_SHIFT             4                                  /**< Shift value for DAC_PRSSEL */
    173. 

  173. #define _DAC_CH0CTRL_PRSSEL_MASK              0xF0UL                             /**< Bit mask for DAC_PRSSEL */
    174. 

  174. #define _DAC_CH0CTRL_PRSSEL_DEFAULT           0x00000000UL                       /**< Mode DEFAULT for DAC_CH0CTRL */
    175. 

  175. #define _DAC_CH0CTRL_PRSSEL_PRSCH0            0x00000000UL                       /**< Mode PRSCH0 for DAC_CH0CTRL */
    176. 

  176. #define _DAC_CH0CTRL_PRSSEL_PRSCH1            0x00000001UL                       /**< Mode PRSCH1 for DAC_CH0CTRL */
    177. 

  177. #define _DAC_CH0CTRL_PRSSEL_PRSCH2            0x00000002UL                       /**< Mode PRSCH2 for DAC_CH0CTRL */
    178. 

  178. #define _DAC_CH0CTRL_PRSSEL_PRSCH3            0x00000003UL                       /**< Mode PRSCH3 for DAC_CH0CTRL */
    179. 

  179. #define _DAC_CH0CTRL_PRSSEL_PRSCH4            0x00000004UL                       /**< Mode PRSCH4 for DAC_CH0CTRL */
    180. 

  180. #define _DAC_CH0CTRL_PRSSEL_PRSCH5            0x00000005UL                       /**< Mode PRSCH5 for DAC_CH0CTRL */
    181. 

  181. #define _DAC_CH0CTRL_PRSSEL_PRSCH6            0x00000006UL                       /**< Mode PRSCH6 for DAC_CH0CTRL */
    182. 

  182. #define _DAC_CH0CTRL_PRSSEL_PRSCH7            0x00000007UL                       /**< Mode PRSCH7 for DAC_CH0CTRL */
    183. 

  183. #define _DAC_CH0CTRL_PRSSEL_PRSCH8            0x00000008UL                       /**< Mode PRSCH8 for DAC_CH0CTRL */
    184. 

  184. #define _DAC_CH0CTRL_PRSSEL_PRSCH9            0x00000009UL                       /**< Mode PRSCH9 for DAC_CH0CTRL */
    185. 

  185. #define _DAC_CH0CTRL_PRSSEL_PRSCH10           0x0000000AUL                       /**< Mode PRSCH10 for DAC_CH0CTRL */
    186. 

  186. #define _DAC_CH0CTRL_PRSSEL_PRSCH11           0x0000000BUL                       /**< Mode PRSCH11 for DAC_CH0CTRL */
    187. 

  187. #define DAC_CH0CTRL_PRSSEL_DEFAULT            (_DAC_CH0CTRL_PRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_CH0CTRL */
    188. 

  188. #define DAC_CH0CTRL_PRSSEL_PRSCH0             (_DAC_CH0CTRL_PRSSEL_PRSCH0 << 4)  /**< Shifted mode PRSCH0 for DAC_CH0CTRL */
    189. 

  189. #define DAC_CH0CTRL_PRSSEL_PRSCH1             (_DAC_CH0CTRL_PRSSEL_PRSCH1 << 4)  /**< Shifted mode PRSCH1 for DAC_CH0CTRL */
    190. 

  190. #define DAC_CH0CTRL_PRSSEL_PRSCH2             (_DAC_CH0CTRL_PRSSEL_PRSCH2 << 4)  /**< Shifted mode PRSCH2 for DAC_CH0CTRL */
    191. 

  191. #define DAC_CH0CTRL_PRSSEL_PRSCH3             (_DAC_CH0CTRL_PRSSEL_PRSCH3 << 4)  /**< Shifted mode PRSCH3 for DAC_CH0CTRL */
    192. 

  192. #define DAC_CH0CTRL_PRSSEL_PRSCH4             (_DAC_CH0CTRL_PRSSEL_PRSCH4 << 4)  /**< Shifted mode PRSCH4 for DAC_CH0CTRL */
    193. 

  193. #define DAC_CH0CTRL_PRSSEL_PRSCH5             (_DAC_CH0CTRL_PRSSEL_PRSCH5 << 4)  /**< Shifted mode PRSCH5 for DAC_CH0CTRL */
    194. 

  194. #define DAC_CH0CTRL_PRSSEL_PRSCH6             (_DAC_CH0CTRL_PRSSEL_PRSCH6 << 4)  /**< Shifted mode PRSCH6 for DAC_CH0CTRL */
    195. 

  195. #define DAC_CH0CTRL_PRSSEL_PRSCH7             (_DAC_CH0CTRL_PRSSEL_PRSCH7 << 4)  /**< Shifted mode PRSCH7 for DAC_CH0CTRL */
    196. 

  196. #define DAC_CH0CTRL_PRSSEL_PRSCH8             (_DAC_CH0CTRL_PRSSEL_PRSCH8 << 4)  /**< Shifted mode PRSCH8 for DAC_CH0CTRL */
    197. 

  197. #define DAC_CH0CTRL_PRSSEL_PRSCH9             (_DAC_CH0CTRL_PRSSEL_PRSCH9 << 4)  /**< Shifted mode PRSCH9 for DAC_CH0CTRL */
    198. 

  198. #define DAC_CH0CTRL_PRSSEL_PRSCH10            (_DAC_CH0CTRL_PRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for DAC_CH0CTRL */
    199. 

  199. #define DAC_CH0CTRL_PRSSEL_PRSCH11            (_DAC_CH0CTRL_PRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for DAC_CH0CTRL */
    200. 

  200. 

  201. /* Bit fields for DAC CH1CTRL */
    202. 

  202. #define _DAC_CH1CTRL_RESETVALUE               0x00000000UL                       /**< Default value for DAC_CH1CTRL */
    203. 

  203. #define _DAC_CH1CTRL_MASK                     0x000000F7UL                       /**< Mask for DAC_CH1CTRL */
    204. 

  204. #define DAC_CH1CTRL_EN                        (0x1UL << 0)                       /**< Channel 1 Enable */
    205. 

  205. #define _DAC_CH1CTRL_EN_SHIFT                 0                                  /**< Shift value for DAC_EN */
    206. 

  206. #define _DAC_CH1CTRL_EN_MASK                  0x1UL                              /**< Bit mask for DAC_EN */
    207. 

  207. #define _DAC_CH1CTRL_EN_DEFAULT               0x00000000UL                       /**< Mode DEFAULT for DAC_CH1CTRL */
    208. 

  208. #define DAC_CH1CTRL_EN_DEFAULT                (_DAC_CH1CTRL_EN_DEFAULT << 0)     /**< Shifted mode DEFAULT for DAC_CH1CTRL */
    209. 

  209. #define DAC_CH1CTRL_REFREN                    (0x1UL << 1)                       /**< Channel 1 Automatic Refresh Enable */
    210. 

  210. #define _DAC_CH1CTRL_REFREN_SHIFT             1                                  /**< Shift value for DAC_REFREN */
    211. 

  211. #define _DAC_CH1CTRL_REFREN_MASK              0x2UL                              /**< Bit mask for DAC_REFREN */
    212. 

  212. #define _DAC_CH1CTRL_REFREN_DEFAULT           0x00000000UL                       /**< Mode DEFAULT for DAC_CH1CTRL */
    213. 

  213. #define DAC_CH1CTRL_REFREN_DEFAULT            (_DAC_CH1CTRL_REFREN_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_CH1CTRL */
    214. 

  214. #define DAC_CH1CTRL_PRSEN                     (0x1UL << 2)                       /**< Channel 1 PRS Trigger Enable */
    215. 

  215. #define _DAC_CH1CTRL_PRSEN_SHIFT              2                                  /**< Shift value for DAC_PRSEN */
    216. 

  216. #define _DAC_CH1CTRL_PRSEN_MASK               0x4UL                              /**< Bit mask for DAC_PRSEN */
    217. 

  217. #define _DAC_CH1CTRL_PRSEN_DEFAULT            0x00000000UL                       /**< Mode DEFAULT for DAC_CH1CTRL */
    218. 

  218. #define DAC_CH1CTRL_PRSEN_DEFAULT             (_DAC_CH1CTRL_PRSEN_DEFAULT << 2)  /**< Shifted mode DEFAULT for DAC_CH1CTRL */
    219. 

  219. #define _DAC_CH1CTRL_PRSSEL_SHIFT             4                                  /**< Shift value for DAC_PRSSEL */
    220. 

  220. #define _DAC_CH1CTRL_PRSSEL_MASK              0xF0UL                             /**< Bit mask for DAC_PRSSEL */
    221. 

  221. #define _DAC_CH1CTRL_PRSSEL_DEFAULT           0x00000000UL                       /**< Mode DEFAULT for DAC_CH1CTRL */
    222. 

  222. #define _DAC_CH1CTRL_PRSSEL_PRSCH0            0x00000000UL                       /**< Mode PRSCH0 for DAC_CH1CTRL */
    223. 

  223. #define _DAC_CH1CTRL_PRSSEL_PRSCH1            0x00000001UL                       /**< Mode PRSCH1 for DAC_CH1CTRL */
    224. 

  224. #define _DAC_CH1CTRL_PRSSEL_PRSCH2            0x00000002UL                       /**< Mode PRSCH2 for DAC_CH1CTRL */
    225. 

  225. #define _DAC_CH1CTRL_PRSSEL_PRSCH3            0x00000003UL                       /**< Mode PRSCH3 for DAC_CH1CTRL */
    226. 

  226. #define _DAC_CH1CTRL_PRSSEL_PRSCH4            0x00000004UL                       /**< Mode PRSCH4 for DAC_CH1CTRL */
    227. 

  227. #define _DAC_CH1CTRL_PRSSEL_PRSCH5            0x00000005UL                       /**< Mode PRSCH5 for DAC_CH1CTRL */
    228. 

  228. #define _DAC_CH1CTRL_PRSSEL_PRSCH6            0x00000006UL                       /**< Mode PRSCH6 for DAC_CH1CTRL */
    229. 

  229. #define _DAC_CH1CTRL_PRSSEL_PRSCH7            0x00000007UL                       /**< Mode PRSCH7 for DAC_CH1CTRL */
    230. 

  230. #define _DAC_CH1CTRL_PRSSEL_PRSCH8            0x00000008UL                       /**< Mode PRSCH8 for DAC_CH1CTRL */
    231. 

  231. #define _DAC_CH1CTRL_PRSSEL_PRSCH9            0x00000009UL                       /**< Mode PRSCH9 for DAC_CH1CTRL */
    232. 

  232. #define _DAC_CH1CTRL_PRSSEL_PRSCH10           0x0000000AUL                       /**< Mode PRSCH10 for DAC_CH1CTRL */
    233. 

  233. #define _DAC_CH1CTRL_PRSSEL_PRSCH11           0x0000000BUL                       /**< Mode PRSCH11 for DAC_CH1CTRL */
    234. 

  234. #define DAC_CH1CTRL_PRSSEL_DEFAULT            (_DAC_CH1CTRL_PRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_CH1CTRL */
    235. 

  235. #define DAC_CH1CTRL_PRSSEL_PRSCH0             (_DAC_CH1CTRL_PRSSEL_PRSCH0 << 4)  /**< Shifted mode PRSCH0 for DAC_CH1CTRL */
    236. 

  236. #define DAC_CH1CTRL_PRSSEL_PRSCH1             (_DAC_CH1CTRL_PRSSEL_PRSCH1 << 4)  /**< Shifted mode PRSCH1 for DAC_CH1CTRL */
    237. 

  237. #define DAC_CH1CTRL_PRSSEL_PRSCH2             (_DAC_CH1CTRL_PRSSEL_PRSCH2 << 4)  /**< Shifted mode PRSCH2 for DAC_CH1CTRL */
    238. 

  238. #define DAC_CH1CTRL_PRSSEL_PRSCH3             (_DAC_CH1CTRL_PRSSEL_PRSCH3 << 4)  /**< Shifted mode PRSCH3 for DAC_CH1CTRL */
    239. 

  239. #define DAC_CH1CTRL_PRSSEL_PRSCH4             (_DAC_CH1CTRL_PRSSEL_PRSCH4 << 4)  /**< Shifted mode PRSCH4 for DAC_CH1CTRL */
    240. 

  240. #define DAC_CH1CTRL_PRSSEL_PRSCH5             (_DAC_CH1CTRL_PRSSEL_PRSCH5 << 4)  /**< Shifted mode PRSCH5 for DAC_CH1CTRL */
    241. 

  241. #define DAC_CH1CTRL_PRSSEL_PRSCH6             (_DAC_CH1CTRL_PRSSEL_PRSCH6 << 4)  /**< Shifted mode PRSCH6 for DAC_CH1CTRL */
    242. 

  242. #define DAC_CH1CTRL_PRSSEL_PRSCH7             (_DAC_CH1CTRL_PRSSEL_PRSCH7 << 4)  /**< Shifted mode PRSCH7 for DAC_CH1CTRL */
    243. 

  243. #define DAC_CH1CTRL_PRSSEL_PRSCH8             (_DAC_CH1CTRL_PRSSEL_PRSCH8 << 4)  /**< Shifted mode PRSCH8 for DAC_CH1CTRL */
    244. 

  244. #define DAC_CH1CTRL_PRSSEL_PRSCH9             (_DAC_CH1CTRL_PRSSEL_PRSCH9 << 4)  /**< Shifted mode PRSCH9 for DAC_CH1CTRL */
    245. 

  245. #define DAC_CH1CTRL_PRSSEL_PRSCH10            (_DAC_CH1CTRL_PRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for DAC_CH1CTRL */
    246. 

  246. #define DAC_CH1CTRL_PRSSEL_PRSCH11            (_DAC_CH1CTRL_PRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for DAC_CH1CTRL */
    247. 

  247. 

  248. /* Bit fields for DAC IEN */
    249. 

  249. #define _DAC_IEN_RESETVALUE                   0x00000000UL                  /**< Default value for DAC_IEN */
    250. 

  250. #define _DAC_IEN_MASK                         0x00000033UL                  /**< Mask for DAC_IEN */
    251. 

  251. #define DAC_IEN_CH0                           (0x1UL << 0)                  /**< Channel 0 Conversion Complete Interrupt Enable */
    252. 

  252. #define _DAC_IEN_CH0_SHIFT                    0                             /**< Shift value for DAC_CH0 */
    253. 

  253. #define _DAC_IEN_CH0_MASK                     0x1UL                         /**< Bit mask for DAC_CH0 */
    254. 

  254. #define _DAC_IEN_CH0_DEFAULT                  0x00000000UL                  /**< Mode DEFAULT for DAC_IEN */
    255. 

  255. #define DAC_IEN_CH0_DEFAULT                   (_DAC_IEN_CH0_DEFAULT << 0)   /**< Shifted mode DEFAULT for DAC_IEN */
    256. 

  256. #define DAC_IEN_CH1                           (0x1UL << 1)                  /**< Channel 1 Conversion Complete Interrupt Enable */
    257. 

  257. #define _DAC_IEN_CH1_SHIFT                    1                             /**< Shift value for DAC_CH1 */
    258. 

  258. #define _DAC_IEN_CH1_MASK                     0x2UL                         /**< Bit mask for DAC_CH1 */
    259. 

  259. #define _DAC_IEN_CH1_DEFAULT                  0x00000000UL                  /**< Mode DEFAULT for DAC_IEN */
    260. 

  260. #define DAC_IEN_CH1_DEFAULT                   (_DAC_IEN_CH1_DEFAULT << 1)   /**< Shifted mode DEFAULT for DAC_IEN */
    261. 

  261. #define DAC_IEN_CH0UF                         (0x1UL << 4)                  /**< Channel 0 Conversion Data Underflow Interrupt Enable */
    262. 

  262. #define _DAC_IEN_CH0UF_SHIFT                  4                             /**< Shift value for DAC_CH0UF */
    263. 

  263. #define _DAC_IEN_CH0UF_MASK                   0x10UL                        /**< Bit mask for DAC_CH0UF */
    264. 

  264. #define _DAC_IEN_CH0UF_DEFAULT                0x00000000UL                  /**< Mode DEFAULT for DAC_IEN */
    265. 

  265. #define DAC_IEN_CH0UF_DEFAULT                 (_DAC_IEN_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_IEN */
    266. 

  266. #define DAC_IEN_CH1UF                         (0x1UL << 5)                  /**< Channel 1 Conversion Data Underflow Interrupt Enable */
    267. 

  267. #define _DAC_IEN_CH1UF_SHIFT                  5                             /**< Shift value for DAC_CH1UF */
    268. 

  268. #define _DAC_IEN_CH1UF_MASK                   0x20UL                        /**< Bit mask for DAC_CH1UF */
    269. 

  269. #define _DAC_IEN_CH1UF_DEFAULT                0x00000000UL                  /**< Mode DEFAULT for DAC_IEN */
    270. 

  270. #define DAC_IEN_CH1UF_DEFAULT                 (_DAC_IEN_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for DAC_IEN */
    271. 

  271. 

  272. /* Bit fields for DAC IF */
    273. 

  273. #define _DAC_IF_RESETVALUE                    0x00000000UL                 /**< Default value for DAC_IF */
    274. 

  274. #define _DAC_IF_MASK                          0x00000033UL                 /**< Mask for DAC_IF */
    275. 

  275. #define DAC_IF_CH0                            (0x1UL << 0)                 /**< Channel 0 Conversion Complete Interrupt Flag */
    276. 

  276. #define _DAC_IF_CH0_SHIFT                     0                            /**< Shift value for DAC_CH0 */
    277. 

  277. #define _DAC_IF_CH0_MASK                      0x1UL                        /**< Bit mask for DAC_CH0 */
    278. 

  278. #define _DAC_IF_CH0_DEFAULT                   0x00000000UL                 /**< Mode DEFAULT for DAC_IF */
    279. 

  279. #define DAC_IF_CH0_DEFAULT                    (_DAC_IF_CH0_DEFAULT << 0)   /**< Shifted mode DEFAULT for DAC_IF */
    280. 

  280. #define DAC_IF_CH1                            (0x1UL << 1)                 /**< Channel 1 Conversion Complete Interrupt Flag */
    281. 

  281. #define _DAC_IF_CH1_SHIFT                     1                            /**< Shift value for DAC_CH1 */
    282. 

  282. #define _DAC_IF_CH1_MASK                      0x2UL                        /**< Bit mask for DAC_CH1 */
    283. 

  283. #define _DAC_IF_CH1_DEFAULT                   0x00000000UL                 /**< Mode DEFAULT for DAC_IF */
    284. 

  284. #define DAC_IF_CH1_DEFAULT                    (_DAC_IF_CH1_DEFAULT << 1)   /**< Shifted mode DEFAULT for DAC_IF */
    285. 

  285. #define DAC_IF_CH0UF                          (0x1UL << 4)                 /**< Channel 0 Data Underflow Interrupt Flag */
    286. 

  286. #define _DAC_IF_CH0UF_SHIFT                   4                            /**< Shift value for DAC_CH0UF */
    287. 

  287. #define _DAC_IF_CH0UF_MASK                    0x10UL                       /**< Bit mask for DAC_CH0UF */
    288. 

  288. #define _DAC_IF_CH0UF_DEFAULT                 0x00000000UL                 /**< Mode DEFAULT for DAC_IF */
    289. 

  289. #define DAC_IF_CH0UF_DEFAULT                  (_DAC_IF_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_IF */
    290. 

  290. #define DAC_IF_CH1UF                          (0x1UL << 5)                 /**< Channel 1 Data Underflow Interrupt Flag */
    291. 

  291. #define _DAC_IF_CH1UF_SHIFT                   5                            /**< Shift value for DAC_CH1UF */
    292. 

  292. #define _DAC_IF_CH1UF_MASK                    0x20UL                       /**< Bit mask for DAC_CH1UF */
    293. 

  293. #define _DAC_IF_CH1UF_DEFAULT                 0x00000000UL                 /**< Mode DEFAULT for DAC_IF */
    294. 

  294. #define DAC_IF_CH1UF_DEFAULT                  (_DAC_IF_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for DAC_IF */
    295. 

  295. 

  296. /* Bit fields for DAC IFS */
    297. 

  297. #define _DAC_IFS_RESETVALUE                   0x00000000UL                  /**< Default value for DAC_IFS */
    298. 

  298. #define _DAC_IFS_MASK                         0x00000033UL                  /**< Mask for DAC_IFS */
    299. 

  299. #define DAC_IFS_CH0                           (0x1UL << 0)                  /**< Channel 0 Conversion Complete Interrupt Flag Set */
    300. 

  300. #define _DAC_IFS_CH0_SHIFT                    0                             /**< Shift value for DAC_CH0 */
    301. 

  301. #define _DAC_IFS_CH0_MASK                     0x1UL                         /**< Bit mask for DAC_CH0 */
    302. 

  302. #define _DAC_IFS_CH0_DEFAULT                  0x00000000UL                  /**< Mode DEFAULT for DAC_IFS */
    303. 

  303. #define DAC_IFS_CH0_DEFAULT                   (_DAC_IFS_CH0_DEFAULT << 0)   /**< Shifted mode DEFAULT for DAC_IFS */
    304. 

  304. #define DAC_IFS_CH1                           (0x1UL << 1)                  /**< Channel 1 Conversion Complete Interrupt Flag Set */
    305. 

  305. #define _DAC_IFS_CH1_SHIFT                    1                             /**< Shift value for DAC_CH1 */
    306. 

  306. #define _DAC_IFS_CH1_MASK                     0x2UL                         /**< Bit mask for DAC_CH1 */
    307. 

  307. #define _DAC_IFS_CH1_DEFAULT                  0x00000000UL                  /**< Mode DEFAULT for DAC_IFS */
    308. 

  308. #define DAC_IFS_CH1_DEFAULT                   (_DAC_IFS_CH1_DEFAULT << 1)   /**< Shifted mode DEFAULT for DAC_IFS */
    309. 

  309. #define DAC_IFS_CH0UF                         (0x1UL << 4)                  /**< Channel 0 Data Underflow Interrupt Flag Set */
    310. 

  310. #define _DAC_IFS_CH0UF_SHIFT                  4                             /**< Shift value for DAC_CH0UF */
    311. 

  311. #define _DAC_IFS_CH0UF_MASK                   0x10UL                        /**< Bit mask for DAC_CH0UF */
    312. 

  312. #define _DAC_IFS_CH0UF_DEFAULT                0x00000000UL                  /**< Mode DEFAULT for DAC_IFS */
    313. 

  313. #define DAC_IFS_CH0UF_DEFAULT                 (_DAC_IFS_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_IFS */
    314. 

  314. #define DAC_IFS_CH1UF                         (0x1UL << 5)                  /**< Channel 1 Data Underflow Interrupt Flag Set */
    315. 

  315. #define _DAC_IFS_CH1UF_SHIFT                  5                             /**< Shift value for DAC_CH1UF */
    316. 

  316. #define _DAC_IFS_CH1UF_MASK                   0x20UL                        /**< Bit mask for DAC_CH1UF */
    317. 

  317. #define _DAC_IFS_CH1UF_DEFAULT                0x00000000UL                  /**< Mode DEFAULT for DAC_IFS */
    318. 

  318. #define DAC_IFS_CH1UF_DEFAULT                 (_DAC_IFS_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for DAC_IFS */
    319. 

  319. 

  320. /* Bit fields for DAC IFC */
    321. 

  321. #define _DAC_IFC_RESETVALUE                   0x00000000UL                  /**< Default value for DAC_IFC */
    322. 

  322. #define _DAC_IFC_MASK                         0x00000033UL                  /**< Mask for DAC_IFC */
    323. 

  323. #define DAC_IFC_CH0                           (0x1UL << 0)                  /**< Channel 0 Conversion Complete Interrupt Flag Clear */
    324. 

  324. #define _DAC_IFC_CH0_SHIFT                    0                             /**< Shift value for DAC_CH0 */
    325. 

  325. #define _DAC_IFC_CH0_MASK                     0x1UL                         /**< Bit mask for DAC_CH0 */
    326. 

  326. #define _DAC_IFC_CH0_DEFAULT                  0x00000000UL                  /**< Mode DEFAULT for DAC_IFC */
    327. 

  327. #define DAC_IFC_CH0_DEFAULT                   (_DAC_IFC_CH0_DEFAULT << 0)   /**< Shifted mode DEFAULT for DAC_IFC */
    328. 

  328. #define DAC_IFC_CH1                           (0x1UL << 1)                  /**< Channel 1 Conversion Complete Interrupt Flag Clear */
    329. 

  329. #define _DAC_IFC_CH1_SHIFT                    1                             /**< Shift value for DAC_CH1 */
    330. 

  330. #define _DAC_IFC_CH1_MASK                     0x2UL                         /**< Bit mask for DAC_CH1 */
    331. 

  331. #define _DAC_IFC_CH1_DEFAULT                  0x00000000UL                  /**< Mode DEFAULT for DAC_IFC */
    332. 

  332. #define DAC_IFC_CH1_DEFAULT                   (_DAC_IFC_CH1_DEFAULT << 1)   /**< Shifted mode DEFAULT for DAC_IFC */
    333. 

  333. #define DAC_IFC_CH0UF                         (0x1UL << 4)                  /**< Channel 0 Data Underflow Interrupt Flag Clear */
    334. 

  334. #define _DAC_IFC_CH0UF_SHIFT                  4                             /**< Shift value for DAC_CH0UF */
    335. 

  335. #define _DAC_IFC_CH0UF_MASK                   0x10UL                        /**< Bit mask for DAC_CH0UF */
    336. 

  336. #define _DAC_IFC_CH0UF_DEFAULT                0x00000000UL                  /**< Mode DEFAULT for DAC_IFC */
    337. 

  337. #define DAC_IFC_CH0UF_DEFAULT                 (_DAC_IFC_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_IFC */
    338. 

  338. #define DAC_IFC_CH1UF                         (0x1UL << 5)                  /**< Channel 1 Data Underflow Interrupt Flag Clear */
    339. 

  339. #define _DAC_IFC_CH1UF_SHIFT                  5                             /**< Shift value for DAC_CH1UF */
    340. 

  340. #define _DAC_IFC_CH1UF_MASK                   0x20UL                        /**< Bit mask for DAC_CH1UF */
    341. 

  341. #define _DAC_IFC_CH1UF_DEFAULT                0x00000000UL                  /**< Mode DEFAULT for DAC_IFC */
    342. 

  342. #define DAC_IFC_CH1UF_DEFAULT                 (_DAC_IFC_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for DAC_IFC */
    343. 

  343. 

  344. /* Bit fields for DAC CH0DATA */
    345. 

  345. #define _DAC_CH0DATA_RESETVALUE               0x00000000UL                     /**< Default value for DAC_CH0DATA */
    346. 

  346. #define _DAC_CH0DATA_MASK                     0x00000FFFUL                     /**< Mask for DAC_CH0DATA */
    347. 

  347. #define _DAC_CH0DATA_DATA_SHIFT               0                                /**< Shift value for DAC_DATA */
    348. 

  348. #define _DAC_CH0DATA_DATA_MASK                0xFFFUL                          /**< Bit mask for DAC_DATA */
    349. 

  349. #define _DAC_CH0DATA_DATA_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for DAC_CH0DATA */
    350. 

  350. #define DAC_CH0DATA_DATA_DEFAULT              (_DAC_CH0DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_CH0DATA */
    351. 

  351. 

  352. /* Bit fields for DAC CH1DATA */
    353. 

  353. #define _DAC_CH1DATA_RESETVALUE               0x00000000UL                     /**< Default value for DAC_CH1DATA */
    354. 

  354. #define _DAC_CH1DATA_MASK                     0x00000FFFUL                     /**< Mask for DAC_CH1DATA */
    355. 

  355. #define _DAC_CH1DATA_DATA_SHIFT               0                                /**< Shift value for DAC_DATA */
    356. 

  356. #define _DAC_CH1DATA_DATA_MASK                0xFFFUL                          /**< Bit mask for DAC_DATA */
    357. 

  357. #define _DAC_CH1DATA_DATA_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for DAC_CH1DATA */
    358. 

  358. #define DAC_CH1DATA_DATA_DEFAULT              (_DAC_CH1DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_CH1DATA */
    359. 

  359. 

  360. /* Bit fields for DAC COMBDATA */
    361. 

  361. #define _DAC_COMBDATA_RESETVALUE              0x00000000UL                          /**< Default value for DAC_COMBDATA */
    362. 

  362. #define _DAC_COMBDATA_MASK                    0x0FFF0FFFUL                          /**< Mask for DAC_COMBDATA */
    363. 

  363. #define _DAC_COMBDATA_CH0DATA_SHIFT           0                                     /**< Shift value for DAC_CH0DATA */
    364. 

  364. #define _DAC_COMBDATA_CH0DATA_MASK            0xFFFUL                               /**< Bit mask for DAC_CH0DATA */
    365. 

  365. #define _DAC_COMBDATA_CH0DATA_DEFAULT         0x00000000UL                          /**< Mode DEFAULT for DAC_COMBDATA */
    366. 

  366. #define DAC_COMBDATA_CH0DATA_DEFAULT          (_DAC_COMBDATA_CH0DATA_DEFAULT << 0)  /**< Shifted mode DEFAULT for DAC_COMBDATA */
    367. 

  367. #define _DAC_COMBDATA_CH1DATA_SHIFT           16                                    /**< Shift value for DAC_CH1DATA */
    368. 

  368. #define _DAC_COMBDATA_CH1DATA_MASK            0xFFF0000UL                           /**< Bit mask for DAC_CH1DATA */
    369. 

  369. #define _DAC_COMBDATA_CH1DATA_DEFAULT         0x00000000UL                          /**< Mode DEFAULT for DAC_COMBDATA */
    370. 

  370. #define DAC_COMBDATA_CH1DATA_DEFAULT          (_DAC_COMBDATA_CH1DATA_DEFAULT << 16) /**< Shifted mode DEFAULT for DAC_COMBDATA */
    371. 

  371. 

  372. /* Bit fields for DAC CAL */
    373. 

  373. #define _DAC_CAL_RESETVALUE                   0x00400000UL                      /**< Default value for DAC_CAL */
    374. 

  374. #define _DAC_CAL_MASK                         0x007F3F3FUL                      /**< Mask for DAC_CAL */
    375. 

  375. #define _DAC_CAL_CH0OFFSET_SHIFT              0                                 /**< Shift value for DAC_CH0OFFSET */
    376. 

  376. #define _DAC_CAL_CH0OFFSET_MASK               0x3FUL                            /**< Bit mask for DAC_CH0OFFSET */
    377. 

  377. #define _DAC_CAL_CH0OFFSET_DEFAULT            0x00000000UL                      /**< Mode DEFAULT for DAC_CAL */
    378. 

  378. #define DAC_CAL_CH0OFFSET_DEFAULT             (_DAC_CAL_CH0OFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_CAL */
    379. 

  379. #define _DAC_CAL_CH1OFFSET_SHIFT              8                                 /**< Shift value for DAC_CH1OFFSET */
    380. 

  380. #define _DAC_CAL_CH1OFFSET_MASK               0x3F00UL                          /**< Bit mask for DAC_CH1OFFSET */
    381. 

  381. #define _DAC_CAL_CH1OFFSET_DEFAULT            0x00000000UL                      /**< Mode DEFAULT for DAC_CAL */
    382. 

  382. #define DAC_CAL_CH1OFFSET_DEFAULT             (_DAC_CAL_CH1OFFSET_DEFAULT << 8) /**< Shifted mode DEFAULT for DAC_CAL */
    383. 

  383. #define _DAC_CAL_GAIN_SHIFT                   16                                /**< Shift value for DAC_GAIN */
    384. 

  384. #define _DAC_CAL_GAIN_MASK                    0x7F0000UL                        /**< Bit mask for DAC_GAIN */
    385. 

  385. #define _DAC_CAL_GAIN_DEFAULT                 0x00000040UL                      /**< Mode DEFAULT for DAC_CAL */
    386. 

  386. #define DAC_CAL_GAIN_DEFAULT                  (_DAC_CAL_GAIN_DEFAULT << 16)     /**< Shifted mode DEFAULT for DAC_CAL */
    387. 

  387. 

  388. /* Bit fields for DAC BIASPROG */
    389. 

  389. #define _DAC_BIASPROG_RESETVALUE              0x00004747UL                               /**< Default value for DAC_BIASPROG */
    390. 

  390. #define _DAC_BIASPROG_MASK                    0x00004F4FUL                               /**< Mask for DAC_BIASPROG */
    391. 

  391. #define _DAC_BIASPROG_BIASPROG_SHIFT          0                                          /**< Shift value for DAC_BIASPROG */
    392. 

  392. #define _DAC_BIASPROG_BIASPROG_MASK           0xFUL                                      /**< Bit mask for DAC_BIASPROG */
    393. 

  393. #define _DAC_BIASPROG_BIASPROG_DEFAULT        0x00000007UL                               /**< Mode DEFAULT for DAC_BIASPROG */
    394. 

  394. #define DAC_BIASPROG_BIASPROG_DEFAULT         (_DAC_BIASPROG_BIASPROG_DEFAULT << 0)      /**< Shifted mode DEFAULT for DAC_BIASPROG */
    395. 

  395. #define DAC_BIASPROG_HALFBIAS                 (0x1UL << 6)                               /**< Half Bias Current */
    396. 

  396. #define _DAC_BIASPROG_HALFBIAS_SHIFT          6                                          /**< Shift value for DAC_HALFBIAS */
    397. 

  397. #define _DAC_BIASPROG_HALFBIAS_MASK           0x40UL                                     /**< Bit mask for DAC_HALFBIAS */
    398. 

  398. #define _DAC_BIASPROG_HALFBIAS_DEFAULT        0x00000001UL                               /**< Mode DEFAULT for DAC_BIASPROG */
    399. 

  399. #define DAC_BIASPROG_HALFBIAS_DEFAULT         (_DAC_BIASPROG_HALFBIAS_DEFAULT << 6)      /**< Shifted mode DEFAULT for DAC_BIASPROG */
    400. 

  400. #define _DAC_BIASPROG_OPA2BIASPROG_SHIFT      8                                          /**< Shift value for DAC_OPA2BIASPROG */
    401. 

  401. #define _DAC_BIASPROG_OPA2BIASPROG_MASK       0xF00UL                                    /**< Bit mask for DAC_OPA2BIASPROG */
    402. 

  402. #define _DAC_BIASPROG_OPA2BIASPROG_DEFAULT    0x00000007UL                               /**< Mode DEFAULT for DAC_BIASPROG */
    403. 

  403. #define DAC_BIASPROG_OPA2BIASPROG_DEFAULT     (_DAC_BIASPROG_OPA2BIASPROG_DEFAULT << 8)  /**< Shifted mode DEFAULT for DAC_BIASPROG */
    404. 

  404. #define DAC_BIASPROG_OPA2HALFBIAS             (0x1UL << 14)                              /**< Half Bias Current */
    405. 

  405. #define _DAC_BIASPROG_OPA2HALFBIAS_SHIFT      14                                         /**< Shift value for DAC_OPA2HALFBIAS */
    406. 

  406. #define _DAC_BIASPROG_OPA2HALFBIAS_MASK       0x4000UL                                   /**< Bit mask for DAC_OPA2HALFBIAS */
    407. 

  407. #define _DAC_BIASPROG_OPA2HALFBIAS_DEFAULT    0x00000001UL                               /**< Mode DEFAULT for DAC_BIASPROG */
    408. 

  408. #define DAC_BIASPROG_OPA2HALFBIAS_DEFAULT     (_DAC_BIASPROG_OPA2HALFBIAS_DEFAULT << 14) /**< Shifted mode DEFAULT for DAC_BIASPROG */
    409. 

  409. 

  410. /* Bit fields for DAC OPACTRL */
    411. 

  411. #define _DAC_OPACTRL_RESETVALUE               0x00000000UL                            /**< Default value for DAC_OPACTRL */
    412. 

  412. #define _DAC_OPACTRL_MASK                     0x01C3F1C7UL                            /**< Mask for DAC_OPACTRL */
    413. 

  413. #define DAC_OPACTRL_OPA0EN                    (0x1UL << 0)                            /**< OPA0 Enable */
    414. 

  414. #define _DAC_OPACTRL_OPA0EN_SHIFT             0                                       /**< Shift value for DAC_OPA0EN */
    415. 

  415. #define _DAC_OPACTRL_OPA0EN_MASK              0x1UL                                   /**< Bit mask for DAC_OPA0EN */
    416. 

  416. #define _DAC_OPACTRL_OPA0EN_DEFAULT           0x00000000UL                            /**< Mode DEFAULT for DAC_OPACTRL */
    417. 

  417. #define DAC_OPACTRL_OPA0EN_DEFAULT            (_DAC_OPACTRL_OPA0EN_DEFAULT << 0)      /**< Shifted mode DEFAULT for DAC_OPACTRL */
    418. 

  418. #define DAC_OPACTRL_OPA1EN                    (0x1UL << 1)                            /**< OPA1 Enable */
    419. 

  419. #define _DAC_OPACTRL_OPA1EN_SHIFT             1                                       /**< Shift value for DAC_OPA1EN */
    420. 

  420. #define _DAC_OPACTRL_OPA1EN_MASK              0x2UL                                   /**< Bit mask for DAC_OPA1EN */
    421. 

  421. #define _DAC_OPACTRL_OPA1EN_DEFAULT           0x00000000UL                            /**< Mode DEFAULT for DAC_OPACTRL */
    422. 

  422. #define DAC_OPACTRL_OPA1EN_DEFAULT            (_DAC_OPACTRL_OPA1EN_DEFAULT << 1)      /**< Shifted mode DEFAULT for DAC_OPACTRL */
    423. 

  423. #define DAC_OPACTRL_OPA2EN                    (0x1UL << 2)                            /**< OPA2 Enable */
    424. 

  424. #define _DAC_OPACTRL_OPA2EN_SHIFT             2                                       /**< Shift value for DAC_OPA2EN */
    425. 

  425. #define _DAC_OPACTRL_OPA2EN_MASK              0x4UL                                   /**< Bit mask for DAC_OPA2EN */
    426. 

  426. #define _DAC_OPACTRL_OPA2EN_DEFAULT           0x00000000UL                            /**< Mode DEFAULT for DAC_OPACTRL */
    427. 

  427. #define DAC_OPACTRL_OPA2EN_DEFAULT            (_DAC_OPACTRL_OPA2EN_DEFAULT << 2)      /**< Shifted mode DEFAULT for DAC_OPACTRL */
    428. 

  428. #define DAC_OPACTRL_OPA0HCMDIS                (0x1UL << 6)                            /**< High Common Mode Disable. */
    429. 

  429. #define _DAC_OPACTRL_OPA0HCMDIS_SHIFT         6                                       /**< Shift value for DAC_OPA0HCMDIS */
    430. 

  430. #define _DAC_OPACTRL_OPA0HCMDIS_MASK          0x40UL                                  /**< Bit mask for DAC_OPA0HCMDIS */
    431. 

  431. #define _DAC_OPACTRL_OPA0HCMDIS_DEFAULT       0x00000000UL                            /**< Mode DEFAULT for DAC_OPACTRL */
    432. 

  432. #define DAC_OPACTRL_OPA0HCMDIS_DEFAULT        (_DAC_OPACTRL_OPA0HCMDIS_DEFAULT << 6)  /**< Shifted mode DEFAULT for DAC_OPACTRL */
    433. 

  433. #define DAC_OPACTRL_OPA1HCMDIS                (0x1UL << 7)                            /**< High Common Mode Disable. */
    434. 

  434. #define _DAC_OPACTRL_OPA1HCMDIS_SHIFT         7                                       /**< Shift value for DAC_OPA1HCMDIS */
    435. 

  435. #define _DAC_OPACTRL_OPA1HCMDIS_MASK          0x80UL                                  /**< Bit mask for DAC_OPA1HCMDIS */
    436. 

  436. #define _DAC_OPACTRL_OPA1HCMDIS_DEFAULT       0x00000000UL                            /**< Mode DEFAULT for DAC_OPACTRL */
    437. 

  437. #define DAC_OPACTRL_OPA1HCMDIS_DEFAULT        (_DAC_OPACTRL_OPA1HCMDIS_DEFAULT << 7)  /**< Shifted mode DEFAULT for DAC_OPACTRL */
    438. 

  438. #define DAC_OPACTRL_OPA2HCMDIS                (0x1UL << 8)                            /**< High Common Mode Disable. */
    439. 

  439. #define _DAC_OPACTRL_OPA2HCMDIS_SHIFT         8                                       /**< Shift value for DAC_OPA2HCMDIS */
    440. 

  440. #define _DAC_OPACTRL_OPA2HCMDIS_MASK          0x100UL                                 /**< Bit mask for DAC_OPA2HCMDIS */
    441. 

  441. #define _DAC_OPACTRL_OPA2HCMDIS_DEFAULT       0x00000000UL                            /**< Mode DEFAULT for DAC_OPACTRL */
    442. 

  442. #define DAC_OPACTRL_OPA2HCMDIS_DEFAULT        (_DAC_OPACTRL_OPA2HCMDIS_DEFAULT << 8)  /**< Shifted mode DEFAULT for DAC_OPACTRL */
    443. 

  443. #define _DAC_OPACTRL_OPA0LPFDIS_SHIFT         12                                      /**< Shift value for DAC_OPA0LPFDIS */
    444. 

  444. #define _DAC_OPACTRL_OPA0LPFDIS_MASK          0x3000UL                                /**< Bit mask for DAC_OPA0LPFDIS */
    445. 

  445. #define _DAC_OPACTRL_OPA0LPFDIS_DEFAULT       0x00000000UL                            /**< Mode DEFAULT for DAC_OPACTRL */
    446. 

  446. #define _DAC_OPACTRL_OPA0LPFDIS_PLPFDIS       0x00000001UL                            /**< Mode PLPFDIS for DAC_OPACTRL */
    447. 

  447. #define _DAC_OPACTRL_OPA0LPFDIS_NLPFDIS       0x00000002UL                            /**< Mode NLPFDIS for DAC_OPACTRL */
    448. 

  448. #define DAC_OPACTRL_OPA0LPFDIS_DEFAULT        (_DAC_OPACTRL_OPA0LPFDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for DAC_OPACTRL */
    449. 

  449. #define DAC_OPACTRL_OPA0LPFDIS_PLPFDIS        (_DAC_OPACTRL_OPA0LPFDIS_PLPFDIS << 12) /**< Shifted mode PLPFDIS for DAC_OPACTRL */
    450. 

  450. #define DAC_OPACTRL_OPA0LPFDIS_NLPFDIS        (_DAC_OPACTRL_OPA0LPFDIS_NLPFDIS << 12) /**< Shifted mode NLPFDIS for DAC_OPACTRL */
    451. 

  451. #define _DAC_OPACTRL_OPA1LPFDIS_SHIFT         14                                      /**< Shift value for DAC_OPA1LPFDIS */
    452. 

  452. #define _DAC_OPACTRL_OPA1LPFDIS_MASK          0xC000UL                                /**< Bit mask for DAC_OPA1LPFDIS */
    453. 

  453. #define _DAC_OPACTRL_OPA1LPFDIS_DEFAULT       0x00000000UL                            /**< Mode DEFAULT for DAC_OPACTRL */
    454. 

  454. #define _DAC_OPACTRL_OPA1LPFDIS_PLPFDIS       0x00000001UL                            /**< Mode PLPFDIS for DAC_OPACTRL */
    455. 

  455. #define _DAC_OPACTRL_OPA1LPFDIS_NLPFDIS       0x00000002UL                            /**< Mode NLPFDIS for DAC_OPACTRL */
    456. 

  456. #define DAC_OPACTRL_OPA1LPFDIS_DEFAULT        (_DAC_OPACTRL_OPA1LPFDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for DAC_OPACTRL */
    457. 

  457. #define DAC_OPACTRL_OPA1LPFDIS_PLPFDIS        (_DAC_OPACTRL_OPA1LPFDIS_PLPFDIS << 14) /**< Shifted mode PLPFDIS for DAC_OPACTRL */
    458. 

  458. #define DAC_OPACTRL_OPA1LPFDIS_NLPFDIS        (_DAC_OPACTRL_OPA1LPFDIS_NLPFDIS << 14) /**< Shifted mode NLPFDIS for DAC_OPACTRL */
    459. 

  459. #define _DAC_OPACTRL_OPA2LPFDIS_SHIFT         16                                      /**< Shift value for DAC_OPA2LPFDIS */
    460. 

  460. #define _DAC_OPACTRL_OPA2LPFDIS_MASK          0x30000UL                               /**< Bit mask for DAC_OPA2LPFDIS */
    461. 

  461. #define _DAC_OPACTRL_OPA2LPFDIS_DEFAULT       0x00000000UL                            /**< Mode DEFAULT for DAC_OPACTRL */
    462. 

  462. #define _DAC_OPACTRL_OPA2LPFDIS_PLPFDIS       0x00000001UL                            /**< Mode PLPFDIS for DAC_OPACTRL */
    463. 

  463. #define _DAC_OPACTRL_OPA2LPFDIS_NLPFDIS       0x00000002UL                            /**< Mode NLPFDIS for DAC_OPACTRL */
    464. 

  464. #define DAC_OPACTRL_OPA2LPFDIS_DEFAULT        (_DAC_OPACTRL_OPA2LPFDIS_DEFAULT << 16) /**< Shifted mode DEFAULT for DAC_OPACTRL */
    465. 

  465. #define DAC_OPACTRL_OPA2LPFDIS_PLPFDIS        (_DAC_OPACTRL_OPA2LPFDIS_PLPFDIS << 16) /**< Shifted mode PLPFDIS for DAC_OPACTRL */
    466. 

  466. #define DAC_OPACTRL_OPA2LPFDIS_NLPFDIS        (_DAC_OPACTRL_OPA2LPFDIS_NLPFDIS << 16) /**< Shifted mode NLPFDIS for DAC_OPACTRL */
    467. 

  467. #define DAC_OPACTRL_OPA0SHORT                 (0x1UL << 22)                           /**< Short the non-inverting and Invering Input. */
    468. 

  468. #define _DAC_OPACTRL_OPA0SHORT_SHIFT          22                                      /**< Shift value for DAC_OPA0SHORT */
    469. 

  469. #define _DAC_OPACTRL_OPA0SHORT_MASK           0x400000UL                              /**< Bit mask for DAC_OPA0SHORT */
    470. 

  470. #define _DAC_OPACTRL_OPA0SHORT_DEFAULT        0x00000000UL                            /**< Mode DEFAULT for DAC_OPACTRL */
    471. 

  471. #define DAC_OPACTRL_OPA0SHORT_DEFAULT         (_DAC_OPACTRL_OPA0SHORT_DEFAULT << 22)  /**< Shifted mode DEFAULT for DAC_OPACTRL */
    472. 

  472. #define DAC_OPACTRL_OPA1SHORT                 (0x1UL << 23)                           /**< Short the non-inverting and Invering Input. */
    473. 

  473. #define _DAC_OPACTRL_OPA1SHORT_SHIFT          23                                      /**< Shift value for DAC_OPA1SHORT */
    474. 

  474. #define _DAC_OPACTRL_OPA1SHORT_MASK           0x800000UL                              /**< Bit mask for DAC_OPA1SHORT */
    475. 

  475. #define _DAC_OPACTRL_OPA1SHORT_DEFAULT        0x00000000UL                            /**< Mode DEFAULT for DAC_OPACTRL */
    476. 

  476. #define DAC_OPACTRL_OPA1SHORT_DEFAULT         (_DAC_OPACTRL_OPA1SHORT_DEFAULT << 23)  /**< Shifted mode DEFAULT for DAC_OPACTRL */
    477. 

  477. #define DAC_OPACTRL_OPA2SHORT                 (0x1UL << 24)                           /**< Short the non-inverting and Invering Input. */
    478. 

  478. #define _DAC_OPACTRL_OPA2SHORT_SHIFT          24                                      /**< Shift value for DAC_OPA2SHORT */
    479. 

  479. #define _DAC_OPACTRL_OPA2SHORT_MASK           0x1000000UL                             /**< Bit mask for DAC_OPA2SHORT */
    480. 

  480. #define _DAC_OPACTRL_OPA2SHORT_DEFAULT        0x00000000UL                            /**< Mode DEFAULT for DAC_OPACTRL */
    481. 

  481. #define DAC_OPACTRL_OPA2SHORT_DEFAULT         (_DAC_OPACTRL_OPA2SHORT_DEFAULT << 24)  /**< Shifted mode DEFAULT for DAC_OPACTRL */
    482. 

  482. 

  483. /* Bit fields for DAC OPAOFFSET */
    484. 

  484. #define _DAC_OPAOFFSET_RESETVALUE             0x00000000UL                             /**< Default value for DAC_OPAOFFSET */
    485. 

  485. #define _DAC_OPAOFFSET_MASK                   0x0000003FUL                             /**< Mask for DAC_OPAOFFSET */
    486. 

  486. #define _DAC_OPAOFFSET_OPA2OFFSET_SHIFT       0                                        /**< Shift value for DAC_OPA2OFFSET */
    487. 

  487. #define _DAC_OPAOFFSET_OPA2OFFSET_MASK        0x3FUL                                   /**< Bit mask for DAC_OPA2OFFSET */
    488. 

  488. #define _DAC_OPAOFFSET_OPA2OFFSET_DEFAULT     0x00000000UL                             /**< Mode DEFAULT for DAC_OPAOFFSET */
    489. 

  489. #define DAC_OPAOFFSET_OPA2OFFSET_DEFAULT      (_DAC_OPAOFFSET_OPA2OFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_OPAOFFSET */
    490. 

  490. 

  491. /* Bit fields for DAC OPA0MUX */
    492. 

  492. #define _DAC_OPA0MUX_RESETVALUE               0x00400000UL                         /**< Default value for DAC_OPA0MUX */
    493. 

  493. #define _DAC_OPA0MUX_MASK                     0x74C7F737UL                         /**< Mask for DAC_OPA0MUX */
    494. 

  494. #define _DAC_OPA0MUX_POSSEL_SHIFT             0                                    /**< Shift value for DAC_POSSEL */
    495. 

  495. #define _DAC_OPA0MUX_POSSEL_MASK              0x7UL                                /**< Bit mask for DAC_POSSEL */
    496. 

  496. #define _DAC_OPA0MUX_POSSEL_DEFAULT           0x00000000UL                         /**< Mode DEFAULT for DAC_OPA0MUX */
    497. 

  497. #define _DAC_OPA0MUX_POSSEL_DISABLE           0x00000000UL                         /**< Mode DISABLE for DAC_OPA0MUX */
    498. 

  498. #define _DAC_OPA0MUX_POSSEL_DAC               0x00000001UL                         /**< Mode DAC for DAC_OPA0MUX */
    499. 

  499. #define _DAC_OPA0MUX_POSSEL_POSPAD            0x00000002UL                         /**< Mode POSPAD for DAC_OPA0MUX */
    500. 

  500. #define _DAC_OPA0MUX_POSSEL_OPA0INP           0x00000003UL                         /**< Mode OPA0INP for DAC_OPA0MUX */
    501. 

  501. #define _DAC_OPA0MUX_POSSEL_OPATAP            0x00000004UL                         /**< Mode OPATAP for DAC_OPA0MUX */
    502. 

  502. #define DAC_OPA0MUX_POSSEL_DEFAULT            (_DAC_OPA0MUX_POSSEL_DEFAULT << 0)   /**< Shifted mode DEFAULT for DAC_OPA0MUX */
    503. 

  503. #define DAC_OPA0MUX_POSSEL_DISABLE            (_DAC_OPA0MUX_POSSEL_DISABLE << 0)   /**< Shifted mode DISABLE for DAC_OPA0MUX */
    504. 

  504. #define DAC_OPA0MUX_POSSEL_DAC                (_DAC_OPA0MUX_POSSEL_DAC << 0)       /**< Shifted mode DAC for DAC_OPA0MUX */
    505. 

  505. #define DAC_OPA0MUX_POSSEL_POSPAD             (_DAC_OPA0MUX_POSSEL_POSPAD << 0)    /**< Shifted mode POSPAD for DAC_OPA0MUX */
    506. 

  506. #define DAC_OPA0MUX_POSSEL_OPA0INP            (_DAC_OPA0MUX_POSSEL_OPA0INP << 0)   /**< Shifted mode OPA0INP for DAC_OPA0MUX */
    507. 

  507. #define DAC_OPA0MUX_POSSEL_OPATAP             (_DAC_OPA0MUX_POSSEL_OPATAP << 0)    /**< Shifted mode OPATAP for DAC_OPA0MUX */
    508. 

  508. #define _DAC_OPA0MUX_NEGSEL_SHIFT             4                                    /**< Shift value for DAC_NEGSEL */
    509. 

  509. #define _DAC_OPA0MUX_NEGSEL_MASK              0x30UL                               /**< Bit mask for DAC_NEGSEL */
    510. 

  510. #define _DAC_OPA0MUX_NEGSEL_DEFAULT           0x00000000UL                         /**< Mode DEFAULT for DAC_OPA0MUX */
    511. 

  511. #define _DAC_OPA0MUX_NEGSEL_DISABLE           0x00000000UL                         /**< Mode DISABLE for DAC_OPA0MUX */
    512. 

  512. #define _DAC_OPA0MUX_NEGSEL_UG                0x00000001UL                         /**< Mode UG for DAC_OPA0MUX */
    513. 

  513. #define _DAC_OPA0MUX_NEGSEL_OPATAP            0x00000002UL                         /**< Mode OPATAP for DAC_OPA0MUX */
    514. 

  514. #define _DAC_OPA0MUX_NEGSEL_NEGPAD            0x00000003UL                         /**< Mode NEGPAD for DAC_OPA0MUX */
    515. 

  515. #define DAC_OPA0MUX_NEGSEL_DEFAULT            (_DAC_OPA0MUX_NEGSEL_DEFAULT << 4)   /**< Shifted mode DEFAULT for DAC_OPA0MUX */
    516. 

  516. #define DAC_OPA0MUX_NEGSEL_DISABLE            (_DAC_OPA0MUX_NEGSEL_DISABLE << 4)   /**< Shifted mode DISABLE for DAC_OPA0MUX */
    517. 

  517. #define DAC_OPA0MUX_NEGSEL_UG                 (_DAC_OPA0MUX_NEGSEL_UG << 4)        /**< Shifted mode UG for DAC_OPA0MUX */
    518. 

  518. #define DAC_OPA0MUX_NEGSEL_OPATAP             (_DAC_OPA0MUX_NEGSEL_OPATAP << 4)    /**< Shifted mode OPATAP for DAC_OPA0MUX */
    519. 

  519. #define DAC_OPA0MUX_NEGSEL_NEGPAD             (_DAC_OPA0MUX_NEGSEL_NEGPAD << 4)    /**< Shifted mode NEGPAD for DAC_OPA0MUX */
    520. 

  520. #define _DAC_OPA0MUX_RESINMUX_SHIFT           8                                    /**< Shift value for DAC_RESINMUX */
    521. 

  521. #define _DAC_OPA0MUX_RESINMUX_MASK            0x700UL                              /**< Bit mask for DAC_RESINMUX */
    522. 

  522. #define _DAC_OPA0MUX_RESINMUX_DEFAULT         0x00000000UL                         /**< Mode DEFAULT for DAC_OPA0MUX */
    523. 

  523. #define _DAC_OPA0MUX_RESINMUX_DISABLE         0x00000000UL                         /**< Mode DISABLE for DAC_OPA0MUX */
    524. 

  524. #define _DAC_OPA0MUX_RESINMUX_OPA0INP         0x00000001UL                         /**< Mode OPA0INP for DAC_OPA0MUX */
    525. 

  525. #define _DAC_OPA0MUX_RESINMUX_NEGPAD          0x00000002UL                         /**< Mode NEGPAD for DAC_OPA0MUX */
    526. 

  526. #define _DAC_OPA0MUX_RESINMUX_POSPAD          0x00000003UL                         /**< Mode POSPAD for DAC_OPA0MUX */
    527. 

  527. #define _DAC_OPA0MUX_RESINMUX_VSS             0x00000004UL                         /**< Mode VSS for DAC_OPA0MUX */
    528. 

  528. #define DAC_OPA0MUX_RESINMUX_DEFAULT          (_DAC_OPA0MUX_RESINMUX_DEFAULT << 8) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
    529. 

  529. #define DAC_OPA0MUX_RESINMUX_DISABLE          (_DAC_OPA0MUX_RESINMUX_DISABLE << 8) /**< Shifted mode DISABLE for DAC_OPA0MUX */
    530. 

  530. #define DAC_OPA0MUX_RESINMUX_OPA0INP          (_DAC_OPA0MUX_RESINMUX_OPA0INP << 8) /**< Shifted mode OPA0INP for DAC_OPA0MUX */
    531. 

  531. #define DAC_OPA0MUX_RESINMUX_NEGPAD           (_DAC_OPA0MUX_RESINMUX_NEGPAD << 8)  /**< Shifted mode NEGPAD for DAC_OPA0MUX */
    532. 

  532. #define DAC_OPA0MUX_RESINMUX_POSPAD           (_DAC_OPA0MUX_RESINMUX_POSPAD << 8)  /**< Shifted mode POSPAD for DAC_OPA0MUX */
    533. 

  533. #define DAC_OPA0MUX_RESINMUX_VSS              (_DAC_OPA0MUX_RESINMUX_VSS << 8)     /**< Shifted mode VSS for DAC_OPA0MUX */
    534. 

  534. #define DAC_OPA0MUX_PPEN                      (0x1UL << 12)                        /**< OPA0 Positive Pad Input Enable */
    535. 

  535. #define _DAC_OPA0MUX_PPEN_SHIFT               12                                   /**< Shift value for DAC_PPEN */
    536. 

  536. #define _DAC_OPA0MUX_PPEN_MASK                0x1000UL                             /**< Bit mask for DAC_PPEN */
    537. 

  537. #define _DAC_OPA0MUX_PPEN_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for DAC_OPA0MUX */
    538. 

  538. #define DAC_OPA0MUX_PPEN_DEFAULT              (_DAC_OPA0MUX_PPEN_DEFAULT << 12)    /**< Shifted mode DEFAULT for DAC_OPA0MUX */
    539. 

  539. #define DAC_OPA0MUX_NPEN                      (0x1UL << 13)                        /**< OPA0 Negative Pad Input Enable */
    540. 

  540. #define _DAC_OPA0MUX_NPEN_SHIFT               13                                   /**< Shift value for DAC_NPEN */
    541. 

  541. #define _DAC_OPA0MUX_NPEN_MASK                0x2000UL                             /**< Bit mask for DAC_NPEN */
    542. 

  542. #define _DAC_OPA0MUX_NPEN_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for DAC_OPA0MUX */
    543. 

  543. #define DAC_OPA0MUX_NPEN_DEFAULT              (_DAC_OPA0MUX_NPEN_DEFAULT << 13)    /**< Shifted mode DEFAULT for DAC_OPA0MUX */
    544. 

  544. #define _DAC_OPA0MUX_OUTPEN_SHIFT             14                                   /**< Shift value for DAC_OUTPEN */
    545. 

  545. #define _DAC_OPA0MUX_OUTPEN_MASK              0x7C000UL                            /**< Bit mask for DAC_OUTPEN */
    546. 

  546. #define _DAC_OPA0MUX_OUTPEN_DEFAULT           0x00000000UL                         /**< Mode DEFAULT for DAC_OPA0MUX */
    547. 

  547. #define _DAC_OPA0MUX_OUTPEN_OUT0              0x00000001UL                         /**< Mode OUT0 for DAC_OPA0MUX */
    548. 

  548. #define _DAC_OPA0MUX_OUTPEN_OUT1              0x00000002UL                         /**< Mode OUT1 for DAC_OPA0MUX */
    549. 

  549. #define _DAC_OPA0MUX_OUTPEN_OUT2              0x00000004UL                         /**< Mode OUT2 for DAC_OPA0MUX */
    550. 

  550. #define _DAC_OPA0MUX_OUTPEN_OUT3              0x00000008UL                         /**< Mode OUT3 for DAC_OPA0MUX */
    551. 

  551. #define _DAC_OPA0MUX_OUTPEN_OUT4              0x00000010UL                         /**< Mode OUT4 for DAC_OPA0MUX */
    552. 

  552. #define DAC_OPA0MUX_OUTPEN_DEFAULT            (_DAC_OPA0MUX_OUTPEN_DEFAULT << 14)  /**< Shifted mode DEFAULT for DAC_OPA0MUX */
    553. 

  553. #define DAC_OPA0MUX_OUTPEN_OUT0               (_DAC_OPA0MUX_OUTPEN_OUT0 << 14)     /**< Shifted mode OUT0 for DAC_OPA0MUX */
    554. 

  554. #define DAC_OPA0MUX_OUTPEN_OUT1               (_DAC_OPA0MUX_OUTPEN_OUT1 << 14)     /**< Shifted mode OUT1 for DAC_OPA0MUX */
    555. 

  555. #define DAC_OPA0MUX_OUTPEN_OUT2               (_DAC_OPA0MUX_OUTPEN_OUT2 << 14)     /**< Shifted mode OUT2 for DAC_OPA0MUX */
    556. 

  556. #define DAC_OPA0MUX_OUTPEN_OUT3               (_DAC_OPA0MUX_OUTPEN_OUT3 << 14)     /**< Shifted mode OUT3 for DAC_OPA0MUX */
    557. 

  557. #define DAC_OPA0MUX_OUTPEN_OUT4               (_DAC_OPA0MUX_OUTPEN_OUT4 << 14)     /**< Shifted mode OUT4 for DAC_OPA0MUX */
    558. 

  558. #define _DAC_OPA0MUX_OUTMODE_SHIFT            22                                   /**< Shift value for DAC_OUTMODE */
    559. 

  559. #define _DAC_OPA0MUX_OUTMODE_MASK             0xC00000UL                           /**< Bit mask for DAC_OUTMODE */
    560. 

  560. #define _DAC_OPA0MUX_OUTMODE_DISABLE          0x00000000UL                         /**< Mode DISABLE for DAC_OPA0MUX */
    561. 

  561. #define _DAC_OPA0MUX_OUTMODE_DEFAULT          0x00000001UL                         /**< Mode DEFAULT for DAC_OPA0MUX */
    562. 

  562. #define _DAC_OPA0MUX_OUTMODE_MAIN             0x00000001UL                         /**< Mode MAIN for DAC_OPA0MUX */
    563. 

  563. #define _DAC_OPA0MUX_OUTMODE_ALT              0x00000002UL                         /**< Mode ALT for DAC_OPA0MUX */
    564. 

  564. #define _DAC_OPA0MUX_OUTMODE_ALL              0x00000003UL                         /**< Mode ALL for DAC_OPA0MUX */
    565. 

  565. #define DAC_OPA0MUX_OUTMODE_DISABLE           (_DAC_OPA0MUX_OUTMODE_DISABLE << 22) /**< Shifted mode DISABLE for DAC_OPA0MUX */
    566. 

  566. #define DAC_OPA0MUX_OUTMODE_DEFAULT           (_DAC_OPA0MUX_OUTMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
    567. 

  567. #define DAC_OPA0MUX_OUTMODE_MAIN              (_DAC_OPA0MUX_OUTMODE_MAIN << 22)    /**< Shifted mode MAIN for DAC_OPA0MUX */
    568. 

  568. #define DAC_OPA0MUX_OUTMODE_ALT               (_DAC_OPA0MUX_OUTMODE_ALT << 22)     /**< Shifted mode ALT for DAC_OPA0MUX */
    569. 

  569. #define DAC_OPA0MUX_OUTMODE_ALL               (_DAC_OPA0MUX_OUTMODE_ALL << 22)     /**< Shifted mode ALL for DAC_OPA0MUX */
    570. 

  570. #define DAC_OPA0MUX_NEXTOUT                   (0x1UL << 26)                        /**< OPA0 Next Enable */
    571. 

  571. #define _DAC_OPA0MUX_NEXTOUT_SHIFT            26                                   /**< Shift value for DAC_NEXTOUT */
    572. 

  572. #define _DAC_OPA0MUX_NEXTOUT_MASK             0x4000000UL                          /**< Bit mask for DAC_NEXTOUT */
    573. 

  573. #define _DAC_OPA0MUX_NEXTOUT_DEFAULT          0x00000000UL                         /**< Mode DEFAULT for DAC_OPA0MUX */
    574. 

  574. #define DAC_OPA0MUX_NEXTOUT_DEFAULT           (_DAC_OPA0MUX_NEXTOUT_DEFAULT << 26) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
    575. 

  575. #define _DAC_OPA0MUX_RESSEL_SHIFT             28                                   /**< Shift value for DAC_RESSEL */
    576. 

  576. #define _DAC_OPA0MUX_RESSEL_MASK              0x70000000UL                         /**< Bit mask for DAC_RESSEL */
    577. 

  577. #define _DAC_OPA0MUX_RESSEL_DEFAULT           0x00000000UL                         /**< Mode DEFAULT for DAC_OPA0MUX */
    578. 

  578. #define _DAC_OPA0MUX_RESSEL_RES0              0x00000000UL                         /**< Mode RES0 for DAC_OPA0MUX */
    579. 

  579. #define _DAC_OPA0MUX_RESSEL_RES1              0x00000001UL                         /**< Mode RES1 for DAC_OPA0MUX */
    580. 

  580. #define _DAC_OPA0MUX_RESSEL_RES2              0x00000002UL                         /**< Mode RES2 for DAC_OPA0MUX */
    581. 

  581. #define _DAC_OPA0MUX_RESSEL_RES3              0x00000003UL                         /**< Mode RES3 for DAC_OPA0MUX */
    582. 

  582. #define _DAC_OPA0MUX_RESSEL_RES4              0x00000004UL                         /**< Mode RES4 for DAC_OPA0MUX */
    583. 

  583. #define _DAC_OPA0MUX_RESSEL_RES5              0x00000005UL                         /**< Mode RES5 for DAC_OPA0MUX */
    584. 

  584. #define _DAC_OPA0MUX_RESSEL_RES6              0x00000006UL                         /**< Mode RES6 for DAC_OPA0MUX */
    585. 

  585. #define _DAC_OPA0MUX_RESSEL_RES7              0x00000007UL                         /**< Mode RES7 for DAC_OPA0MUX */
    586. 

  586. #define DAC_OPA0MUX_RESSEL_DEFAULT            (_DAC_OPA0MUX_RESSEL_DEFAULT << 28)  /**< Shifted mode DEFAULT for DAC_OPA0MUX */
    587. 

  587. #define DAC_OPA0MUX_RESSEL_RES0               (_DAC_OPA0MUX_RESSEL_RES0 << 28)     /**< Shifted mode RES0 for DAC_OPA0MUX */
    588. 

  588. #define DAC_OPA0MUX_RESSEL_RES1               (_DAC_OPA0MUX_RESSEL_RES1 << 28)     /**< Shifted mode RES1 for DAC_OPA0MUX */
    589. 

  589. #define DAC_OPA0MUX_RESSEL_RES2               (_DAC_OPA0MUX_RESSEL_RES2 << 28)     /**< Shifted mode RES2 for DAC_OPA0MUX */
    590. 

  590. #define DAC_OPA0MUX_RESSEL_RES3               (_DAC_OPA0MUX_RESSEL_RES3 << 28)     /**< Shifted mode RES3 for DAC_OPA0MUX */
    591. 

  591. #define DAC_OPA0MUX_RESSEL_RES4               (_DAC_OPA0MUX_RESSEL_RES4 << 28)     /**< Shifted mode RES4 for DAC_OPA0MUX */
    592. 

  592. #define DAC_OPA0MUX_RESSEL_RES5               (_DAC_OPA0MUX_RESSEL_RES5 << 28)     /**< Shifted mode RES5 for DAC_OPA0MUX */
    593. 

  593. #define DAC_OPA0MUX_RESSEL_RES6               (_DAC_OPA0MUX_RESSEL_RES6 << 28)     /**< Shifted mode RES6 for DAC_OPA0MUX */
    594. 

  594. #define DAC_OPA0MUX_RESSEL_RES7               (_DAC_OPA0MUX_RESSEL_RES7 << 28)     /**< Shifted mode RES7 for DAC_OPA0MUX */
    595. 

  595. 

  596. /* Bit fields for DAC OPA1MUX */
    597. 

  597. #define _DAC_OPA1MUX_RESETVALUE               0x00000000UL                         /**< Default value for DAC_OPA1MUX */
    598. 

  598. #define _DAC_OPA1MUX_MASK                     0x74C7F737UL                         /**< Mask for DAC_OPA1MUX */
    599. 

  599. #define _DAC_OPA1MUX_POSSEL_SHIFT             0                                    /**< Shift value for DAC_POSSEL */
    600. 

  600. #define _DAC_OPA1MUX_POSSEL_MASK              0x7UL                                /**< Bit mask for DAC_POSSEL */
    601. 

  601. #define _DAC_OPA1MUX_POSSEL_DEFAULT           0x00000000UL                         /**< Mode DEFAULT for DAC_OPA1MUX */
    602. 

  602. #define _DAC_OPA1MUX_POSSEL_DISABLE           0x00000000UL                         /**< Mode DISABLE for DAC_OPA1MUX */
    603. 

  603. #define _DAC_OPA1MUX_POSSEL_DAC               0x00000001UL                         /**< Mode DAC for DAC_OPA1MUX */
    604. 

  604. #define _DAC_OPA1MUX_POSSEL_POSPAD            0x00000002UL                         /**< Mode POSPAD for DAC_OPA1MUX */
    605. 

  605. #define _DAC_OPA1MUX_POSSEL_OPA0INP           0x00000003UL                         /**< Mode OPA0INP for DAC_OPA1MUX */
    606. 

  606. #define _DAC_OPA1MUX_POSSEL_OPATAP            0x00000004UL                         /**< Mode OPATAP for DAC_OPA1MUX */
    607. 

  607. #define DAC_OPA1MUX_POSSEL_DEFAULT            (_DAC_OPA1MUX_POSSEL_DEFAULT << 0)   /**< Shifted mode DEFAULT for DAC_OPA1MUX */
    608. 

  608. #define DAC_OPA1MUX_POSSEL_DISABLE            (_DAC_OPA1MUX_POSSEL_DISABLE << 0)   /**< Shifted mode DISABLE for DAC_OPA1MUX */
    609. 

  609. #define DAC_OPA1MUX_POSSEL_DAC                (_DAC_OPA1MUX_POSSEL_DAC << 0)       /**< Shifted mode DAC for DAC_OPA1MUX */
    610. 

  610. #define DAC_OPA1MUX_POSSEL_POSPAD             (_DAC_OPA1MUX_POSSEL_POSPAD << 0)    /**< Shifted mode POSPAD for DAC_OPA1MUX */
    611. 

  611. #define DAC_OPA1MUX_POSSEL_OPA0INP            (_DAC_OPA1MUX_POSSEL_OPA0INP << 0)   /**< Shifted mode OPA0INP for DAC_OPA1MUX */
    612. 

  612. #define DAC_OPA1MUX_POSSEL_OPATAP             (_DAC_OPA1MUX_POSSEL_OPATAP << 0)    /**< Shifted mode OPATAP for DAC_OPA1MUX */
    613. 

  613. #define _DAC_OPA1MUX_NEGSEL_SHIFT             4                                    /**< Shift value for DAC_NEGSEL */
    614. 

  614. #define _DAC_OPA1MUX_NEGSEL_MASK              0x30UL                               /**< Bit mask for DAC_NEGSEL */
    615. 

  615. #define _DAC_OPA1MUX_NEGSEL_DEFAULT           0x00000000UL                         /**< Mode DEFAULT for DAC_OPA1MUX */
    616. 

  616. #define _DAC_OPA1MUX_NEGSEL_DISABLE           0x00000000UL                         /**< Mode DISABLE for DAC_OPA1MUX */
    617. 

  617. #define _DAC_OPA1MUX_NEGSEL_UG                0x00000001UL                         /**< Mode UG for DAC_OPA1MUX */
    618. 

  618. #define _DAC_OPA1MUX_NEGSEL_OPATAP            0x00000002UL                         /**< Mode OPATAP for DAC_OPA1MUX */
    619. 

  619. #define _DAC_OPA1MUX_NEGSEL_NEGPAD            0x00000003UL                         /**< Mode NEGPAD for DAC_OPA1MUX */
    620. 

  620. #define DAC_OPA1MUX_NEGSEL_DEFAULT            (_DAC_OPA1MUX_NEGSEL_DEFAULT << 4)   /**< Shifted mode DEFAULT for DAC_OPA1MUX */
    621. 

  621. #define DAC_OPA1MUX_NEGSEL_DISABLE            (_DAC_OPA1MUX_NEGSEL_DISABLE << 4)   /**< Shifted mode DISABLE for DAC_OPA1MUX */
    622. 

  622. #define DAC_OPA1MUX_NEGSEL_UG                 (_DAC_OPA1MUX_NEGSEL_UG << 4)        /**< Shifted mode UG for DAC_OPA1MUX */
    623. 

  623. #define DAC_OPA1MUX_NEGSEL_OPATAP             (_DAC_OPA1MUX_NEGSEL_OPATAP << 4)    /**< Shifted mode OPATAP for DAC_OPA1MUX */
    624. 

  624. #define DAC_OPA1MUX_NEGSEL_NEGPAD             (_DAC_OPA1MUX_NEGSEL_NEGPAD << 4)    /**< Shifted mode NEGPAD for DAC_OPA1MUX */
    625. 

  625. #define _DAC_OPA1MUX_RESINMUX_SHIFT           8                                    /**< Shift value for DAC_RESINMUX */
    626. 

  626. #define _DAC_OPA1MUX_RESINMUX_MASK            0x700UL                              /**< Bit mask for DAC_RESINMUX */
    627. 

  627. #define _DAC_OPA1MUX_RESINMUX_DEFAULT         0x00000000UL                         /**< Mode DEFAULT for DAC_OPA1MUX */
    628. 

  628. #define _DAC_OPA1MUX_RESINMUX_DISABLE         0x00000000UL                         /**< Mode DISABLE for DAC_OPA1MUX */
    629. 

  629. #define _DAC_OPA1MUX_RESINMUX_OPA0INP         0x00000001UL                         /**< Mode OPA0INP for DAC_OPA1MUX */
    630. 

  630. #define _DAC_OPA1MUX_RESINMUX_NEGPAD          0x00000002UL                         /**< Mode NEGPAD for DAC_OPA1MUX */
    631. 

  631. #define _DAC_OPA1MUX_RESINMUX_POSPAD          0x00000003UL                         /**< Mode POSPAD for DAC_OPA1MUX */
    632. 

  632. #define _DAC_OPA1MUX_RESINMUX_VSS             0x00000004UL                         /**< Mode VSS for DAC_OPA1MUX */
    633. 

  633. #define DAC_OPA1MUX_RESINMUX_DEFAULT          (_DAC_OPA1MUX_RESINMUX_DEFAULT << 8) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
    634. 

  634. #define DAC_OPA1MUX_RESINMUX_DISABLE          (_DAC_OPA1MUX_RESINMUX_DISABLE << 8) /**< Shifted mode DISABLE for DAC_OPA1MUX */
    635. 

  635. #define DAC_OPA1MUX_RESINMUX_OPA0INP          (_DAC_OPA1MUX_RESINMUX_OPA0INP << 8) /**< Shifted mode OPA0INP for DAC_OPA1MUX */
    636. 

  636. #define DAC_OPA1MUX_RESINMUX_NEGPAD           (_DAC_OPA1MUX_RESINMUX_NEGPAD << 8)  /**< Shifted mode NEGPAD for DAC_OPA1MUX */
    637. 

  637. #define DAC_OPA1MUX_RESINMUX_POSPAD           (_DAC_OPA1MUX_RESINMUX_POSPAD << 8)  /**< Shifted mode POSPAD for DAC_OPA1MUX */
    638. 

  638. #define DAC_OPA1MUX_RESINMUX_VSS              (_DAC_OPA1MUX_RESINMUX_VSS << 8)     /**< Shifted mode VSS for DAC_OPA1MUX */
    639. 

  639. #define DAC_OPA1MUX_PPEN                      (0x1UL << 12)                        /**< OPA1 Positive Pad Input Enable */
    640. 

  640. #define _DAC_OPA1MUX_PPEN_SHIFT               12                                   /**< Shift value for DAC_PPEN */
    641. 

  641. #define _DAC_OPA1MUX_PPEN_MASK                0x1000UL                             /**< Bit mask for DAC_PPEN */
    642. 

  642. #define _DAC_OPA1MUX_PPEN_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for DAC_OPA1MUX */
    643. 

  643. #define DAC_OPA1MUX_PPEN_DEFAULT              (_DAC_OPA1MUX_PPEN_DEFAULT << 12)    /**< Shifted mode DEFAULT for DAC_OPA1MUX */
    644. 

  644. #define DAC_OPA1MUX_NPEN                      (0x1UL << 13)                        /**< OPA1 Negative Pad Input Enable */
    645. 

  645. #define _DAC_OPA1MUX_NPEN_SHIFT               13                                   /**< Shift value for DAC_NPEN */
    646. 

  646. #define _DAC_OPA1MUX_NPEN_MASK                0x2000UL                             /**< Bit mask for DAC_NPEN */
    647. 

  647. #define _DAC_OPA1MUX_NPEN_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for DAC_OPA1MUX */
    648. 

  648. #define DAC_OPA1MUX_NPEN_DEFAULT              (_DAC_OPA1MUX_NPEN_DEFAULT << 13)    /**< Shifted mode DEFAULT for DAC_OPA1MUX */
    649. 

  649. #define _DAC_OPA1MUX_OUTPEN_SHIFT             14                                   /**< Shift value for DAC_OUTPEN */
    650. 

  650. #define _DAC_OPA1MUX_OUTPEN_MASK              0x7C000UL                            /**< Bit mask for DAC_OUTPEN */
    651. 

  651. #define _DAC_OPA1MUX_OUTPEN_DEFAULT           0x00000000UL                         /**< Mode DEFAULT for DAC_OPA1MUX */
    652. 

  652. #define _DAC_OPA1MUX_OUTPEN_OUT0              0x00000001UL                         /**< Mode OUT0 for DAC_OPA1MUX */
    653. 

  653. #define _DAC_OPA1MUX_OUTPEN_OUT1              0x00000002UL                         /**< Mode OUT1 for DAC_OPA1MUX */
    654. 

  654. #define _DAC_OPA1MUX_OUTPEN_OUT2              0x00000004UL                         /**< Mode OUT2 for DAC_OPA1MUX */
    655. 

  655. #define _DAC_OPA1MUX_OUTPEN_OUT3              0x00000008UL                         /**< Mode OUT3 for DAC_OPA1MUX */
    656. 

  656. #define _DAC_OPA1MUX_OUTPEN_OUT4              0x00000010UL                         /**< Mode OUT4 for DAC_OPA1MUX */
    657. 

  657. #define DAC_OPA1MUX_OUTPEN_DEFAULT            (_DAC_OPA1MUX_OUTPEN_DEFAULT << 14)  /**< Shifted mode DEFAULT for DAC_OPA1MUX */
    658. 

  658. #define DAC_OPA1MUX_OUTPEN_OUT0               (_DAC_OPA1MUX_OUTPEN_OUT0 << 14)     /**< Shifted mode OUT0 for DAC_OPA1MUX */
    659. 

  659. #define DAC_OPA1MUX_OUTPEN_OUT1               (_DAC_OPA1MUX_OUTPEN_OUT1 << 14)     /**< Shifted mode OUT1 for DAC_OPA1MUX */
    660. 

  660. #define DAC_OPA1MUX_OUTPEN_OUT2               (_DAC_OPA1MUX_OUTPEN_OUT2 << 14)     /**< Shifted mode OUT2 for DAC_OPA1MUX */
    661. 

  661. #define DAC_OPA1MUX_OUTPEN_OUT3               (_DAC_OPA1MUX_OUTPEN_OUT3 << 14)     /**< Shifted mode OUT3 for DAC_OPA1MUX */
    662. 

  662. #define DAC_OPA1MUX_OUTPEN_OUT4               (_DAC_OPA1MUX_OUTPEN_OUT4 << 14)     /**< Shifted mode OUT4 for DAC_OPA1MUX */
    663. 

  663. #define _DAC_OPA1MUX_OUTMODE_SHIFT            22                                   /**< Shift value for DAC_OUTMODE */
    664. 

  664. #define _DAC_OPA1MUX_OUTMODE_MASK             0xC00000UL                           /**< Bit mask for DAC_OUTMODE */
    665. 

  665. #define _DAC_OPA1MUX_OUTMODE_DEFAULT          0x00000000UL                         /**< Mode DEFAULT for DAC_OPA1MUX */
    666. 

  666. #define _DAC_OPA1MUX_OUTMODE_DISABLE          0x00000000UL                         /**< Mode DISABLE for DAC_OPA1MUX */
    667. 

  667. #define _DAC_OPA1MUX_OUTMODE_MAIN             0x00000001UL                         /**< Mode MAIN for DAC_OPA1MUX */
    668. 

  668. #define _DAC_OPA1MUX_OUTMODE_ALT              0x00000002UL                         /**< Mode ALT for DAC_OPA1MUX */
    669. 

  669. #define _DAC_OPA1MUX_OUTMODE_ALL              0x00000003UL                         /**< Mode ALL for DAC_OPA1MUX */
    670. 

  670. #define DAC_OPA1MUX_OUTMODE_DEFAULT           (_DAC_OPA1MUX_OUTMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
    671. 

  671. #define DAC_OPA1MUX_OUTMODE_DISABLE           (_DAC_OPA1MUX_OUTMODE_DISABLE << 22) /**< Shifted mode DISABLE for DAC_OPA1MUX */
    672. 

  672. #define DAC_OPA1MUX_OUTMODE_MAIN              (_DAC_OPA1MUX_OUTMODE_MAIN << 22)    /**< Shifted mode MAIN for DAC_OPA1MUX */
    673. 

  673. #define DAC_OPA1MUX_OUTMODE_ALT               (_DAC_OPA1MUX_OUTMODE_ALT << 22)     /**< Shifted mode ALT for DAC_OPA1MUX */
    674. 

  674. #define DAC_OPA1MUX_OUTMODE_ALL               (_DAC_OPA1MUX_OUTMODE_ALL << 22)     /**< Shifted mode ALL for DAC_OPA1MUX */
    675. 

  675. #define DAC_OPA1MUX_NEXTOUT                   (0x1UL << 26)                        /**< OPA1 Next Enable */
    676. 

  676. #define _DAC_OPA1MUX_NEXTOUT_SHIFT            26                                   /**< Shift value for DAC_NEXTOUT */
    677. 

  677. #define _DAC_OPA1MUX_NEXTOUT_MASK             0x4000000UL                          /**< Bit mask for DAC_NEXTOUT */
    678. 

  678. #define _DAC_OPA1MUX_NEXTOUT_DEFAULT          0x00000000UL                         /**< Mode DEFAULT for DAC_OPA1MUX */
    679. 

  679. #define DAC_OPA1MUX_NEXTOUT_DEFAULT           (_DAC_OPA1MUX_NEXTOUT_DEFAULT << 26) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
    680. 

  680. #define _DAC_OPA1MUX_RESSEL_SHIFT             28                                   /**< Shift value for DAC_RESSEL */
    681. 

  681. #define _DAC_OPA1MUX_RESSEL_MASK              0x70000000UL                         /**< Bit mask for DAC_RESSEL */
    682. 

  682. #define _DAC_OPA1MUX_RESSEL_DEFAULT           0x00000000UL                         /**< Mode DEFAULT for DAC_OPA1MUX */
    683. 

  683. #define _DAC_OPA1MUX_RESSEL_RES0              0x00000000UL                         /**< Mode RES0 for DAC_OPA1MUX */
    684. 

  684. #define _DAC_OPA1MUX_RESSEL_RES1              0x00000001UL                         /**< Mode RES1 for DAC_OPA1MUX */
    685. 

  685. #define _DAC_OPA1MUX_RESSEL_RES2              0x00000002UL                         /**< Mode RES2 for DAC_OPA1MUX */
    686. 

  686. #define _DAC_OPA1MUX_RESSEL_RES3              0x00000003UL                         /**< Mode RES3 for DAC_OPA1MUX */
    687. 

  687. #define _DAC_OPA1MUX_RESSEL_RES4              0x00000004UL                         /**< Mode RES4 for DAC_OPA1MUX */
    688. 

  688. #define _DAC_OPA1MUX_RESSEL_RES5              0x00000005UL                         /**< Mode RES5 for DAC_OPA1MUX */
    689. 

  689. #define _DAC_OPA1MUX_RESSEL_RES6              0x00000006UL                         /**< Mode RES6 for DAC_OPA1MUX */
    690. 

  690. #define _DAC_OPA1MUX_RESSEL_RES7              0x00000007UL                         /**< Mode RES7 for DAC_OPA1MUX */
    691. 

  691. #define DAC_OPA1MUX_RESSEL_DEFAULT            (_DAC_OPA1MUX_RESSEL_DEFAULT << 28)  /**< Shifted mode DEFAULT for DAC_OPA1MUX */
    692. 

  692. #define DAC_OPA1MUX_RESSEL_RES0               (_DAC_OPA1MUX_RESSEL_RES0 << 28)     /**< Shifted mode RES0 for DAC_OPA1MUX */
    693. 

  693. #define DAC_OPA1MUX_RESSEL_RES1               (_DAC_OPA1MUX_RESSEL_RES1 << 28)     /**< Shifted mode RES1 for DAC_OPA1MUX */
    694. 

  694. #define DAC_OPA1MUX_RESSEL_RES2               (_DAC_OPA1MUX_RESSEL_RES2 << 28)     /**< Shifted mode RES2 for DAC_OPA1MUX */
    695. 

  695. #define DAC_OPA1MUX_RESSEL_RES3               (_DAC_OPA1MUX_RESSEL_RES3 << 28)     /**< Shifted mode RES3 for DAC_OPA1MUX */
    696. 

  696. #define DAC_OPA1MUX_RESSEL_RES4               (_DAC_OPA1MUX_RESSEL_RES4 << 28)     /**< Shifted mode RES4 for DAC_OPA1MUX */
    697. 

  697. #define DAC_OPA1MUX_RESSEL_RES5               (_DAC_OPA1MUX_RESSEL_RES5 << 28)     /**< Shifted mode RES5 for DAC_OPA1MUX */
    698. 

  698. #define DAC_OPA1MUX_RESSEL_RES6               (_DAC_OPA1MUX_RESSEL_RES6 << 28)     /**< Shifted mode RES6 for DAC_OPA1MUX */
    699. 

  699. #define DAC_OPA1MUX_RESSEL_RES7               (_DAC_OPA1MUX_RESSEL_RES7 << 28)     /**< Shifted mode RES7 for DAC_OPA1MUX */
    700. 

  700. 

  701. /* Bit fields for DAC OPA2MUX */
    702. 

  702. #define _DAC_OPA2MUX_RESETVALUE               0x00000000UL                         /**< Default value for DAC_OPA2MUX */
    703. 

  703. #define _DAC_OPA2MUX_MASK                     0x7440F737UL                         /**< Mask for DAC_OPA2MUX */
    704. 

  704. #define _DAC_OPA2MUX_POSSEL_SHIFT             0                                    /**< Shift value for DAC_POSSEL */
    705. 

  705. #define _DAC_OPA2MUX_POSSEL_MASK              0x7UL                                /**< Bit mask for DAC_POSSEL */
    706. 

  706. #define _DAC_OPA2MUX_POSSEL_DEFAULT           0x00000000UL                         /**< Mode DEFAULT for DAC_OPA2MUX */
    707. 

  707. #define _DAC_OPA2MUX_POSSEL_DISABLE           0x00000000UL                         /**< Mode DISABLE for DAC_OPA2MUX */
    708. 

  708. #define _DAC_OPA2MUX_POSSEL_POSPAD            0x00000002UL                         /**< Mode POSPAD for DAC_OPA2MUX */
    709. 

  709. #define _DAC_OPA2MUX_POSSEL_OPA1INP           0x00000003UL                         /**< Mode OPA1INP for DAC_OPA2MUX */
    710. 

  710. #define _DAC_OPA2MUX_POSSEL_OPATAP            0x00000004UL                         /**< Mode OPATAP for DAC_OPA2MUX */
    711. 

  711. #define DAC_OPA2MUX_POSSEL_DEFAULT            (_DAC_OPA2MUX_POSSEL_DEFAULT << 0)   /**< Shifted mode DEFAULT for DAC_OPA2MUX */
    712. 

  712. #define DAC_OPA2MUX_POSSEL_DISABLE            (_DAC_OPA2MUX_POSSEL_DISABLE << 0)   /**< Shifted mode DISABLE for DAC_OPA2MUX */
    713. 

  713. #define DAC_OPA2MUX_POSSEL_POSPAD             (_DAC_OPA2MUX_POSSEL_POSPAD << 0)    /**< Shifted mode POSPAD for DAC_OPA2MUX */
    714. 

  714. #define DAC_OPA2MUX_POSSEL_OPA1INP            (_DAC_OPA2MUX_POSSEL_OPA1INP << 0)   /**< Shifted mode OPA1INP for DAC_OPA2MUX */
    715. 

  715. #define DAC_OPA2MUX_POSSEL_OPATAP             (_DAC_OPA2MUX_POSSEL_OPATAP << 0)    /**< Shifted mode OPATAP for DAC_OPA2MUX */
    716. 

  716. #define _DAC_OPA2MUX_NEGSEL_SHIFT             4                                    /**< Shift value for DAC_NEGSEL */
    717. 

  717. #define _DAC_OPA2MUX_NEGSEL_MASK              0x30UL                               /**< Bit mask for DAC_NEGSEL */
    718. 

  718. #define _DAC_OPA2MUX_NEGSEL_DEFAULT           0x00000000UL                         /**< Mode DEFAULT for DAC_OPA2MUX */
    719. 

  719. #define _DAC_OPA2MUX_NEGSEL_DISABLE           0x00000000UL                         /**< Mode DISABLE for DAC_OPA2MUX */
    720. 

  720. #define _DAC_OPA2MUX_NEGSEL_UG                0x00000001UL                         /**< Mode UG for DAC_OPA2MUX */
    721. 

  721. #define _DAC_OPA2MUX_NEGSEL_OPATAP            0x00000002UL                         /**< Mode OPATAP for DAC_OPA2MUX */
    722. 

  722. #define _DAC_OPA2MUX_NEGSEL_NEGPAD            0x00000003UL                         /**< Mode NEGPAD for DAC_OPA2MUX */
    723. 

  723. #define DAC_OPA2MUX_NEGSEL_DEFAULT            (_DAC_OPA2MUX_NEGSEL_DEFAULT << 4)   /**< Shifted mode DEFAULT for DAC_OPA2MUX */
    724. 

  724. #define DAC_OPA2MUX_NEGSEL_DISABLE            (_DAC_OPA2MUX_NEGSEL_DISABLE << 4)   /**< Shifted mode DISABLE for DAC_OPA2MUX */
    725. 

  725. #define DAC_OPA2MUX_NEGSEL_UG                 (_DAC_OPA2MUX_NEGSEL_UG << 4)        /**< Shifted mode UG for DAC_OPA2MUX */
    726. 

  726. #define DAC_OPA2MUX_NEGSEL_OPATAP             (_DAC_OPA2MUX_NEGSEL_OPATAP << 4)    /**< Shifted mode OPATAP for DAC_OPA2MUX */
    727. 

  727. #define DAC_OPA2MUX_NEGSEL_NEGPAD             (_DAC_OPA2MUX_NEGSEL_NEGPAD << 4)    /**< Shifted mode NEGPAD for DAC_OPA2MUX */
    728. 

  728. #define _DAC_OPA2MUX_RESINMUX_SHIFT           8                                    /**< Shift value for DAC_RESINMUX */
    729. 

  729. #define _DAC_OPA2MUX_RESINMUX_MASK            0x700UL                              /**< Bit mask for DAC_RESINMUX */
    730. 

  730. #define _DAC_OPA2MUX_RESINMUX_DEFAULT         0x00000000UL                         /**< Mode DEFAULT for DAC_OPA2MUX */
    731. 

  731. #define _DAC_OPA2MUX_RESINMUX_DISABLE         0x00000000UL                         /**< Mode DISABLE for DAC_OPA2MUX */
    732. 

  732. #define _DAC_OPA2MUX_RESINMUX_OPA1INP         0x00000001UL                         /**< Mode OPA1INP for DAC_OPA2MUX */
    733. 

  733. #define _DAC_OPA2MUX_RESINMUX_NEGPAD          0x00000002UL                         /**< Mode NEGPAD for DAC_OPA2MUX */
    734. 

  734. #define _DAC_OPA2MUX_RESINMUX_POSPAD          0x00000003UL                         /**< Mode POSPAD for DAC_OPA2MUX */
    735. 

  735. #define _DAC_OPA2MUX_RESINMUX_VSS             0x00000004UL                         /**< Mode VSS for DAC_OPA2MUX */
    736. 

  736. #define DAC_OPA2MUX_RESINMUX_DEFAULT          (_DAC_OPA2MUX_RESINMUX_DEFAULT << 8) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
    737. 

  737. #define DAC_OPA2MUX_RESINMUX_DISABLE          (_DAC_OPA2MUX_RESINMUX_DISABLE << 8) /**< Shifted mode DISABLE for DAC_OPA2MUX */
    738. 

  738. #define DAC_OPA2MUX_RESINMUX_OPA1INP          (_DAC_OPA2MUX_RESINMUX_OPA1INP << 8) /**< Shifted mode OPA1INP for DAC_OPA2MUX */
    739. 

  739. #define DAC_OPA2MUX_RESINMUX_NEGPAD           (_DAC_OPA2MUX_RESINMUX_NEGPAD << 8)  /**< Shifted mode NEGPAD for DAC_OPA2MUX */
    740. 

  740. #define DAC_OPA2MUX_RESINMUX_POSPAD           (_DAC_OPA2MUX_RESINMUX_POSPAD << 8)  /**< Shifted mode POSPAD for DAC_OPA2MUX */
    741. 

  741. #define DAC_OPA2MUX_RESINMUX_VSS              (_DAC_OPA2MUX_RESINMUX_VSS << 8)     /**< Shifted mode VSS for DAC_OPA2MUX */
    742. 

  742. #define DAC_OPA2MUX_PPEN                      (0x1UL << 12)                        /**< OPA2 Positive Pad Input Enable */
    743. 

  743. #define _DAC_OPA2MUX_PPEN_SHIFT               12                                   /**< Shift value for DAC_PPEN */
    744. 

  744. #define _DAC_OPA2MUX_PPEN_MASK                0x1000UL                             /**< Bit mask for DAC_PPEN */
    745. 

  745. #define _DAC_OPA2MUX_PPEN_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for DAC_OPA2MUX */
    746. 

  746. #define DAC_OPA2MUX_PPEN_DEFAULT              (_DAC_OPA2MUX_PPEN_DEFAULT << 12)    /**< Shifted mode DEFAULT for DAC_OPA2MUX */
    747. 

  747. #define DAC_OPA2MUX_NPEN                      (0x1UL << 13)                        /**< OPA2 Negative Pad Input Enable */
    748. 

  748. #define _DAC_OPA2MUX_NPEN_SHIFT               13                                   /**< Shift value for DAC_NPEN */
    749. 

  749. #define _DAC_OPA2MUX_NPEN_MASK                0x2000UL                             /**< Bit mask for DAC_NPEN */
    750. 

  750. #define _DAC_OPA2MUX_NPEN_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for DAC_OPA2MUX */
    751. 

  751. #define DAC_OPA2MUX_NPEN_DEFAULT              (_DAC_OPA2MUX_NPEN_DEFAULT << 13)    /**< Shifted mode DEFAULT for DAC_OPA2MUX */
    752. 

  752. #define _DAC_OPA2MUX_OUTPEN_SHIFT             14                                   /**< Shift value for DAC_OUTPEN */
    753. 

  753. #define _DAC_OPA2MUX_OUTPEN_MASK              0xC000UL                             /**< Bit mask for DAC_OUTPEN */
    754. 

  754. #define _DAC_OPA2MUX_OUTPEN_DEFAULT           0x00000000UL                         /**< Mode DEFAULT for DAC_OPA2MUX */
    755. 

  755. #define _DAC_OPA2MUX_OUTPEN_OUT0              0x00000001UL                         /**< Mode OUT0 for DAC_OPA2MUX */
    756. 

  756. #define _DAC_OPA2MUX_OUTPEN_OUT1              0x00000002UL                         /**< Mode OUT1 for DAC_OPA2MUX */
    757. 

  757. #define DAC_OPA2MUX_OUTPEN_DEFAULT            (_DAC_OPA2MUX_OUTPEN_DEFAULT << 14)  /**< Shifted mode DEFAULT for DAC_OPA2MUX */
    758. 

  758. #define DAC_OPA2MUX_OUTPEN_OUT0               (_DAC_OPA2MUX_OUTPEN_OUT0 << 14)     /**< Shifted mode OUT0 for DAC_OPA2MUX */
    759. 

  759. #define DAC_OPA2MUX_OUTPEN_OUT1               (_DAC_OPA2MUX_OUTPEN_OUT1 << 14)     /**< Shifted mode OUT1 for DAC_OPA2MUX */
    760. 

  760. #define DAC_OPA2MUX_OUTMODE                   (0x1UL << 22)                        /**< Output Select */
    761. 

  761. #define _DAC_OPA2MUX_OUTMODE_SHIFT            22                                   /**< Shift value for DAC_OUTMODE */
    762. 

  762. #define _DAC_OPA2MUX_OUTMODE_MASK             0x400000UL                           /**< Bit mask for DAC_OUTMODE */
    763. 

  763. #define _DAC_OPA2MUX_OUTMODE_DEFAULT          0x00000000UL                         /**< Mode DEFAULT for DAC_OPA2MUX */
    764. 

  764. #define DAC_OPA2MUX_OUTMODE_DEFAULT           (_DAC_OPA2MUX_OUTMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
    765. 

  765. #define DAC_OPA2MUX_NEXTOUT                   (0x1UL << 26)                        /**< OPA2 Next Enable */
    766. 

  766. #define _DAC_OPA2MUX_NEXTOUT_SHIFT            26                                   /**< Shift value for DAC_NEXTOUT */
    767. 

  767. #define _DAC_OPA2MUX_NEXTOUT_MASK             0x4000000UL                          /**< Bit mask for DAC_NEXTOUT */
    768. 

  768. #define _DAC_OPA2MUX_NEXTOUT_DEFAULT          0x00000000UL                         /**< Mode DEFAULT for DAC_OPA2MUX */
    769. 

  769. #define DAC_OPA2MUX_NEXTOUT_DEFAULT           (_DAC_OPA2MUX_NEXTOUT_DEFAULT << 26) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
    770. 

  770. #define _DAC_OPA2MUX_RESSEL_SHIFT             28                                   /**< Shift value for DAC_RESSEL */
    771. 

  771. #define _DAC_OPA2MUX_RESSEL_MASK              0x70000000UL                         /**< Bit mask for DAC_RESSEL */
    772. 

  772. #define _DAC_OPA2MUX_RESSEL_DEFAULT           0x00000000UL                         /**< Mode DEFAULT for DAC_OPA2MUX */
    773. 

  773. #define _DAC_OPA2MUX_RESSEL_RES0              0x00000000UL                         /**< Mode RES0 for DAC_OPA2MUX */
    774. 

  774. #define _DAC_OPA2MUX_RESSEL_RES1              0x00000001UL                         /**< Mode RES1 for DAC_OPA2MUX */
    775. 

  775. #define _DAC_OPA2MUX_RESSEL_RES2              0x00000002UL                         /**< Mode RES2 for DAC_OPA2MUX */
    776. 

  776. #define _DAC_OPA2MUX_RESSEL_RES3              0x00000003UL                         /**< Mode RES3 for DAC_OPA2MUX */
    777. 

  777. #define _DAC_OPA2MUX_RESSEL_RES4              0x00000004UL                         /**< Mode RES4 for DAC_OPA2MUX */
    778. 

  778. #define _DAC_OPA2MUX_RESSEL_RES5              0x00000005UL                         /**< Mode RES5 for DAC_OPA2MUX */
    779. 

  779. #define _DAC_OPA2MUX_RESSEL_RES6              0x00000006UL                         /**< Mode RES6 for DAC_OPA2MUX */
    780. 

  780. #define _DAC_OPA2MUX_RESSEL_RES7              0x00000007UL                         /**< Mode RES7 for DAC_OPA2MUX */
    781. 

  781. #define DAC_OPA2MUX_RESSEL_DEFAULT            (_DAC_OPA2MUX_RESSEL_DEFAULT << 28)  /**< Shifted mode DEFAULT for DAC_OPA2MUX */
    782. 

  782. #define DAC_OPA2MUX_RESSEL_RES0               (_DAC_OPA2MUX_RESSEL_RES0 << 28)     /**< Shifted mode RES0 for DAC_OPA2MUX */
    783. 

  783. #define DAC_OPA2MUX_RESSEL_RES1               (_DAC_OPA2MUX_RESSEL_RES1 << 28)     /**< Shifted mode RES1 for DAC_OPA2MUX */
    784. 

  784. #define DAC_OPA2MUX_RESSEL_RES2               (_DAC_OPA2MUX_RESSEL_RES2 << 28)     /**< Shifted mode RES2 for DAC_OPA2MUX */
    785. 

  785. #define DAC_OPA2MUX_RESSEL_RES3               (_DAC_OPA2MUX_RESSEL_RES3 << 28)     /**< Shifted mode RES3 for DAC_OPA2MUX */
    786. 

  786. #define DAC_OPA2MUX_RESSEL_RES4               (_DAC_OPA2MUX_RESSEL_RES4 << 28)     /**< Shifted mode RES4 for DAC_OPA2MUX */
    787. 

  787. #define DAC_OPA2MUX_RESSEL_RES5               (_DAC_OPA2MUX_RESSEL_RES5 << 28)     /**< Shifted mode RES5 for DAC_OPA2MUX */
    788. 

  788. #define DAC_OPA2MUX_RESSEL_RES6               (_DAC_OPA2MUX_RESSEL_RES6 << 28)     /**< Shifted mode RES6 for DAC_OPA2MUX */
    789. 

  789. #define DAC_OPA2MUX_RESSEL_RES7               (_DAC_OPA2MUX_RESSEL_RES7 << 28)     /**< Shifted mode RES7 for DAC_OPA2MUX */
    790. 

  790. 

  791. /** @} End of group EFM32GG_DAC */
    792. 

  792. 

  793.