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efm32gg_ebi.h

efm32gg_ebi.h 165 KB
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  1. /**************************************************************************//**
    2. 

  2.  * @file
    3. 

  3.  * @brief efm32gg_ebi Register and Bit Field definitions
    4. 

  4.  * @author Energy Micro AS
    5. 

  5.  * @version 3.0.0
    6. 

  6.  ******************************************************************************
    7. 

  7.  * @section License
    8. 

  8.  * <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
    9. 

  9.  ******************************************************************************
    10. 

  10.  *
    11. 

  11.  * Permission is granted to anyone to use this software for any purpose,
    12. 

  12.  * including commercial applications, and to alter it and redistribute it
    13. 

  13.  * freely, subject to the following restrictions:
    14. 

  14.  *
    15. 

  15.  * 1. The origin of this software must not be misrepresented; you must not
    16. 

  16.  *    claim that you wrote the original software.
    17. 

  17.  * 2. Altered source versions must be plainly marked as such, and must not be
    18. 

  18.  *    misrepresented as being the original software.
    19. 

  19.  * 3. This notice may not be removed or altered from any source distribution.
    20. 

  20.  *
    21. 

  21.  * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
    22. 

  22.  * obligation to support this Software. Energy Micro AS is providing the
    23. 

  23.  * Software "AS IS", with no express or implied warranties of any kind,
    24. 

  24.  * including, but not limited to, any implied warranties of merchantability
    25. 

  25.  * or fitness for any particular purpose or warranties against infringement
    26. 

  26.  * of any proprietary rights of a third party.
    27. 

  27.  *
    28. 

  28.  * Energy Micro AS will not be liable for any consequential, incidental, or
    29. 

  29.  * special damages, or any other relief, or for any claim by any third party,
    30. 

  30.  * arising from your use of this Software.
    31. 

  31.  *
    32. 

  32.  *****************************************************************************/
    33. 

  33. /**************************************************************************//**
    34. 

  34.  * @defgroup EFM32GG_EBI
    35. 

  35.  * @{
    36. 

  36.  * @brief EFM32GG_EBI Register Declaration
    37. 

  37.  *****************************************************************************/
    38. 

  38. typedef struct
    39. 

  39. {
    40. 

  40.   __IO uint32_t CTRL;         /**< Control Register  */
    41. 

  41.   __IO uint32_t ADDRTIMING;   /**< Address Timing Register  */
    42. 

  42.   __IO uint32_t RDTIMING;     /**< Read Timing Register  */
    43. 

  43.   __IO uint32_t WRTIMING;     /**< Write Timing Register  */
    44. 

  44.   __IO uint32_t POLARITY;     /**< Polarity Register  */
    45. 

  45.   __IO uint32_t ROUTE;        /**< I/O Routing Register  */
    46. 

  46.   __IO uint32_t ADDRTIMING1;  /**< Address Timing Register 1  */
    47. 

  47.   __IO uint32_t RDTIMING1;    /**< Read Timing Register 1  */
    48. 

  48.   __IO uint32_t WRTIMING1;    /**< Write Timing Register 1  */
    49. 

  49.   __IO uint32_t POLARITY1;    /**< Polarity Register 1  */
    50. 

  50.   __IO uint32_t ADDRTIMING2;  /**< Address Timing Register 2  */
    51. 

  51.   __IO uint32_t RDTIMING2;    /**< Read Timing Register 2  */
    52. 

  52.   __IO uint32_t WRTIMING2;    /**< Write Timing Register 2  */
    53. 

  53.   __IO uint32_t POLARITY2;    /**< Polarity Register 2  */
    54. 

  54.   __IO uint32_t ADDRTIMING3;  /**< Address Timing Register 3  */
    55. 

  55.   __IO uint32_t RDTIMING3;    /**< Read Timing Register 3  */
    56. 

  56.   __IO uint32_t WRTIMING3;    /**< Write Timing Register 3  */
    57. 

  57.   __IO uint32_t POLARITY3;    /**< Polarity Register 3  */
    58. 

  58.   __IO uint32_t PAGECTRL;     /**< Page Control Register  */
    59. 

  59.   __IO uint32_t NANDCTRL;     /**< NAND Control Register  */
    60. 

  60.   __IO uint32_t CMD;          /**< Command Register  */
    61. 

  61.   __I uint32_t  STATUS;       /**< Status Register  */
    62. 

  62.   __I uint32_t  ECCPARITY;    /**< ECC Parity register  */
    63. 

  63.   __IO uint32_t TFTCTRL;      /**< TFT Control Register  */
    64. 

  64.   __I uint32_t  TFTSTATUS;    /**< TFT Status Register  */
    65. 

  65.   __IO uint32_t TFTFRAMEBASE; /**< TFT Frame Base Register  */
    66. 

  66.   __IO uint32_t TFTSTRIDE;    /**< TFT Stride Register  */
    67. 

  67.   __IO uint32_t TFTSIZE;      /**< TFT Size Register  */
    68. 

  68.   __IO uint32_t TFTHPORCH;    /**< TFT Horizontal Porch Register  */
    69. 

  69.   __IO uint32_t TFTVPORCH;    /**< TFT Vertical Porch Register  */
    70. 

  70.   __IO uint32_t TFTTIMING;    /**< TFT Timing Register  */
    71. 

  71.   __IO uint32_t TFTPOLARITY;  /**< TFT Polarity Register  */
    72. 

  72.   __IO uint32_t TFTDD;        /**< TFT Direct Drive Data Register  */
    73. 

  73.   __IO uint32_t TFTALPHA;     /**< TFT Alpha Blending Register  */
    74. 

  74.   __IO uint32_t TFTPIXEL0;    /**< TFT Pixel 0 Register  */
    75. 

  75.   __IO uint32_t TFTPIXEL1;    /**< TFT Pixel 1 Register  */
    76. 

  76.   __I uint32_t  TFTPIXEL;     /**< TFT Alpha Blending Result Pixel Register  */
    77. 

  77.   __IO uint32_t TFTMASK;      /**< TFT Masking Register  */
    78. 

  78.   __I uint32_t  IF;           /**< Interrupt Flag Register  */
    79. 

  79.   __IO uint32_t IFS;          /**< Interrupt Flag Set Register  */
    80. 

  80.   __IO uint32_t IFC;          /**< Interrupt Flag Clear Register  */
    81. 

  81.   __IO uint32_t IEN;          /**< Interrupt Enable Register  */
    82. 

  82. } EBI_TypeDef;                /** @} */
    83. 

  83. 

  84. /**************************************************************************//**
    85. 

  85.  * @defgroup EFM32GG_EBI_BitFields
    86. 

  86.  * @{
    87. 

  87.  *****************************************************************************/
    88. 

  88. 

  89. /* Bit fields for EBI CTRL */
    90. 

  90. #define _EBI_CTRL_RESETVALUE                      0x00000000UL                         /**< Default value for EBI_CTRL */
    91. 

  91. #define _EBI_CTRL_MASK                            0xEFFFFFFFUL                         /**< Mask for EBI_CTRL */
    92. 

  92. #define _EBI_CTRL_MODE_SHIFT                      0                                    /**< Shift value for EBI_MODE */
    93. 

  93. #define _EBI_CTRL_MODE_MASK                       0x3UL                                /**< Bit mask for EBI_MODE */
    94. 

  94. #define _EBI_CTRL_MODE_DEFAULT                    0x00000000UL                         /**< Mode DEFAULT for EBI_CTRL */
    95. 

  95. #define _EBI_CTRL_MODE_D8A8                       0x00000000UL                         /**< Mode D8A8 for EBI_CTRL */
    96. 

  96. #define _EBI_CTRL_MODE_D16A16ALE                  0x00000001UL                         /**< Mode D16A16ALE for EBI_CTRL */
    97. 

  97. #define _EBI_CTRL_MODE_D8A24ALE                   0x00000002UL                         /**< Mode D8A24ALE for EBI_CTRL */
    98. 

  98. #define _EBI_CTRL_MODE_D16                        0x00000003UL                         /**< Mode D16 for EBI_CTRL */
    99. 

  99. #define EBI_CTRL_MODE_DEFAULT                     (_EBI_CTRL_MODE_DEFAULT << 0)        /**< Shifted mode DEFAULT for EBI_CTRL */
    100. 

  100. #define EBI_CTRL_MODE_D8A8                        (_EBI_CTRL_MODE_D8A8 << 0)           /**< Shifted mode D8A8 for EBI_CTRL */
    101. 

  101. #define EBI_CTRL_MODE_D16A16ALE                   (_EBI_CTRL_MODE_D16A16ALE << 0)      /**< Shifted mode D16A16ALE for EBI_CTRL */
    102. 

  102. #define EBI_CTRL_MODE_D8A24ALE                    (_EBI_CTRL_MODE_D8A24ALE << 0)       /**< Shifted mode D8A24ALE for EBI_CTRL */
    103. 

  103. #define EBI_CTRL_MODE_D16                         (_EBI_CTRL_MODE_D16 << 0)            /**< Shifted mode D16 for EBI_CTRL */
    104. 

  104. #define _EBI_CTRL_MODE1_SHIFT                     2                                    /**< Shift value for EBI_MODE1 */
    105. 

  105. #define _EBI_CTRL_MODE1_MASK                      0xCUL                                /**< Bit mask for EBI_MODE1 */
    106. 

  106. #define _EBI_CTRL_MODE1_DEFAULT                   0x00000000UL                         /**< Mode DEFAULT for EBI_CTRL */
    107. 

  107. #define _EBI_CTRL_MODE1_D8A8                      0x00000000UL                         /**< Mode D8A8 for EBI_CTRL */
    108. 

  108. #define _EBI_CTRL_MODE1_D16A16ALE                 0x00000001UL                         /**< Mode D16A16ALE for EBI_CTRL */
    109. 

  109. #define _EBI_CTRL_MODE1_D8A24ALE                  0x00000002UL                         /**< Mode D8A24ALE for EBI_CTRL */
    110. 

  110. #define _EBI_CTRL_MODE1_D16                       0x00000003UL                         /**< Mode D16 for EBI_CTRL */
    111. 

  111. #define EBI_CTRL_MODE1_DEFAULT                    (_EBI_CTRL_MODE1_DEFAULT << 2)       /**< Shifted mode DEFAULT for EBI_CTRL */
    112. 

  112. #define EBI_CTRL_MODE1_D8A8                       (_EBI_CTRL_MODE1_D8A8 << 2)          /**< Shifted mode D8A8 for EBI_CTRL */
    113. 

  113. #define EBI_CTRL_MODE1_D16A16ALE                  (_EBI_CTRL_MODE1_D16A16ALE << 2)     /**< Shifted mode D16A16ALE for EBI_CTRL */
    114. 

  114. #define EBI_CTRL_MODE1_D8A24ALE                   (_EBI_CTRL_MODE1_D8A24ALE << 2)      /**< Shifted mode D8A24ALE for EBI_CTRL */
    115. 

  115. #define EBI_CTRL_MODE1_D16                        (_EBI_CTRL_MODE1_D16 << 2)           /**< Shifted mode D16 for EBI_CTRL */
    116. 

  116. #define _EBI_CTRL_MODE2_SHIFT                     4                                    /**< Shift value for EBI_MODE2 */
    117. 

  117. #define _EBI_CTRL_MODE2_MASK                      0x30UL                               /**< Bit mask for EBI_MODE2 */
    118. 

  118. #define _EBI_CTRL_MODE2_DEFAULT                   0x00000000UL                         /**< Mode DEFAULT for EBI_CTRL */
    119. 

  119. #define _EBI_CTRL_MODE2_D8A8                      0x00000000UL                         /**< Mode D8A8 for EBI_CTRL */
    120. 

  120. #define _EBI_CTRL_MODE2_D16A16ALE                 0x00000001UL                         /**< Mode D16A16ALE for EBI_CTRL */
    121. 

  121. #define _EBI_CTRL_MODE2_D8A24ALE                  0x00000002UL                         /**< Mode D8A24ALE for EBI_CTRL */
    122. 

  122. #define _EBI_CTRL_MODE2_D16                       0x00000003UL                         /**< Mode D16 for EBI_CTRL */
    123. 

  123. #define EBI_CTRL_MODE2_DEFAULT                    (_EBI_CTRL_MODE2_DEFAULT << 4)       /**< Shifted mode DEFAULT for EBI_CTRL */
    124. 

  124. #define EBI_CTRL_MODE2_D8A8                       (_EBI_CTRL_MODE2_D8A8 << 4)          /**< Shifted mode D8A8 for EBI_CTRL */
    125. 

  125. #define EBI_CTRL_MODE2_D16A16ALE                  (_EBI_CTRL_MODE2_D16A16ALE << 4)     /**< Shifted mode D16A16ALE for EBI_CTRL */
    126. 

  126. #define EBI_CTRL_MODE2_D8A24ALE                   (_EBI_CTRL_MODE2_D8A24ALE << 4)      /**< Shifted mode D8A24ALE for EBI_CTRL */
    127. 

  127. #define EBI_CTRL_MODE2_D16                        (_EBI_CTRL_MODE2_D16 << 4)           /**< Shifted mode D16 for EBI_CTRL */
    128. 

  128. #define _EBI_CTRL_MODE3_SHIFT                     6                                    /**< Shift value for EBI_MODE3 */
    129. 

  129. #define _EBI_CTRL_MODE3_MASK                      0xC0UL                               /**< Bit mask for EBI_MODE3 */
    130. 

  130. #define _EBI_CTRL_MODE3_DEFAULT                   0x00000000UL                         /**< Mode DEFAULT for EBI_CTRL */
    131. 

  131. #define _EBI_CTRL_MODE3_D8A8                      0x00000000UL                         /**< Mode D8A8 for EBI_CTRL */
    132. 

  132. #define _EBI_CTRL_MODE3_D16A16ALE                 0x00000001UL                         /**< Mode D16A16ALE for EBI_CTRL */
    133. 

  133. #define _EBI_CTRL_MODE3_D8A24ALE                  0x00000002UL                         /**< Mode D8A24ALE for EBI_CTRL */
    134. 

  134. #define _EBI_CTRL_MODE3_D16                       0x00000003UL                         /**< Mode D16 for EBI_CTRL */
    135. 

  135. #define EBI_CTRL_MODE3_DEFAULT                    (_EBI_CTRL_MODE3_DEFAULT << 6)       /**< Shifted mode DEFAULT for EBI_CTRL */
    136. 

  136. #define EBI_CTRL_MODE3_D8A8                       (_EBI_CTRL_MODE3_D8A8 << 6)          /**< Shifted mode D8A8 for EBI_CTRL */
    137. 

  137. #define EBI_CTRL_MODE3_D16A16ALE                  (_EBI_CTRL_MODE3_D16A16ALE << 6)     /**< Shifted mode D16A16ALE for EBI_CTRL */
    138. 

  138. #define EBI_CTRL_MODE3_D8A24ALE                   (_EBI_CTRL_MODE3_D8A24ALE << 6)      /**< Shifted mode D8A24ALE for EBI_CTRL */
    139. 

  139. #define EBI_CTRL_MODE3_D16                        (_EBI_CTRL_MODE3_D16 << 6)           /**< Shifted mode D16 for EBI_CTRL */
    140. 

  140. #define EBI_CTRL_BANK0EN                          (0x1UL << 8)                         /**< Bank 0 Enable */
    141. 

  141. #define _EBI_CTRL_BANK0EN_SHIFT                   8                                    /**< Shift value for EBI_BANK0EN */
    142. 

  142. #define _EBI_CTRL_BANK0EN_MASK                    0x100UL                              /**< Bit mask for EBI_BANK0EN */
    143. 

  143. #define _EBI_CTRL_BANK0EN_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for EBI_CTRL */
    144. 

  144. #define EBI_CTRL_BANK0EN_DEFAULT                  (_EBI_CTRL_BANK0EN_DEFAULT << 8)     /**< Shifted mode DEFAULT for EBI_CTRL */
    145. 

  145. #define EBI_CTRL_BANK1EN                          (0x1UL << 9)                         /**< Bank 1 Enable */
    146. 

  146. #define _EBI_CTRL_BANK1EN_SHIFT                   9                                    /**< Shift value for EBI_BANK1EN */
    147. 

  147. #define _EBI_CTRL_BANK1EN_MASK                    0x200UL                              /**< Bit mask for EBI_BANK1EN */
    148. 

  148. #define _EBI_CTRL_BANK1EN_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for EBI_CTRL */
    149. 

  149. #define EBI_CTRL_BANK1EN_DEFAULT                  (_EBI_CTRL_BANK1EN_DEFAULT << 9)     /**< Shifted mode DEFAULT for EBI_CTRL */
    150. 

  150. #define EBI_CTRL_BANK2EN                          (0x1UL << 10)                        /**< Bank 2 Enable */
    151. 

  151. #define _EBI_CTRL_BANK2EN_SHIFT                   10                                   /**< Shift value for EBI_BANK2EN */
    152. 

  152. #define _EBI_CTRL_BANK2EN_MASK                    0x400UL                              /**< Bit mask for EBI_BANK2EN */
    153. 

  153. #define _EBI_CTRL_BANK2EN_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for EBI_CTRL */
    154. 

  154. #define EBI_CTRL_BANK2EN_DEFAULT                  (_EBI_CTRL_BANK2EN_DEFAULT << 10)    /**< Shifted mode DEFAULT for EBI_CTRL */
    155. 

  155. #define EBI_CTRL_BANK3EN                          (0x1UL << 11)                        /**< Bank 3 Enable */
    156. 

  156. #define _EBI_CTRL_BANK3EN_SHIFT                   11                                   /**< Shift value for EBI_BANK3EN */
    157. 

  157. #define _EBI_CTRL_BANK3EN_MASK                    0x800UL                              /**< Bit mask for EBI_BANK3EN */
    158. 

  158. #define _EBI_CTRL_BANK3EN_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for EBI_CTRL */
    159. 

  159. #define EBI_CTRL_BANK3EN_DEFAULT                  (_EBI_CTRL_BANK3EN_DEFAULT << 11)    /**< Shifted mode DEFAULT for EBI_CTRL */
    160. 

  160. #define EBI_CTRL_NOIDLE                           (0x1UL << 12)                        /**< No idle cycle insertion on bank 0. */
    161. 

  161. #define _EBI_CTRL_NOIDLE_SHIFT                    12                                   /**< Shift value for EBI_NOIDLE */
    162. 

  162. #define _EBI_CTRL_NOIDLE_MASK                     0x1000UL                             /**< Bit mask for EBI_NOIDLE */
    163. 

  163. #define _EBI_CTRL_NOIDLE_DEFAULT                  0x00000000UL                         /**< Mode DEFAULT for EBI_CTRL */
    164. 

  164. #define EBI_CTRL_NOIDLE_DEFAULT                   (_EBI_CTRL_NOIDLE_DEFAULT << 12)     /**< Shifted mode DEFAULT for EBI_CTRL */
    165. 

  165. #define EBI_CTRL_NOIDLE1                          (0x1UL << 13)                        /**< No idle cycle insertion on bank 1. */
    166. 

  166. #define _EBI_CTRL_NOIDLE1_SHIFT                   13                                   /**< Shift value for EBI_NOIDLE1 */
    167. 

  167. #define _EBI_CTRL_NOIDLE1_MASK                    0x2000UL                             /**< Bit mask for EBI_NOIDLE1 */
    168. 

  168. #define _EBI_CTRL_NOIDLE1_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for EBI_CTRL */
    169. 

  169. #define EBI_CTRL_NOIDLE1_DEFAULT                  (_EBI_CTRL_NOIDLE1_DEFAULT << 13)    /**< Shifted mode DEFAULT for EBI_CTRL */
    170. 

  170. #define EBI_CTRL_NOIDLE2                          (0x1UL << 14)                        /**< No idle cycle insertion on bank 2. */
    171. 

  171. #define _EBI_CTRL_NOIDLE2_SHIFT                   14                                   /**< Shift value for EBI_NOIDLE2 */
    172. 

  172. #define _EBI_CTRL_NOIDLE2_MASK                    0x4000UL                             /**< Bit mask for EBI_NOIDLE2 */
    173. 

  173. #define _EBI_CTRL_NOIDLE2_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for EBI_CTRL */
    174. 

  174. #define EBI_CTRL_NOIDLE2_DEFAULT                  (_EBI_CTRL_NOIDLE2_DEFAULT << 14)    /**< Shifted mode DEFAULT for EBI_CTRL */
    175. 

  175. #define EBI_CTRL_NOIDLE3                          (0x1UL << 15)                        /**< No idle cycle insertion on bank 3. */
    176. 

  176. #define _EBI_CTRL_NOIDLE3_SHIFT                   15                                   /**< Shift value for EBI_NOIDLE3 */
    177. 

  177. #define _EBI_CTRL_NOIDLE3_MASK                    0x8000UL                             /**< Bit mask for EBI_NOIDLE3 */
    178. 

  178. #define _EBI_CTRL_NOIDLE3_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for EBI_CTRL */
    179. 

  179. #define EBI_CTRL_NOIDLE3_DEFAULT                  (_EBI_CTRL_NOIDLE3_DEFAULT << 15)    /**< Shifted mode DEFAULT for EBI_CTRL */
    180. 

  180. #define EBI_CTRL_ARDYEN                           (0x1UL << 16)                        /**< ARDY Enable */
    181. 

  181. #define _EBI_CTRL_ARDYEN_SHIFT                    16                                   /**< Shift value for EBI_ARDYEN */
    182. 

  182. #define _EBI_CTRL_ARDYEN_MASK                     0x10000UL                            /**< Bit mask for EBI_ARDYEN */
    183. 

  183. #define _EBI_CTRL_ARDYEN_DEFAULT                  0x00000000UL                         /**< Mode DEFAULT for EBI_CTRL */
    184. 

  184. #define EBI_CTRL_ARDYEN_DEFAULT                   (_EBI_CTRL_ARDYEN_DEFAULT << 16)     /**< Shifted mode DEFAULT for EBI_CTRL */
    185. 

  185. #define EBI_CTRL_ARDYTODIS                        (0x1UL << 17)                        /**< ARDY Timeout Disable */
    186. 

  186. #define _EBI_CTRL_ARDYTODIS_SHIFT                 17                                   /**< Shift value for EBI_ARDYTODIS */
    187. 

  187. #define _EBI_CTRL_ARDYTODIS_MASK                  0x20000UL                            /**< Bit mask for EBI_ARDYTODIS */
    188. 

  188. #define _EBI_CTRL_ARDYTODIS_DEFAULT               0x00000000UL                         /**< Mode DEFAULT for EBI_CTRL */
    189. 

  189. #define EBI_CTRL_ARDYTODIS_DEFAULT                (_EBI_CTRL_ARDYTODIS_DEFAULT << 17)  /**< Shifted mode DEFAULT for EBI_CTRL */
    190. 

  190. #define EBI_CTRL_ARDY1EN                          (0x1UL << 18)                        /**< ARDY Enable for bank 1 */
    191. 

  191. #define _EBI_CTRL_ARDY1EN_SHIFT                   18                                   /**< Shift value for EBI_ARDY1EN */
    192. 

  192. #define _EBI_CTRL_ARDY1EN_MASK                    0x40000UL                            /**< Bit mask for EBI_ARDY1EN */
    193. 

  193. #define _EBI_CTRL_ARDY1EN_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for EBI_CTRL */
    194. 

  194. #define EBI_CTRL_ARDY1EN_DEFAULT                  (_EBI_CTRL_ARDY1EN_DEFAULT << 18)    /**< Shifted mode DEFAULT for EBI_CTRL */
    195. 

  195. #define EBI_CTRL_ARDYTO1DIS                       (0x1UL << 19)                        /**< ARDY Timeout Disable for bank 1 */
    196. 

  196. #define _EBI_CTRL_ARDYTO1DIS_SHIFT                19                                   /**< Shift value for EBI_ARDYTO1DIS */
    197. 

  197. #define _EBI_CTRL_ARDYTO1DIS_MASK                 0x80000UL                            /**< Bit mask for EBI_ARDYTO1DIS */
    198. 

  198. #define _EBI_CTRL_ARDYTO1DIS_DEFAULT              0x00000000UL                         /**< Mode DEFAULT for EBI_CTRL */
    199. 

  199. #define EBI_CTRL_ARDYTO1DIS_DEFAULT               (_EBI_CTRL_ARDYTO1DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EBI_CTRL */
    200. 

  200. #define EBI_CTRL_ARDY2EN                          (0x1UL << 20)                        /**< ARDY Enable for bank 2 */
    201. 

  201. #define _EBI_CTRL_ARDY2EN_SHIFT                   20                                   /**< Shift value for EBI_ARDY2EN */
    202. 

  202. #define _EBI_CTRL_ARDY2EN_MASK                    0x100000UL                           /**< Bit mask for EBI_ARDY2EN */
    203. 

  203. #define _EBI_CTRL_ARDY2EN_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for EBI_CTRL */
    204. 

  204. #define EBI_CTRL_ARDY2EN_DEFAULT                  (_EBI_CTRL_ARDY2EN_DEFAULT << 20)    /**< Shifted mode DEFAULT for EBI_CTRL */
    205. 

  205. #define EBI_CTRL_ARDYTO2DIS                       (0x1UL << 21)                        /**< ARDY Timeout Disable for bank 2 */
    206. 

  206. #define _EBI_CTRL_ARDYTO2DIS_SHIFT                21                                   /**< Shift value for EBI_ARDYTO2DIS */
    207. 

  207. #define _EBI_CTRL_ARDYTO2DIS_MASK                 0x200000UL                           /**< Bit mask for EBI_ARDYTO2DIS */
    208. 

  208. #define _EBI_CTRL_ARDYTO2DIS_DEFAULT              0x00000000UL                         /**< Mode DEFAULT for EBI_CTRL */
    209. 

  209. #define EBI_CTRL_ARDYTO2DIS_DEFAULT               (_EBI_CTRL_ARDYTO2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EBI_CTRL */
    210. 

  210. #define EBI_CTRL_ARDY3EN                          (0x1UL << 22)                        /**< ARDY Enable for bank 3 */
    211. 

  211. #define _EBI_CTRL_ARDY3EN_SHIFT                   22                                   /**< Shift value for EBI_ARDY3EN */
    212. 

  212. #define _EBI_CTRL_ARDY3EN_MASK                    0x400000UL                           /**< Bit mask for EBI_ARDY3EN */
    213. 

  213. #define _EBI_CTRL_ARDY3EN_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for EBI_CTRL */
    214. 

  214. #define EBI_CTRL_ARDY3EN_DEFAULT                  (_EBI_CTRL_ARDY3EN_DEFAULT << 22)    /**< Shifted mode DEFAULT for EBI_CTRL */
    215. 

  215. #define EBI_CTRL_ARDYTO3DIS                       (0x1UL << 23)                        /**< ARDY Timeout Disable for bank 3 */
    216. 

  216. #define _EBI_CTRL_ARDYTO3DIS_SHIFT                23                                   /**< Shift value for EBI_ARDYTO3DIS */
    217. 

  217. #define _EBI_CTRL_ARDYTO3DIS_MASK                 0x800000UL                           /**< Bit mask for EBI_ARDYTO3DIS */
    218. 

  218. #define _EBI_CTRL_ARDYTO3DIS_DEFAULT              0x00000000UL                         /**< Mode DEFAULT for EBI_CTRL */
    219. 

  219. #define EBI_CTRL_ARDYTO3DIS_DEFAULT               (_EBI_CTRL_ARDYTO3DIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EBI_CTRL */
    220. 

  220. #define EBI_CTRL_BL                               (0x1UL << 24)                        /**< Byte Lane Enable for bank 0 */
    221. 

  221. #define _EBI_CTRL_BL_SHIFT                        24                                   /**< Shift value for EBI_BL */
    222. 

  222. #define _EBI_CTRL_BL_MASK                         0x1000000UL                          /**< Bit mask for EBI_BL */
    223. 

  223. #define _EBI_CTRL_BL_DEFAULT                      0x00000000UL                         /**< Mode DEFAULT for EBI_CTRL */
    224. 

  224. #define EBI_CTRL_BL_DEFAULT                       (_EBI_CTRL_BL_DEFAULT << 24)         /**< Shifted mode DEFAULT for EBI_CTRL */
    225. 

  225. #define EBI_CTRL_BL1                              (0x1UL << 25)                        /**< Byte Lane Enable for bank 1 */
    226. 

  226. #define _EBI_CTRL_BL1_SHIFT                       25                                   /**< Shift value for EBI_BL1 */
    227. 

  227. #define _EBI_CTRL_BL1_MASK                        0x2000000UL                          /**< Bit mask for EBI_BL1 */
    228. 

  228. #define _EBI_CTRL_BL1_DEFAULT                     0x00000000UL                         /**< Mode DEFAULT for EBI_CTRL */
    229. 

  229. #define EBI_CTRL_BL1_DEFAULT                      (_EBI_CTRL_BL1_DEFAULT << 25)        /**< Shifted mode DEFAULT for EBI_CTRL */
    230. 

  230. #define EBI_CTRL_BL2                              (0x1UL << 26)                        /**< Byte Lane Enable for bank 2 */
    231. 

  231. #define _EBI_CTRL_BL2_SHIFT                       26                                   /**< Shift value for EBI_BL2 */
    232. 

  232. #define _EBI_CTRL_BL2_MASK                        0x4000000UL                          /**< Bit mask for EBI_BL2 */
    233. 

  233. #define _EBI_CTRL_BL2_DEFAULT                     0x00000000UL                         /**< Mode DEFAULT for EBI_CTRL */
    234. 

  234. #define EBI_CTRL_BL2_DEFAULT                      (_EBI_CTRL_BL2_DEFAULT << 26)        /**< Shifted mode DEFAULT for EBI_CTRL */
    235. 

  235. #define EBI_CTRL_BL3                              (0x1UL << 27)                        /**< Byte Lane Enable for bank 3 */
    236. 

  236. #define _EBI_CTRL_BL3_SHIFT                       27                                   /**< Shift value for EBI_BL3 */
    237. 

  237. #define _EBI_CTRL_BL3_MASK                        0x8000000UL                          /**< Bit mask for EBI_BL3 */
    238. 

  238. #define _EBI_CTRL_BL3_DEFAULT                     0x00000000UL                         /**< Mode DEFAULT for EBI_CTRL */
    239. 

  239. #define EBI_CTRL_BL3_DEFAULT                      (_EBI_CTRL_BL3_DEFAULT << 27)        /**< Shifted mode DEFAULT for EBI_CTRL */
    240. 

  240. #define EBI_CTRL_ITS                              (0x1UL << 30)                        /**< Individual Timing Set, Line Polarity and Mode Definition Enable */
    241. 

  241. #define _EBI_CTRL_ITS_SHIFT                       30                                   /**< Shift value for EBI_ITS */
    242. 

  242. #define _EBI_CTRL_ITS_MASK                        0x40000000UL                         /**< Bit mask for EBI_ITS */
    243. 

  243. #define _EBI_CTRL_ITS_DEFAULT                     0x00000000UL                         /**< Mode DEFAULT for EBI_CTRL */
    244. 

  244. #define EBI_CTRL_ITS_DEFAULT                      (_EBI_CTRL_ITS_DEFAULT << 30)        /**< Shifted mode DEFAULT for EBI_CTRL */
    245. 

  245. #define EBI_CTRL_ALTMAP                           (0x1UL << 31)                        /**< Alternative Address Map Enable */
    246. 

  246. #define _EBI_CTRL_ALTMAP_SHIFT                    31                                   /**< Shift value for EBI_ALTMAP */
    247. 

  247. #define _EBI_CTRL_ALTMAP_MASK                     0x80000000UL                         /**< Bit mask for EBI_ALTMAP */
    248. 

  248. #define _EBI_CTRL_ALTMAP_DEFAULT                  0x00000000UL                         /**< Mode DEFAULT for EBI_CTRL */
    249. 

  249. #define EBI_CTRL_ALTMAP_DEFAULT                   (_EBI_CTRL_ALTMAP_DEFAULT << 31)     /**< Shifted mode DEFAULT for EBI_CTRL */
    250. 

  250. 

  251. /* Bit fields for EBI ADDRTIMING */
    252. 

  252. #define _EBI_ADDRTIMING_RESETVALUE                0x00000303UL                             /**< Default value for EBI_ADDRTIMING */
    253. 

  253. #define _EBI_ADDRTIMING_MASK                      0x10000303UL                             /**< Mask for EBI_ADDRTIMING */
    254. 

  254. #define _EBI_ADDRTIMING_ADDRSETUP_SHIFT           0                                        /**< Shift value for EBI_ADDRSETUP */
    255. 

  255. #define _EBI_ADDRTIMING_ADDRSETUP_MASK            0x3UL                                    /**< Bit mask for EBI_ADDRSETUP */
    256. 

  256. #define _EBI_ADDRTIMING_ADDRSETUP_DEFAULT         0x00000003UL                             /**< Mode DEFAULT for EBI_ADDRTIMING */
    257. 

  257. #define EBI_ADDRTIMING_ADDRSETUP_DEFAULT          (_EBI_ADDRTIMING_ADDRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ADDRTIMING */
    258. 

  258. #define _EBI_ADDRTIMING_ADDRHOLD_SHIFT            8                                        /**< Shift value for EBI_ADDRHOLD */
    259. 

  259. #define _EBI_ADDRTIMING_ADDRHOLD_MASK             0x300UL                                  /**< Bit mask for EBI_ADDRHOLD */
    260. 

  260. #define _EBI_ADDRTIMING_ADDRHOLD_DEFAULT          0x00000003UL                             /**< Mode DEFAULT for EBI_ADDRTIMING */
    261. 

  261. #define EBI_ADDRTIMING_ADDRHOLD_DEFAULT           (_EBI_ADDRTIMING_ADDRHOLD_DEFAULT << 8)  /**< Shifted mode DEFAULT for EBI_ADDRTIMING */
    262. 

  262. #define EBI_ADDRTIMING_HALFALE                    (0x1UL << 28)                            /**< Half Cycle ALE Strobe Duration Enable */
    263. 

  263. #define _EBI_ADDRTIMING_HALFALE_SHIFT             28                                       /**< Shift value for EBI_HALFALE */
    264. 

  264. #define _EBI_ADDRTIMING_HALFALE_MASK              0x10000000UL                             /**< Bit mask for EBI_HALFALE */
    265. 

  265. #define _EBI_ADDRTIMING_HALFALE_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for EBI_ADDRTIMING */
    266. 

  266. #define EBI_ADDRTIMING_HALFALE_DEFAULT            (_EBI_ADDRTIMING_HALFALE_DEFAULT << 28)  /**< Shifted mode DEFAULT for EBI_ADDRTIMING */
    267. 

  267. 

  268. /* Bit fields for EBI RDTIMING */
    269. 

  269. #define _EBI_RDTIMING_RESETVALUE                  0x00033F03UL                           /**< Default value for EBI_RDTIMING */
    270. 

  270. #define _EBI_RDTIMING_MASK                        0x70033F03UL                           /**< Mask for EBI_RDTIMING */
    271. 

  271. #define _EBI_RDTIMING_RDSETUP_SHIFT               0                                      /**< Shift value for EBI_RDSETUP */
    272. 

  272. #define _EBI_RDTIMING_RDSETUP_MASK                0x3UL                                  /**< Bit mask for EBI_RDSETUP */
    273. 

  273. #define _EBI_RDTIMING_RDSETUP_DEFAULT             0x00000003UL                           /**< Mode DEFAULT for EBI_RDTIMING */
    274. 

  274. #define EBI_RDTIMING_RDSETUP_DEFAULT              (_EBI_RDTIMING_RDSETUP_DEFAULT << 0)   /**< Shifted mode DEFAULT for EBI_RDTIMING */
    275. 

  275. #define _EBI_RDTIMING_RDSTRB_SHIFT                8                                      /**< Shift value for EBI_RDSTRB */
    276. 

  276. #define _EBI_RDTIMING_RDSTRB_MASK                 0x3F00UL                               /**< Bit mask for EBI_RDSTRB */
    277. 

  277. #define _EBI_RDTIMING_RDSTRB_DEFAULT              0x0000003FUL                           /**< Mode DEFAULT for EBI_RDTIMING */
    278. 

  278. #define EBI_RDTIMING_RDSTRB_DEFAULT               (_EBI_RDTIMING_RDSTRB_DEFAULT << 8)    /**< Shifted mode DEFAULT for EBI_RDTIMING */
    279. 

  279. #define _EBI_RDTIMING_RDHOLD_SHIFT                16                                     /**< Shift value for EBI_RDHOLD */
    280. 

  280. #define _EBI_RDTIMING_RDHOLD_MASK                 0x30000UL                              /**< Bit mask for EBI_RDHOLD */
    281. 

  281. #define _EBI_RDTIMING_RDHOLD_DEFAULT              0x00000003UL                           /**< Mode DEFAULT for EBI_RDTIMING */
    282. 

  282. #define EBI_RDTIMING_RDHOLD_DEFAULT               (_EBI_RDTIMING_RDHOLD_DEFAULT << 16)   /**< Shifted mode DEFAULT for EBI_RDTIMING */
    283. 

  283. #define EBI_RDTIMING_HALFRE                       (0x1UL << 28)                          /**< Half Cycle REn Strobe Duration Enable */
    284. 

  284. #define _EBI_RDTIMING_HALFRE_SHIFT                28                                     /**< Shift value for EBI_HALFRE */
    285. 

  285. #define _EBI_RDTIMING_HALFRE_MASK                 0x10000000UL                           /**< Bit mask for EBI_HALFRE */
    286. 

  286. #define _EBI_RDTIMING_HALFRE_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for EBI_RDTIMING */
    287. 

  287. #define EBI_RDTIMING_HALFRE_DEFAULT               (_EBI_RDTIMING_HALFRE_DEFAULT << 28)   /**< Shifted mode DEFAULT for EBI_RDTIMING */
    288. 

  288. #define EBI_RDTIMING_PREFETCH                     (0x1UL << 29)                          /**< Prefetch Enable */
    289. 

  289. #define _EBI_RDTIMING_PREFETCH_SHIFT              29                                     /**< Shift value for EBI_PREFETCH */
    290. 

  290. #define _EBI_RDTIMING_PREFETCH_MASK               0x20000000UL                           /**< Bit mask for EBI_PREFETCH */
    291. 

  291. #define _EBI_RDTIMING_PREFETCH_DEFAULT            0x00000000UL                           /**< Mode DEFAULT for EBI_RDTIMING */
    292. 

  292. #define EBI_RDTIMING_PREFETCH_DEFAULT             (_EBI_RDTIMING_PREFETCH_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_RDTIMING */
    293. 

  293. #define EBI_RDTIMING_PAGEMODE                     (0x1UL << 30)                          /**< Page Mode Access Enable */
    294. 

  294. #define _EBI_RDTIMING_PAGEMODE_SHIFT              30                                     /**< Shift value for EBI_PAGEMODE */
    295. 

  295. #define _EBI_RDTIMING_PAGEMODE_MASK               0x40000000UL                           /**< Bit mask for EBI_PAGEMODE */
    296. 

  296. #define _EBI_RDTIMING_PAGEMODE_DEFAULT            0x00000000UL                           /**< Mode DEFAULT for EBI_RDTIMING */
    297. 

  297. #define EBI_RDTIMING_PAGEMODE_DEFAULT             (_EBI_RDTIMING_PAGEMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for EBI_RDTIMING */
    298. 

  298. 

  299. /* Bit fields for EBI WRTIMING */
    300. 

  300. #define _EBI_WRTIMING_RESETVALUE                  0x00033F03UL                          /**< Default value for EBI_WRTIMING */
    301. 

  301. #define _EBI_WRTIMING_MASK                        0x30033F03UL                          /**< Mask for EBI_WRTIMING */
    302. 

  302. #define _EBI_WRTIMING_WRSETUP_SHIFT               0                                     /**< Shift value for EBI_WRSETUP */
    303. 

  303. #define _EBI_WRTIMING_WRSETUP_MASK                0x3UL                                 /**< Bit mask for EBI_WRSETUP */
    304. 

  304. #define _EBI_WRTIMING_WRSETUP_DEFAULT             0x00000003UL                          /**< Mode DEFAULT for EBI_WRTIMING */
    305. 

  305. #define EBI_WRTIMING_WRSETUP_DEFAULT              (_EBI_WRTIMING_WRSETUP_DEFAULT << 0)  /**< Shifted mode DEFAULT for EBI_WRTIMING */
    306. 

  306. #define _EBI_WRTIMING_WRSTRB_SHIFT                8                                     /**< Shift value for EBI_WRSTRB */
    307. 

  307. #define _EBI_WRTIMING_WRSTRB_MASK                 0x3F00UL                              /**< Bit mask for EBI_WRSTRB */
    308. 

  308. #define _EBI_WRTIMING_WRSTRB_DEFAULT              0x0000003FUL                          /**< Mode DEFAULT for EBI_WRTIMING */
    309. 

  309. #define EBI_WRTIMING_WRSTRB_DEFAULT               (_EBI_WRTIMING_WRSTRB_DEFAULT << 8)   /**< Shifted mode DEFAULT for EBI_WRTIMING */
    310. 

  310. #define _EBI_WRTIMING_WRHOLD_SHIFT                16                                    /**< Shift value for EBI_WRHOLD */
    311. 

  311. #define _EBI_WRTIMING_WRHOLD_MASK                 0x30000UL                             /**< Bit mask for EBI_WRHOLD */
    312. 

  312. #define _EBI_WRTIMING_WRHOLD_DEFAULT              0x00000003UL                          /**< Mode DEFAULT for EBI_WRTIMING */
    313. 

  313. #define EBI_WRTIMING_WRHOLD_DEFAULT               (_EBI_WRTIMING_WRHOLD_DEFAULT << 16)  /**< Shifted mode DEFAULT for EBI_WRTIMING */
    314. 

  314. #define EBI_WRTIMING_HALFWE                       (0x1UL << 28)                         /**< Half Cycle WEn Strobe Duration Enable */
    315. 

  315. #define _EBI_WRTIMING_HALFWE_SHIFT                28                                    /**< Shift value for EBI_HALFWE */
    316. 

  316. #define _EBI_WRTIMING_HALFWE_MASK                 0x10000000UL                          /**< Bit mask for EBI_HALFWE */
    317. 

  317. #define _EBI_WRTIMING_HALFWE_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for EBI_WRTIMING */
    318. 

  318. #define EBI_WRTIMING_HALFWE_DEFAULT               (_EBI_WRTIMING_HALFWE_DEFAULT << 28)  /**< Shifted mode DEFAULT for EBI_WRTIMING */
    319. 

  319. #define EBI_WRTIMING_WBUFDIS                      (0x1UL << 29)                         /**< Write Buffer Disable */
    320. 

  320. #define _EBI_WRTIMING_WBUFDIS_SHIFT               29                                    /**< Shift value for EBI_WBUFDIS */
    321. 

  321. #define _EBI_WRTIMING_WBUFDIS_MASK                0x20000000UL                          /**< Bit mask for EBI_WBUFDIS */
    322. 

  322. #define _EBI_WRTIMING_WBUFDIS_DEFAULT             0x00000000UL                          /**< Mode DEFAULT for EBI_WRTIMING */
    323. 

  323. #define EBI_WRTIMING_WBUFDIS_DEFAULT              (_EBI_WRTIMING_WBUFDIS_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_WRTIMING */
    324. 

  324. 

  325. /* Bit fields for EBI POLARITY */
    326. 

  326. #define _EBI_POLARITY_RESETVALUE                  0x00000000UL                            /**< Default value for EBI_POLARITY */
    327. 

  327. #define _EBI_POLARITY_MASK                        0x0000003FUL                            /**< Mask for EBI_POLARITY */
    328. 

  328. #define EBI_POLARITY_CSPOL                        (0x1UL << 0)                            /**< Chip Select Polarity */
    329. 

  329. #define _EBI_POLARITY_CSPOL_SHIFT                 0                                       /**< Shift value for EBI_CSPOL */
    330. 

  330. #define _EBI_POLARITY_CSPOL_MASK                  0x1UL                                   /**< Bit mask for EBI_CSPOL */
    331. 

  331. #define _EBI_POLARITY_CSPOL_DEFAULT               0x00000000UL                            /**< Mode DEFAULT for EBI_POLARITY */
    332. 

  332. #define _EBI_POLARITY_CSPOL_ACTIVELOW             0x00000000UL                            /**< Mode ACTIVELOW for EBI_POLARITY */
    333. 

  333. #define _EBI_POLARITY_CSPOL_ACTIVEHIGH            0x00000001UL                            /**< Mode ACTIVEHIGH for EBI_POLARITY */
    334. 

  334. #define EBI_POLARITY_CSPOL_DEFAULT                (_EBI_POLARITY_CSPOL_DEFAULT << 0)      /**< Shifted mode DEFAULT for EBI_POLARITY */
    335. 

  335. #define EBI_POLARITY_CSPOL_ACTIVELOW              (_EBI_POLARITY_CSPOL_ACTIVELOW << 0)    /**< Shifted mode ACTIVELOW for EBI_POLARITY */
    336. 

  336. #define EBI_POLARITY_CSPOL_ACTIVEHIGH             (_EBI_POLARITY_CSPOL_ACTIVEHIGH << 0)   /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */
    337. 

  337. #define EBI_POLARITY_REPOL                        (0x1UL << 1)                            /**< Read Enable Polarity */
    338. 

  338. #define _EBI_POLARITY_REPOL_SHIFT                 1                                       /**< Shift value for EBI_REPOL */
    339. 

  339. #define _EBI_POLARITY_REPOL_MASK                  0x2UL                                   /**< Bit mask for EBI_REPOL */
    340. 

  340. #define _EBI_POLARITY_REPOL_DEFAULT               0x00000000UL                            /**< Mode DEFAULT for EBI_POLARITY */
    341. 

  341. #define _EBI_POLARITY_REPOL_ACTIVELOW             0x00000000UL                            /**< Mode ACTIVELOW for EBI_POLARITY */
    342. 

  342. #define _EBI_POLARITY_REPOL_ACTIVEHIGH            0x00000001UL                            /**< Mode ACTIVEHIGH for EBI_POLARITY */
    343. 

  343. #define EBI_POLARITY_REPOL_DEFAULT                (_EBI_POLARITY_REPOL_DEFAULT << 1)      /**< Shifted mode DEFAULT for EBI_POLARITY */
    344. 

  344. #define EBI_POLARITY_REPOL_ACTIVELOW              (_EBI_POLARITY_REPOL_ACTIVELOW << 1)    /**< Shifted mode ACTIVELOW for EBI_POLARITY */
    345. 

  345. #define EBI_POLARITY_REPOL_ACTIVEHIGH             (_EBI_POLARITY_REPOL_ACTIVEHIGH << 1)   /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */
    346. 

  346. #define EBI_POLARITY_WEPOL                        (0x1UL << 2)                            /**< Write Enable Polarity */
    347. 

  347. #define _EBI_POLARITY_WEPOL_SHIFT                 2                                       /**< Shift value for EBI_WEPOL */
    348. 

  348. #define _EBI_POLARITY_WEPOL_MASK                  0x4UL                                   /**< Bit mask for EBI_WEPOL */
    349. 

  349. #define _EBI_POLARITY_WEPOL_DEFAULT               0x00000000UL                            /**< Mode DEFAULT for EBI_POLARITY */
    350. 

  350. #define _EBI_POLARITY_WEPOL_ACTIVELOW             0x00000000UL                            /**< Mode ACTIVELOW for EBI_POLARITY */
    351. 

  351. #define _EBI_POLARITY_WEPOL_ACTIVEHIGH            0x00000001UL                            /**< Mode ACTIVEHIGH for EBI_POLARITY */
    352. 

  352. #define EBI_POLARITY_WEPOL_DEFAULT                (_EBI_POLARITY_WEPOL_DEFAULT << 2)      /**< Shifted mode DEFAULT for EBI_POLARITY */
    353. 

  353. #define EBI_POLARITY_WEPOL_ACTIVELOW              (_EBI_POLARITY_WEPOL_ACTIVELOW << 2)    /**< Shifted mode ACTIVELOW for EBI_POLARITY */
    354. 

  354. #define EBI_POLARITY_WEPOL_ACTIVEHIGH             (_EBI_POLARITY_WEPOL_ACTIVEHIGH << 2)   /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */
    355. 

  355. #define EBI_POLARITY_ALEPOL                       (0x1UL << 3)                            /**< Address Latch Polarity */
    356. 

  356. #define _EBI_POLARITY_ALEPOL_SHIFT                3                                       /**< Shift value for EBI_ALEPOL */
    357. 

  357. #define _EBI_POLARITY_ALEPOL_MASK                 0x8UL                                   /**< Bit mask for EBI_ALEPOL */
    358. 

  358. #define _EBI_POLARITY_ALEPOL_DEFAULT              0x00000000UL                            /**< Mode DEFAULT for EBI_POLARITY */
    359. 

  359. #define _EBI_POLARITY_ALEPOL_ACTIVELOW            0x00000000UL                            /**< Mode ACTIVELOW for EBI_POLARITY */
    360. 

  360. #define _EBI_POLARITY_ALEPOL_ACTIVEHIGH           0x00000001UL                            /**< Mode ACTIVEHIGH for EBI_POLARITY */
    361. 

  361. #define EBI_POLARITY_ALEPOL_DEFAULT               (_EBI_POLARITY_ALEPOL_DEFAULT << 3)     /**< Shifted mode DEFAULT for EBI_POLARITY */
    362. 

  362. #define EBI_POLARITY_ALEPOL_ACTIVELOW             (_EBI_POLARITY_ALEPOL_ACTIVELOW << 3)   /**< Shifted mode ACTIVELOW for EBI_POLARITY */
    363. 

  363. #define EBI_POLARITY_ALEPOL_ACTIVEHIGH            (_EBI_POLARITY_ALEPOL_ACTIVEHIGH << 3)  /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */
    364. 

  364. #define EBI_POLARITY_ARDYPOL                      (0x1UL << 4)                            /**< ARDY Polarity */
    365. 

  365. #define _EBI_POLARITY_ARDYPOL_SHIFT               4                                       /**< Shift value for EBI_ARDYPOL */
    366. 

  366. #define _EBI_POLARITY_ARDYPOL_MASK                0x10UL                                  /**< Bit mask for EBI_ARDYPOL */
    367. 

  367. #define _EBI_POLARITY_ARDYPOL_DEFAULT             0x00000000UL                            /**< Mode DEFAULT for EBI_POLARITY */
    368. 

  368. #define _EBI_POLARITY_ARDYPOL_ACTIVELOW           0x00000000UL                            /**< Mode ACTIVELOW for EBI_POLARITY */
    369. 

  369. #define _EBI_POLARITY_ARDYPOL_ACTIVEHIGH          0x00000001UL                            /**< Mode ACTIVEHIGH for EBI_POLARITY */
    370. 

  370. #define EBI_POLARITY_ARDYPOL_DEFAULT              (_EBI_POLARITY_ARDYPOL_DEFAULT << 4)    /**< Shifted mode DEFAULT for EBI_POLARITY */
    371. 

  371. #define EBI_POLARITY_ARDYPOL_ACTIVELOW            (_EBI_POLARITY_ARDYPOL_ACTIVELOW << 4)  /**< Shifted mode ACTIVELOW for EBI_POLARITY */
    372. 

  372. #define EBI_POLARITY_ARDYPOL_ACTIVEHIGH           (_EBI_POLARITY_ARDYPOL_ACTIVEHIGH << 4) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */
    373. 

  373. #define EBI_POLARITY_BLPOL                        (0x1UL << 5)                            /**< BL Polarity */
    374. 

  374. #define _EBI_POLARITY_BLPOL_SHIFT                 5                                       /**< Shift value for EBI_BLPOL */
    375. 

  375. #define _EBI_POLARITY_BLPOL_MASK                  0x20UL                                  /**< Bit mask for EBI_BLPOL */
    376. 

  376. #define _EBI_POLARITY_BLPOL_DEFAULT               0x00000000UL                            /**< Mode DEFAULT for EBI_POLARITY */
    377. 

  377. #define _EBI_POLARITY_BLPOL_ACTIVELOW             0x00000000UL                            /**< Mode ACTIVELOW for EBI_POLARITY */
    378. 

  378. #define _EBI_POLARITY_BLPOL_ACTIVEHIGH            0x00000001UL                            /**< Mode ACTIVEHIGH for EBI_POLARITY */
    379. 

  379. #define EBI_POLARITY_BLPOL_DEFAULT                (_EBI_POLARITY_BLPOL_DEFAULT << 5)      /**< Shifted mode DEFAULT for EBI_POLARITY */
    380. 

  380. #define EBI_POLARITY_BLPOL_ACTIVELOW              (_EBI_POLARITY_BLPOL_ACTIVELOW << 5)    /**< Shifted mode ACTIVELOW for EBI_POLARITY */
    381. 

  381. #define EBI_POLARITY_BLPOL_ACTIVEHIGH             (_EBI_POLARITY_BLPOL_ACTIVEHIGH << 5)   /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */
    382. 

  382. 

  383. /* Bit fields for EBI ROUTE */
    384. 

  384. #define _EBI_ROUTE_RESETVALUE                     0x00000000UL                         /**< Default value for EBI_ROUTE */
    385. 

  385. #define _EBI_ROUTE_MASK                           0x777F10FFUL                         /**< Mask for EBI_ROUTE */
    386. 

  386. #define EBI_ROUTE_EBIPEN                          (0x1UL << 0)                         /**< EBI Pin Enable */
    387. 

  387. #define _EBI_ROUTE_EBIPEN_SHIFT                   0                                    /**< Shift value for EBI_EBIPEN */
    388. 

  388. #define _EBI_ROUTE_EBIPEN_MASK                    0x1UL                                /**< Bit mask for EBI_EBIPEN */
    389. 

  389. #define _EBI_ROUTE_EBIPEN_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for EBI_ROUTE */
    390. 

  390. #define EBI_ROUTE_EBIPEN_DEFAULT                  (_EBI_ROUTE_EBIPEN_DEFAULT << 0)     /**< Shifted mode DEFAULT for EBI_ROUTE */
    391. 

  391. #define EBI_ROUTE_CS0PEN                          (0x1UL << 1)                         /**< EBI_CS0 Pin Enable */
    392. 

  392. #define _EBI_ROUTE_CS0PEN_SHIFT                   1                                    /**< Shift value for EBI_CS0PEN */
    393. 

  393. #define _EBI_ROUTE_CS0PEN_MASK                    0x2UL                                /**< Bit mask for EBI_CS0PEN */
    394. 

  394. #define _EBI_ROUTE_CS0PEN_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for EBI_ROUTE */
    395. 

  395. #define EBI_ROUTE_CS0PEN_DEFAULT                  (_EBI_ROUTE_CS0PEN_DEFAULT << 1)     /**< Shifted mode DEFAULT for EBI_ROUTE */
    396. 

  396. #define EBI_ROUTE_CS1PEN                          (0x1UL << 2)                         /**< EBI_CS1 Pin Enable */
    397. 

  397. #define _EBI_ROUTE_CS1PEN_SHIFT                   2                                    /**< Shift value for EBI_CS1PEN */
    398. 

  398. #define _EBI_ROUTE_CS1PEN_MASK                    0x4UL                                /**< Bit mask for EBI_CS1PEN */
    399. 

  399. #define _EBI_ROUTE_CS1PEN_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for EBI_ROUTE */
    400. 

  400. #define EBI_ROUTE_CS1PEN_DEFAULT                  (_EBI_ROUTE_CS1PEN_DEFAULT << 2)     /**< Shifted mode DEFAULT for EBI_ROUTE */
    401. 

  401. #define EBI_ROUTE_CS2PEN                          (0x1UL << 3)                         /**< EBI_CS2 Pin Enable */
    402. 

  402. #define _EBI_ROUTE_CS2PEN_SHIFT                   3                                    /**< Shift value for EBI_CS2PEN */
    403. 

  403. #define _EBI_ROUTE_CS2PEN_MASK                    0x8UL                                /**< Bit mask for EBI_CS2PEN */
    404. 

  404. #define _EBI_ROUTE_CS2PEN_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for EBI_ROUTE */
    405. 

  405. #define EBI_ROUTE_CS2PEN_DEFAULT                  (_EBI_ROUTE_CS2PEN_DEFAULT << 3)     /**< Shifted mode DEFAULT for EBI_ROUTE */
    406. 

  406. #define EBI_ROUTE_CS3PEN                          (0x1UL << 4)                         /**< EBI_CS3 Pin Enable */
    407. 

  407. #define _EBI_ROUTE_CS3PEN_SHIFT                   4                                    /**< Shift value for EBI_CS3PEN */
    408. 

  408. #define _EBI_ROUTE_CS3PEN_MASK                    0x10UL                               /**< Bit mask for EBI_CS3PEN */
    409. 

  409. #define _EBI_ROUTE_CS3PEN_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for EBI_ROUTE */
    410. 

  410. #define EBI_ROUTE_CS3PEN_DEFAULT                  (_EBI_ROUTE_CS3PEN_DEFAULT << 4)     /**< Shifted mode DEFAULT for EBI_ROUTE */
    411. 

  411. #define EBI_ROUTE_ALEPEN                          (0x1UL << 5)                         /**< EBI_ALE Pin Enable */
    412. 

  412. #define _EBI_ROUTE_ALEPEN_SHIFT                   5                                    /**< Shift value for EBI_ALEPEN */
    413. 

  413. #define _EBI_ROUTE_ALEPEN_MASK                    0x20UL                               /**< Bit mask for EBI_ALEPEN */
    414. 

  414. #define _EBI_ROUTE_ALEPEN_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for EBI_ROUTE */
    415. 

  415. #define EBI_ROUTE_ALEPEN_DEFAULT                  (_EBI_ROUTE_ALEPEN_DEFAULT << 5)     /**< Shifted mode DEFAULT for EBI_ROUTE */
    416. 

  416. #define EBI_ROUTE_ARDYPEN                         (0x1UL << 6)                         /**< EBI_ARDY Pin Enable */
    417. 

  417. #define _EBI_ROUTE_ARDYPEN_SHIFT                  6                                    /**< Shift value for EBI_ARDYPEN */
    418. 

  418. #define _EBI_ROUTE_ARDYPEN_MASK                   0x40UL                               /**< Bit mask for EBI_ARDYPEN */
    419. 

  419. #define _EBI_ROUTE_ARDYPEN_DEFAULT                0x00000000UL                         /**< Mode DEFAULT for EBI_ROUTE */
    420. 

  420. #define EBI_ROUTE_ARDYPEN_DEFAULT                 (_EBI_ROUTE_ARDYPEN_DEFAULT << 6)    /**< Shifted mode DEFAULT for EBI_ROUTE */
    421. 

  421. #define EBI_ROUTE_BLPEN                           (0x1UL << 7)                         /**< EBI_BL[1:0] Pin Enable */
    422. 

  422. #define _EBI_ROUTE_BLPEN_SHIFT                    7                                    /**< Shift value for EBI_BLPEN */
    423. 

  423. #define _EBI_ROUTE_BLPEN_MASK                     0x80UL                               /**< Bit mask for EBI_BLPEN */
    424. 

  424. #define _EBI_ROUTE_BLPEN_DEFAULT                  0x00000000UL                         /**< Mode DEFAULT for EBI_ROUTE */
    425. 

  425. #define EBI_ROUTE_BLPEN_DEFAULT                   (_EBI_ROUTE_BLPEN_DEFAULT << 7)      /**< Shifted mode DEFAULT for EBI_ROUTE */
    426. 

  426. #define EBI_ROUTE_NANDPEN                         (0x1UL << 12)                        /**< NANDRE and NANDWE Pin Enable */
    427. 

  427. #define _EBI_ROUTE_NANDPEN_SHIFT                  12                                   /**< Shift value for EBI_NANDPEN */
    428. 

  428. #define _EBI_ROUTE_NANDPEN_MASK                   0x1000UL                             /**< Bit mask for EBI_NANDPEN */
    429. 

  429. #define _EBI_ROUTE_NANDPEN_DEFAULT                0x00000000UL                         /**< Mode DEFAULT for EBI_ROUTE */
    430. 

  430. #define EBI_ROUTE_NANDPEN_DEFAULT                 (_EBI_ROUTE_NANDPEN_DEFAULT << 12)   /**< Shifted mode DEFAULT for EBI_ROUTE */
    431. 

  431. #define _EBI_ROUTE_ALB_SHIFT                      16                                   /**< Shift value for EBI_ALB */
    432. 

  432. #define _EBI_ROUTE_ALB_MASK                       0x30000UL                            /**< Bit mask for EBI_ALB */
    433. 

  433. #define _EBI_ROUTE_ALB_DEFAULT                    0x00000000UL                         /**< Mode DEFAULT for EBI_ROUTE */
    434. 

  434. #define _EBI_ROUTE_ALB_A0                         0x00000000UL                         /**< Mode A0 for EBI_ROUTE */
    435. 

  435. #define _EBI_ROUTE_ALB_A8                         0x00000001UL                         /**< Mode A8 for EBI_ROUTE */
    436. 

  436. #define _EBI_ROUTE_ALB_A16                        0x00000002UL                         /**< Mode A16 for EBI_ROUTE */
    437. 

  437. #define _EBI_ROUTE_ALB_A24                        0x00000003UL                         /**< Mode A24 for EBI_ROUTE */
    438. 

  438. #define EBI_ROUTE_ALB_DEFAULT                     (_EBI_ROUTE_ALB_DEFAULT << 16)       /**< Shifted mode DEFAULT for EBI_ROUTE */
    439. 

  439. #define EBI_ROUTE_ALB_A0                          (_EBI_ROUTE_ALB_A0 << 16)            /**< Shifted mode A0 for EBI_ROUTE */
    440. 

  440. #define EBI_ROUTE_ALB_A8                          (_EBI_ROUTE_ALB_A8 << 16)            /**< Shifted mode A8 for EBI_ROUTE */
    441. 

  441. #define EBI_ROUTE_ALB_A16                         (_EBI_ROUTE_ALB_A16 << 16)           /**< Shifted mode A16 for EBI_ROUTE */
    442. 

  442. #define EBI_ROUTE_ALB_A24                         (_EBI_ROUTE_ALB_A24 << 16)           /**< Shifted mode A24 for EBI_ROUTE */
    443. 

  443. #define _EBI_ROUTE_APEN_SHIFT                     18                                   /**< Shift value for EBI_APEN */
    444. 

  444. #define _EBI_ROUTE_APEN_MASK                      0x7C0000UL                           /**< Bit mask for EBI_APEN */
    445. 

  445. #define _EBI_ROUTE_APEN_DEFAULT                   0x00000000UL                         /**< Mode DEFAULT for EBI_ROUTE */
    446. 

  446. #define _EBI_ROUTE_APEN_A0                        0x00000000UL                         /**< Mode A0 for EBI_ROUTE */
    447. 

  447. #define _EBI_ROUTE_APEN_A5                        0x00000005UL                         /**< Mode A5 for EBI_ROUTE */
    448. 

  448. #define _EBI_ROUTE_APEN_A6                        0x00000006UL                         /**< Mode A6 for EBI_ROUTE */
    449. 

  449. #define _EBI_ROUTE_APEN_A7                        0x00000007UL                         /**< Mode A7 for EBI_ROUTE */
    450. 

  450. #define _EBI_ROUTE_APEN_A8                        0x00000008UL                         /**< Mode A8 for EBI_ROUTE */
    451. 

  451. #define _EBI_ROUTE_APEN_A9                        0x00000009UL                         /**< Mode A9 for EBI_ROUTE */
    452. 

  452. #define _EBI_ROUTE_APEN_A10                       0x0000000AUL                         /**< Mode A10 for EBI_ROUTE */
    453. 

  453. #define _EBI_ROUTE_APEN_A11                       0x0000000BUL                         /**< Mode A11 for EBI_ROUTE */
    454. 

  454. #define _EBI_ROUTE_APEN_A12                       0x0000000CUL                         /**< Mode A12 for EBI_ROUTE */
    455. 

  455. #define _EBI_ROUTE_APEN_A13                       0x0000000DUL                         /**< Mode A13 for EBI_ROUTE */
    456. 

  456. #define _EBI_ROUTE_APEN_A14                       0x0000000EUL                         /**< Mode A14 for EBI_ROUTE */
    457. 

  457. #define _EBI_ROUTE_APEN_A15                       0x0000000FUL                         /**< Mode A15 for EBI_ROUTE */
    458. 

  458. #define _EBI_ROUTE_APEN_A16                       0x00000010UL                         /**< Mode A16 for EBI_ROUTE */
    459. 

  459. #define _EBI_ROUTE_APEN_A17                       0x00000011UL                         /**< Mode A17 for EBI_ROUTE */
    460. 

  460. #define _EBI_ROUTE_APEN_A18                       0x00000012UL                         /**< Mode A18 for EBI_ROUTE */
    461. 

  461. #define _EBI_ROUTE_APEN_A19                       0x00000013UL                         /**< Mode A19 for EBI_ROUTE */
    462. 

  462. #define _EBI_ROUTE_APEN_A20                       0x00000014UL                         /**< Mode A20 for EBI_ROUTE */
    463. 

  463. #define _EBI_ROUTE_APEN_A21                       0x00000015UL                         /**< Mode A21 for EBI_ROUTE */
    464. 

  464. #define _EBI_ROUTE_APEN_A22                       0x00000016UL                         /**< Mode A22 for EBI_ROUTE */
    465. 

  465. #define _EBI_ROUTE_APEN_A23                       0x00000017UL                         /**< Mode A23 for EBI_ROUTE */
    466. 

  466. #define _EBI_ROUTE_APEN_A24                       0x00000018UL                         /**< Mode A24 for EBI_ROUTE */
    467. 

  467. #define _EBI_ROUTE_APEN_A25                       0x00000019UL                         /**< Mode A25 for EBI_ROUTE */
    468. 

  468. #define _EBI_ROUTE_APEN_A26                       0x0000001AUL                         /**< Mode A26 for EBI_ROUTE */
    469. 

  469. #define _EBI_ROUTE_APEN_A27                       0x0000001BUL                         /**< Mode A27 for EBI_ROUTE */
    470. 

  470. #define _EBI_ROUTE_APEN_A28                       0x0000001CUL                         /**< Mode A28 for EBI_ROUTE */
    471. 

  471. #define EBI_ROUTE_APEN_DEFAULT                    (_EBI_ROUTE_APEN_DEFAULT << 18)      /**< Shifted mode DEFAULT for EBI_ROUTE */
    472. 

  472. #define EBI_ROUTE_APEN_A0                         (_EBI_ROUTE_APEN_A0 << 18)           /**< Shifted mode A0 for EBI_ROUTE */
    473. 

  473. #define EBI_ROUTE_APEN_A5                         (_EBI_ROUTE_APEN_A5 << 18)           /**< Shifted mode A5 for EBI_ROUTE */
    474. 

  474. #define EBI_ROUTE_APEN_A6                         (_EBI_ROUTE_APEN_A6 << 18)           /**< Shifted mode A6 for EBI_ROUTE */
    475. 

  475. #define EBI_ROUTE_APEN_A7                         (_EBI_ROUTE_APEN_A7 << 18)           /**< Shifted mode A7 for EBI_ROUTE */
    476. 

  476. #define EBI_ROUTE_APEN_A8                         (_EBI_ROUTE_APEN_A8 << 18)           /**< Shifted mode A8 for EBI_ROUTE */
    477. 

  477. #define EBI_ROUTE_APEN_A9                         (_EBI_ROUTE_APEN_A9 << 18)           /**< Shifted mode A9 for EBI_ROUTE */
    478. 

  478. #define EBI_ROUTE_APEN_A10                        (_EBI_ROUTE_APEN_A10 << 18)          /**< Shifted mode A10 for EBI_ROUTE */
    479. 

  479. #define EBI_ROUTE_APEN_A11                        (_EBI_ROUTE_APEN_A11 << 18)          /**< Shifted mode A11 for EBI_ROUTE */
    480. 

  480. #define EBI_ROUTE_APEN_A12                        (_EBI_ROUTE_APEN_A12 << 18)          /**< Shifted mode A12 for EBI_ROUTE */
    481. 

  481. #define EBI_ROUTE_APEN_A13                        (_EBI_ROUTE_APEN_A13 << 18)          /**< Shifted mode A13 for EBI_ROUTE */
    482. 

  482. #define EBI_ROUTE_APEN_A14                        (_EBI_ROUTE_APEN_A14 << 18)          /**< Shifted mode A14 for EBI_ROUTE */
    483. 

  483. #define EBI_ROUTE_APEN_A15                        (_EBI_ROUTE_APEN_A15 << 18)          /**< Shifted mode A15 for EBI_ROUTE */
    484. 

  484. #define EBI_ROUTE_APEN_A16                        (_EBI_ROUTE_APEN_A16 << 18)          /**< Shifted mode A16 for EBI_ROUTE */
    485. 

  485. #define EBI_ROUTE_APEN_A17                        (_EBI_ROUTE_APEN_A17 << 18)          /**< Shifted mode A17 for EBI_ROUTE */
    486. 

  486. #define EBI_ROUTE_APEN_A18                        (_EBI_ROUTE_APEN_A18 << 18)          /**< Shifted mode A18 for EBI_ROUTE */
    487. 

  487. #define EBI_ROUTE_APEN_A19                        (_EBI_ROUTE_APEN_A19 << 18)          /**< Shifted mode A19 for EBI_ROUTE */
    488. 

  488. #define EBI_ROUTE_APEN_A20                        (_EBI_ROUTE_APEN_A20 << 18)          /**< Shifted mode A20 for EBI_ROUTE */
    489. 

  489. #define EBI_ROUTE_APEN_A21                        (_EBI_ROUTE_APEN_A21 << 18)          /**< Shifted mode A21 for EBI_ROUTE */
    490. 

  490. #define EBI_ROUTE_APEN_A22                        (_EBI_ROUTE_APEN_A22 << 18)          /**< Shifted mode A22 for EBI_ROUTE */
    491. 

  491. #define EBI_ROUTE_APEN_A23                        (_EBI_ROUTE_APEN_A23 << 18)          /**< Shifted mode A23 for EBI_ROUTE */
    492. 

  492. #define EBI_ROUTE_APEN_A24                        (_EBI_ROUTE_APEN_A24 << 18)          /**< Shifted mode A24 for EBI_ROUTE */
    493. 

  493. #define EBI_ROUTE_APEN_A25                        (_EBI_ROUTE_APEN_A25 << 18)          /**< Shifted mode A25 for EBI_ROUTE */
    494. 

  494. #define EBI_ROUTE_APEN_A26                        (_EBI_ROUTE_APEN_A26 << 18)          /**< Shifted mode A26 for EBI_ROUTE */
    495. 

  495. #define EBI_ROUTE_APEN_A27                        (_EBI_ROUTE_APEN_A27 << 18)          /**< Shifted mode A27 for EBI_ROUTE */
    496. 

  496. #define EBI_ROUTE_APEN_A28                        (_EBI_ROUTE_APEN_A28 << 18)          /**< Shifted mode A28 for EBI_ROUTE */
    497. 

  497. #define EBI_ROUTE_TFTPEN                          (0x1UL << 24)                        /**< EBI_TFT Pin Enable */
    498. 

  498. #define _EBI_ROUTE_TFTPEN_SHIFT                   24                                   /**< Shift value for EBI_TFTPEN */
    499. 

  499. #define _EBI_ROUTE_TFTPEN_MASK                    0x1000000UL                          /**< Bit mask for EBI_TFTPEN */
    500. 

  500. #define _EBI_ROUTE_TFTPEN_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for EBI_ROUTE */
    501. 

  501. #define EBI_ROUTE_TFTPEN_DEFAULT                  (_EBI_ROUTE_TFTPEN_DEFAULT << 24)    /**< Shifted mode DEFAULT for EBI_ROUTE */
    502. 

  502. #define EBI_ROUTE_DATAENPEN                       (0x1UL << 25)                        /**< EBI_TFT Pin Enable */
    503. 

  503. #define _EBI_ROUTE_DATAENPEN_SHIFT                25                                   /**< Shift value for EBI_DATAENPEN */
    504. 

  504. #define _EBI_ROUTE_DATAENPEN_MASK                 0x2000000UL                          /**< Bit mask for EBI_DATAENPEN */
    505. 

  505. #define _EBI_ROUTE_DATAENPEN_DEFAULT              0x00000000UL                         /**< Mode DEFAULT for EBI_ROUTE */
    506. 

  506. #define EBI_ROUTE_DATAENPEN_DEFAULT               (_EBI_ROUTE_DATAENPEN_DEFAULT << 25) /**< Shifted mode DEFAULT for EBI_ROUTE */
    507. 

  507. #define EBI_ROUTE_CSTFTPEN                        (0x1UL << 26)                        /**< EBI_CSTFT Pin Enable */
    508. 

  508. #define _EBI_ROUTE_CSTFTPEN_SHIFT                 26                                   /**< Shift value for EBI_CSTFTPEN */
    509. 

  509. #define _EBI_ROUTE_CSTFTPEN_MASK                  0x4000000UL                          /**< Bit mask for EBI_CSTFTPEN */
    510. 

  510. #define _EBI_ROUTE_CSTFTPEN_DEFAULT               0x00000000UL                         /**< Mode DEFAULT for EBI_ROUTE */
    511. 

  511. #define EBI_ROUTE_CSTFTPEN_DEFAULT                (_EBI_ROUTE_CSTFTPEN_DEFAULT << 26)  /**< Shifted mode DEFAULT for EBI_ROUTE */
    512. 

  512. #define _EBI_ROUTE_LOCATION_SHIFT                 28                                   /**< Shift value for EBI_LOCATION */
    513. 

  513. #define _EBI_ROUTE_LOCATION_MASK                  0x70000000UL                         /**< Bit mask for EBI_LOCATION */
    514. 

  514. #define _EBI_ROUTE_LOCATION_LOC0                  0x00000000UL                         /**< Mode LOC0 for EBI_ROUTE */
    515. 

  515. #define _EBI_ROUTE_LOCATION_LOC1                  0x00000001UL                         /**< Mode LOC1 for EBI_ROUTE */
    516. 

  516. #define _EBI_ROUTE_LOCATION_LOC2                  0x00000002UL                         /**< Mode LOC2 for EBI_ROUTE */
    517. 

  517. #define EBI_ROUTE_LOCATION_LOC0                   (_EBI_ROUTE_LOCATION_LOC0 << 28)     /**< Shifted mode LOC0 for EBI_ROUTE */
    518. 

  518. #define EBI_ROUTE_LOCATION_LOC1                   (_EBI_ROUTE_LOCATION_LOC1 << 28)     /**< Shifted mode LOC1 for EBI_ROUTE */
    519. 

  519. #define EBI_ROUTE_LOCATION_LOC2                   (_EBI_ROUTE_LOCATION_LOC2 << 28)     /**< Shifted mode LOC2 for EBI_ROUTE */
    520. 

  520. 

  521. /* Bit fields for EBI ADDRTIMING1 */
    522. 

  522. #define _EBI_ADDRTIMING1_RESETVALUE               0x00000303UL                              /**< Default value for EBI_ADDRTIMING1 */
    523. 

  523. #define _EBI_ADDRTIMING1_MASK                     0x10000303UL                              /**< Mask for EBI_ADDRTIMING1 */
    524. 

  524. #define _EBI_ADDRTIMING1_ADDRSETUP_SHIFT          0                                         /**< Shift value for EBI_ADDRSETUP */
    525. 

  525. #define _EBI_ADDRTIMING1_ADDRSETUP_MASK           0x3UL                                     /**< Bit mask for EBI_ADDRSETUP */
    526. 

  526. #define _EBI_ADDRTIMING1_ADDRSETUP_DEFAULT        0x00000003UL                              /**< Mode DEFAULT for EBI_ADDRTIMING1 */
    527. 

  527. #define EBI_ADDRTIMING1_ADDRSETUP_DEFAULT         (_EBI_ADDRTIMING1_ADDRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ADDRTIMING1 */
    528. 

  528. #define _EBI_ADDRTIMING1_ADDRHOLD_SHIFT           8                                         /**< Shift value for EBI_ADDRHOLD */
    529. 

  529. #define _EBI_ADDRTIMING1_ADDRHOLD_MASK            0x300UL                                   /**< Bit mask for EBI_ADDRHOLD */
    530. 

  530. #define _EBI_ADDRTIMING1_ADDRHOLD_DEFAULT         0x00000003UL                              /**< Mode DEFAULT for EBI_ADDRTIMING1 */
    531. 

  531. #define EBI_ADDRTIMING1_ADDRHOLD_DEFAULT          (_EBI_ADDRTIMING1_ADDRHOLD_DEFAULT << 8)  /**< Shifted mode DEFAULT for EBI_ADDRTIMING1 */
    532. 

  532. #define EBI_ADDRTIMING1_HALFALE                   (0x1UL << 28)                             /**< Half Cycle ALE Strobe Duration Enable */
    533. 

  533. #define _EBI_ADDRTIMING1_HALFALE_SHIFT            28                                        /**< Shift value for EBI_HALFALE */
    534. 

  534. #define _EBI_ADDRTIMING1_HALFALE_MASK             0x10000000UL                              /**< Bit mask for EBI_HALFALE */
    535. 

  535. #define _EBI_ADDRTIMING1_HALFALE_DEFAULT          0x00000000UL                              /**< Mode DEFAULT for EBI_ADDRTIMING1 */
    536. 

  536. #define EBI_ADDRTIMING1_HALFALE_DEFAULT           (_EBI_ADDRTIMING1_HALFALE_DEFAULT << 28)  /**< Shifted mode DEFAULT for EBI_ADDRTIMING1 */
    537. 

  537. 

  538. /* Bit fields for EBI RDTIMING1 */
    539. 

  539. #define _EBI_RDTIMING1_RESETVALUE                 0x00033F03UL                            /**< Default value for EBI_RDTIMING1 */
    540. 

  540. #define _EBI_RDTIMING1_MASK                       0x70033F03UL                            /**< Mask for EBI_RDTIMING1 */
    541. 

  541. #define _EBI_RDTIMING1_RDSETUP_SHIFT              0                                       /**< Shift value for EBI_RDSETUP */
    542. 

  542. #define _EBI_RDTIMING1_RDSETUP_MASK               0x3UL                                   /**< Bit mask for EBI_RDSETUP */
    543. 

  543. #define _EBI_RDTIMING1_RDSETUP_DEFAULT            0x00000003UL                            /**< Mode DEFAULT for EBI_RDTIMING1 */
    544. 

  544. #define EBI_RDTIMING1_RDSETUP_DEFAULT             (_EBI_RDTIMING1_RDSETUP_DEFAULT << 0)   /**< Shifted mode DEFAULT for EBI_RDTIMING1 */
    545. 

  545. #define _EBI_RDTIMING1_RDSTRB_SHIFT               8                                       /**< Shift value for EBI_RDSTRB */
    546. 

  546. #define _EBI_RDTIMING1_RDSTRB_MASK                0x3F00UL                                /**< Bit mask for EBI_RDSTRB */
    547. 

  547. #define _EBI_RDTIMING1_RDSTRB_DEFAULT             0x0000003FUL                            /**< Mode DEFAULT for EBI_RDTIMING1 */
    548. 

  548. #define EBI_RDTIMING1_RDSTRB_DEFAULT              (_EBI_RDTIMING1_RDSTRB_DEFAULT << 8)    /**< Shifted mode DEFAULT for EBI_RDTIMING1 */
    549. 

  549. #define _EBI_RDTIMING1_RDHOLD_SHIFT               16                                      /**< Shift value for EBI_RDHOLD */
    550. 

  550. #define _EBI_RDTIMING1_RDHOLD_MASK                0x30000UL                               /**< Bit mask for EBI_RDHOLD */
    551. 

  551. #define _EBI_RDTIMING1_RDHOLD_DEFAULT             0x00000003UL                            /**< Mode DEFAULT for EBI_RDTIMING1 */
    552. 

  552. #define EBI_RDTIMING1_RDHOLD_DEFAULT              (_EBI_RDTIMING1_RDHOLD_DEFAULT << 16)   /**< Shifted mode DEFAULT for EBI_RDTIMING1 */
    553. 

  553. #define EBI_RDTIMING1_HALFRE                      (0x1UL << 28)                           /**< Half Cycle REn Strobe Duration Enable */
    554. 

  554. #define _EBI_RDTIMING1_HALFRE_SHIFT               28                                      /**< Shift value for EBI_HALFRE */
    555. 

  555. #define _EBI_RDTIMING1_HALFRE_MASK                0x10000000UL                            /**< Bit mask for EBI_HALFRE */
    556. 

  556. #define _EBI_RDTIMING1_HALFRE_DEFAULT             0x00000000UL                            /**< Mode DEFAULT for EBI_RDTIMING1 */
    557. 

  557. #define EBI_RDTIMING1_HALFRE_DEFAULT              (_EBI_RDTIMING1_HALFRE_DEFAULT << 28)   /**< Shifted mode DEFAULT for EBI_RDTIMING1 */
    558. 

  558. #define EBI_RDTIMING1_PREFETCH                    (0x1UL << 29)                           /**< Prefetch Enable */
    559. 

  559. #define _EBI_RDTIMING1_PREFETCH_SHIFT             29                                      /**< Shift value for EBI_PREFETCH */
    560. 

  560. #define _EBI_RDTIMING1_PREFETCH_MASK              0x20000000UL                            /**< Bit mask for EBI_PREFETCH */
    561. 

  561. #define _EBI_RDTIMING1_PREFETCH_DEFAULT           0x00000000UL                            /**< Mode DEFAULT for EBI_RDTIMING1 */
    562. 

  562. #define EBI_RDTIMING1_PREFETCH_DEFAULT            (_EBI_RDTIMING1_PREFETCH_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_RDTIMING1 */
    563. 

  563. #define EBI_RDTIMING1_PAGEMODE                    (0x1UL << 30)                           /**< Page Mode Access Enable */
    564. 

  564. #define _EBI_RDTIMING1_PAGEMODE_SHIFT             30                                      /**< Shift value for EBI_PAGEMODE */
    565. 

  565. #define _EBI_RDTIMING1_PAGEMODE_MASK              0x40000000UL                            /**< Bit mask for EBI_PAGEMODE */
    566. 

  566. #define _EBI_RDTIMING1_PAGEMODE_DEFAULT           0x00000000UL                            /**< Mode DEFAULT for EBI_RDTIMING1 */
    567. 

  567. #define EBI_RDTIMING1_PAGEMODE_DEFAULT            (_EBI_RDTIMING1_PAGEMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for EBI_RDTIMING1 */
    568. 

  568. 

  569. /* Bit fields for EBI WRTIMING1 */
    570. 

  570. #define _EBI_WRTIMING1_RESETVALUE                 0x00033F03UL                           /**< Default value for EBI_WRTIMING1 */
    571. 

  571. #define _EBI_WRTIMING1_MASK                       0x30033F03UL                           /**< Mask for EBI_WRTIMING1 */
    572. 

  572. #define _EBI_WRTIMING1_WRSETUP_SHIFT              0                                      /**< Shift value for EBI_WRSETUP */
    573. 

  573. #define _EBI_WRTIMING1_WRSETUP_MASK               0x3UL                                  /**< Bit mask for EBI_WRSETUP */
    574. 

  574. #define _EBI_WRTIMING1_WRSETUP_DEFAULT            0x00000003UL                           /**< Mode DEFAULT for EBI_WRTIMING1 */
    575. 

  575. #define EBI_WRTIMING1_WRSETUP_DEFAULT             (_EBI_WRTIMING1_WRSETUP_DEFAULT << 0)  /**< Shifted mode DEFAULT for EBI_WRTIMING1 */
    576. 

  576. #define _EBI_WRTIMING1_WRSTRB_SHIFT               8                                      /**< Shift value for EBI_WRSTRB */
    577. 

  577. #define _EBI_WRTIMING1_WRSTRB_MASK                0x3F00UL                               /**< Bit mask for EBI_WRSTRB */
    578. 

  578. #define _EBI_WRTIMING1_WRSTRB_DEFAULT             0x0000003FUL                           /**< Mode DEFAULT for EBI_WRTIMING1 */
    579. 

  579. #define EBI_WRTIMING1_WRSTRB_DEFAULT              (_EBI_WRTIMING1_WRSTRB_DEFAULT << 8)   /**< Shifted mode DEFAULT for EBI_WRTIMING1 */
    580. 

  580. #define _EBI_WRTIMING1_WRHOLD_SHIFT               16                                     /**< Shift value for EBI_WRHOLD */
    581. 

  581. #define _EBI_WRTIMING1_WRHOLD_MASK                0x30000UL                              /**< Bit mask for EBI_WRHOLD */
    582. 

  582. #define _EBI_WRTIMING1_WRHOLD_DEFAULT             0x00000003UL                           /**< Mode DEFAULT for EBI_WRTIMING1 */
    583. 

  583. #define EBI_WRTIMING1_WRHOLD_DEFAULT              (_EBI_WRTIMING1_WRHOLD_DEFAULT << 16)  /**< Shifted mode DEFAULT for EBI_WRTIMING1 */
    584. 

  584. #define EBI_WRTIMING1_HALFWE                      (0x1UL << 28)                          /**< Half Cycle WEn Strobe Duration Enable */
    585. 

  585. #define _EBI_WRTIMING1_HALFWE_SHIFT               28                                     /**< Shift value for EBI_HALFWE */
    586. 

  586. #define _EBI_WRTIMING1_HALFWE_MASK                0x10000000UL                           /**< Bit mask for EBI_HALFWE */
    587. 

  587. #define _EBI_WRTIMING1_HALFWE_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for EBI_WRTIMING1 */
    588. 

  588. #define EBI_WRTIMING1_HALFWE_DEFAULT              (_EBI_WRTIMING1_HALFWE_DEFAULT << 28)  /**< Shifted mode DEFAULT for EBI_WRTIMING1 */
    589. 

  589. #define EBI_WRTIMING1_WBUFDIS                     (0x1UL << 29)                          /**< Write Buffer Disable */
    590. 

  590. #define _EBI_WRTIMING1_WBUFDIS_SHIFT              29                                     /**< Shift value for EBI_WBUFDIS */
    591. 

  591. #define _EBI_WRTIMING1_WBUFDIS_MASK               0x20000000UL                           /**< Bit mask for EBI_WBUFDIS */
    592. 

  592. #define _EBI_WRTIMING1_WBUFDIS_DEFAULT            0x00000000UL                           /**< Mode DEFAULT for EBI_WRTIMING1 */
    593. 

  593. #define EBI_WRTIMING1_WBUFDIS_DEFAULT             (_EBI_WRTIMING1_WBUFDIS_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_WRTIMING1 */
    594. 

  594. 

  595. /* Bit fields for EBI POLARITY1 */
    596. 

  596. #define _EBI_POLARITY1_RESETVALUE                 0x00000000UL                             /**< Default value for EBI_POLARITY1 */
    597. 

  597. #define _EBI_POLARITY1_MASK                       0x0000003FUL                             /**< Mask for EBI_POLARITY1 */
    598. 

  598. #define EBI_POLARITY1_CSPOL                       (0x1UL << 0)                             /**< Chip Select Polarity */
    599. 

  599. #define _EBI_POLARITY1_CSPOL_SHIFT                0                                        /**< Shift value for EBI_CSPOL */
    600. 

  600. #define _EBI_POLARITY1_CSPOL_MASK                 0x1UL                                    /**< Bit mask for EBI_CSPOL */
    601. 

  601. #define _EBI_POLARITY1_CSPOL_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for EBI_POLARITY1 */
    602. 

  602. #define _EBI_POLARITY1_CSPOL_ACTIVELOW            0x00000000UL                             /**< Mode ACTIVELOW for EBI_POLARITY1 */
    603. 

  603. #define _EBI_POLARITY1_CSPOL_ACTIVEHIGH           0x00000001UL                             /**< Mode ACTIVEHIGH for EBI_POLARITY1 */
    604. 

  604. #define EBI_POLARITY1_CSPOL_DEFAULT               (_EBI_POLARITY1_CSPOL_DEFAULT << 0)      /**< Shifted mode DEFAULT for EBI_POLARITY1 */
    605. 

  605. #define EBI_POLARITY1_CSPOL_ACTIVELOW             (_EBI_POLARITY1_CSPOL_ACTIVELOW << 0)    /**< Shifted mode ACTIVELOW for EBI_POLARITY1 */
    606. 

  606. #define EBI_POLARITY1_CSPOL_ACTIVEHIGH            (_EBI_POLARITY1_CSPOL_ACTIVEHIGH << 0)   /**< Shifted mode ACTIVEHIGH for EBI_POLARITY1 */
    607. 

  607. #define EBI_POLARITY1_REPOL                       (0x1UL << 1)                             /**< Read Enable Polarity */
    608. 

  608. #define _EBI_POLARITY1_REPOL_SHIFT                1                                        /**< Shift value for EBI_REPOL */
    609. 

  609. #define _EBI_POLARITY1_REPOL_MASK                 0x2UL                                    /**< Bit mask for EBI_REPOL */
    610. 

  610. #define _EBI_POLARITY1_REPOL_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for EBI_POLARITY1 */
    611. 

  611. #define _EBI_POLARITY1_REPOL_ACTIVELOW            0x00000000UL                             /**< Mode ACTIVELOW for EBI_POLARITY1 */
    612. 

  612. #define _EBI_POLARITY1_REPOL_ACTIVEHIGH           0x00000001UL                             /**< Mode ACTIVEHIGH for EBI_POLARITY1 */
    613. 

  613. #define EBI_POLARITY1_REPOL_DEFAULT               (_EBI_POLARITY1_REPOL_DEFAULT << 1)      /**< Shifted mode DEFAULT for EBI_POLARITY1 */
    614. 

  614. #define EBI_POLARITY1_REPOL_ACTIVELOW             (_EBI_POLARITY1_REPOL_ACTIVELOW << 1)    /**< Shifted mode ACTIVELOW for EBI_POLARITY1 */
    615. 

  615. #define EBI_POLARITY1_REPOL_ACTIVEHIGH            (_EBI_POLARITY1_REPOL_ACTIVEHIGH << 1)   /**< Shifted mode ACTIVEHIGH for EBI_POLARITY1 */
    616. 

  616. #define EBI_POLARITY1_WEPOL                       (0x1UL << 2)                             /**< Write Enable Polarity */
    617. 

  617. #define _EBI_POLARITY1_WEPOL_SHIFT                2                                        /**< Shift value for EBI_WEPOL */
    618. 

  618. #define _EBI_POLARITY1_WEPOL_MASK                 0x4UL                                    /**< Bit mask for EBI_WEPOL */
    619. 

  619. #define _EBI_POLARITY1_WEPOL_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for EBI_POLARITY1 */
    620. 

  620. #define _EBI_POLARITY1_WEPOL_ACTIVELOW            0x00000000UL                             /**< Mode ACTIVELOW for EBI_POLARITY1 */
    621. 

  621. #define _EBI_POLARITY1_WEPOL_ACTIVEHIGH           0x00000001UL                             /**< Mode ACTIVEHIGH for EBI_POLARITY1 */
    622. 

  622. #define EBI_POLARITY1_WEPOL_DEFAULT               (_EBI_POLARITY1_WEPOL_DEFAULT << 2)      /**< Shifted mode DEFAULT for EBI_POLARITY1 */
    623. 

  623. #define EBI_POLARITY1_WEPOL_ACTIVELOW             (_EBI_POLARITY1_WEPOL_ACTIVELOW << 2)    /**< Shifted mode ACTIVELOW for EBI_POLARITY1 */
    624. 

  624. #define EBI_POLARITY1_WEPOL_ACTIVEHIGH            (_EBI_POLARITY1_WEPOL_ACTIVEHIGH << 2)   /**< Shifted mode ACTIVEHIGH for EBI_POLARITY1 */
    625. 

  625. #define EBI_POLARITY1_ALEPOL                      (0x1UL << 3)                             /**< Address Latch Polarity */
    626. 

  626. #define _EBI_POLARITY1_ALEPOL_SHIFT               3                                        /**< Shift value for EBI_ALEPOL */
    627. 

  627. #define _EBI_POLARITY1_ALEPOL_MASK                0x8UL                                    /**< Bit mask for EBI_ALEPOL */
    628. 

  628. #define _EBI_POLARITY1_ALEPOL_DEFAULT             0x00000000UL                             /**< Mode DEFAULT for EBI_POLARITY1 */
    629. 

  629. #define _EBI_POLARITY1_ALEPOL_ACTIVELOW           0x00000000UL                             /**< Mode ACTIVELOW for EBI_POLARITY1 */
    630. 

  630. #define _EBI_POLARITY1_ALEPOL_ACTIVEHIGH          0x00000001UL                             /**< Mode ACTIVEHIGH for EBI_POLARITY1 */
    631. 

  631. #define EBI_POLARITY1_ALEPOL_DEFAULT              (_EBI_POLARITY1_ALEPOL_DEFAULT << 3)     /**< Shifted mode DEFAULT for EBI_POLARITY1 */
    632. 

  632. #define EBI_POLARITY1_ALEPOL_ACTIVELOW            (_EBI_POLARITY1_ALEPOL_ACTIVELOW << 3)   /**< Shifted mode ACTIVELOW for EBI_POLARITY1 */
    633. 

  633. #define EBI_POLARITY1_ALEPOL_ACTIVEHIGH           (_EBI_POLARITY1_ALEPOL_ACTIVEHIGH << 3)  /**< Shifted mode ACTIVEHIGH for EBI_POLARITY1 */
    634. 

  634. #define EBI_POLARITY1_ARDYPOL                     (0x1UL << 4)                             /**< ARDY Polarity */
    635. 

  635. #define _EBI_POLARITY1_ARDYPOL_SHIFT              4                                        /**< Shift value for EBI_ARDYPOL */
    636. 

  636. #define _EBI_POLARITY1_ARDYPOL_MASK               0x10UL                                   /**< Bit mask for EBI_ARDYPOL */
    637. 

  637. #define _EBI_POLARITY1_ARDYPOL_DEFAULT            0x00000000UL                             /**< Mode DEFAULT for EBI_POLARITY1 */
    638. 

  638. #define _EBI_POLARITY1_ARDYPOL_ACTIVELOW          0x00000000UL                             /**< Mode ACTIVELOW for EBI_POLARITY1 */
    639. 

  639. #define _EBI_POLARITY1_ARDYPOL_ACTIVEHIGH         0x00000001UL                             /**< Mode ACTIVEHIGH for EBI_POLARITY1 */
    640. 

  640. #define EBI_POLARITY1_ARDYPOL_DEFAULT             (_EBI_POLARITY1_ARDYPOL_DEFAULT << 4)    /**< Shifted mode DEFAULT for EBI_POLARITY1 */
    641. 

  641. #define EBI_POLARITY1_ARDYPOL_ACTIVELOW           (_EBI_POLARITY1_ARDYPOL_ACTIVELOW << 4)  /**< Shifted mode ACTIVELOW for EBI_POLARITY1 */
    642. 

  642. #define EBI_POLARITY1_ARDYPOL_ACTIVEHIGH          (_EBI_POLARITY1_ARDYPOL_ACTIVEHIGH << 4) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY1 */
    643. 

  643. #define EBI_POLARITY1_BLPOL                       (0x1UL << 5)                             /**< BL Polarity */
    644. 

  644. #define _EBI_POLARITY1_BLPOL_SHIFT                5                                        /**< Shift value for EBI_BLPOL */
    645. 

  645. #define _EBI_POLARITY1_BLPOL_MASK                 0x20UL                                   /**< Bit mask for EBI_BLPOL */
    646. 

  646. #define _EBI_POLARITY1_BLPOL_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for EBI_POLARITY1 */
    647. 

  647. #define _EBI_POLARITY1_BLPOL_ACTIVELOW            0x00000000UL                             /**< Mode ACTIVELOW for EBI_POLARITY1 */
    648. 

  648. #define _EBI_POLARITY1_BLPOL_ACTIVEHIGH           0x00000001UL                             /**< Mode ACTIVEHIGH for EBI_POLARITY1 */
    649. 

  649. #define EBI_POLARITY1_BLPOL_DEFAULT               (_EBI_POLARITY1_BLPOL_DEFAULT << 5)      /**< Shifted mode DEFAULT for EBI_POLARITY1 */
    650. 

  650. #define EBI_POLARITY1_BLPOL_ACTIVELOW             (_EBI_POLARITY1_BLPOL_ACTIVELOW << 5)    /**< Shifted mode ACTIVELOW for EBI_POLARITY1 */
    651. 

  651. #define EBI_POLARITY1_BLPOL_ACTIVEHIGH            (_EBI_POLARITY1_BLPOL_ACTIVEHIGH << 5)   /**< Shifted mode ACTIVEHIGH for EBI_POLARITY1 */
    652. 

  652. 

  653. /* Bit fields for EBI ADDRTIMING2 */
    654. 

  654. #define _EBI_ADDRTIMING2_RESETVALUE               0x00000303UL                              /**< Default value for EBI_ADDRTIMING2 */
    655. 

  655. #define _EBI_ADDRTIMING2_MASK                     0x10000303UL                              /**< Mask for EBI_ADDRTIMING2 */
    656. 

  656. #define _EBI_ADDRTIMING2_ADDRSETUP_SHIFT          0                                         /**< Shift value for EBI_ADDRSETUP */
    657. 

  657. #define _EBI_ADDRTIMING2_ADDRSETUP_MASK           0x3UL                                     /**< Bit mask for EBI_ADDRSETUP */
    658. 

  658. #define _EBI_ADDRTIMING2_ADDRSETUP_DEFAULT        0x00000003UL                              /**< Mode DEFAULT for EBI_ADDRTIMING2 */
    659. 

  659. #define EBI_ADDRTIMING2_ADDRSETUP_DEFAULT         (_EBI_ADDRTIMING2_ADDRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ADDRTIMING2 */
    660. 

  660. #define _EBI_ADDRTIMING2_ADDRHOLD_SHIFT           8                                         /**< Shift value for EBI_ADDRHOLD */
    661. 

  661. #define _EBI_ADDRTIMING2_ADDRHOLD_MASK            0x300UL                                   /**< Bit mask for EBI_ADDRHOLD */
    662. 

  662. #define _EBI_ADDRTIMING2_ADDRHOLD_DEFAULT         0x00000003UL                              /**< Mode DEFAULT for EBI_ADDRTIMING2 */
    663. 

  663. #define EBI_ADDRTIMING2_ADDRHOLD_DEFAULT          (_EBI_ADDRTIMING2_ADDRHOLD_DEFAULT << 8)  /**< Shifted mode DEFAULT for EBI_ADDRTIMING2 */
    664. 

  664. #define EBI_ADDRTIMING2_HALFALE                   (0x1UL << 28)                             /**< Half Cycle ALE Strobe Duration Enable */
    665. 

  665. #define _EBI_ADDRTIMING2_HALFALE_SHIFT            28                                        /**< Shift value for EBI_HALFALE */
    666. 

  666. #define _EBI_ADDRTIMING2_HALFALE_MASK             0x10000000UL                              /**< Bit mask for EBI_HALFALE */
    667. 

  667. #define _EBI_ADDRTIMING2_HALFALE_DEFAULT          0x00000000UL                              /**< Mode DEFAULT for EBI_ADDRTIMING2 */
    668. 

  668. #define EBI_ADDRTIMING2_HALFALE_DEFAULT           (_EBI_ADDRTIMING2_HALFALE_DEFAULT << 28)  /**< Shifted mode DEFAULT for EBI_ADDRTIMING2 */
    669. 

  669. 

  670. /* Bit fields for EBI RDTIMING2 */
    671. 

  671. #define _EBI_RDTIMING2_RESETVALUE                 0x00033F03UL                            /**< Default value for EBI_RDTIMING2 */
    672. 

  672. #define _EBI_RDTIMING2_MASK                       0x70033F03UL                            /**< Mask for EBI_RDTIMING2 */
    673. 

  673. #define _EBI_RDTIMING2_RDSETUP_SHIFT              0                                       /**< Shift value for EBI_RDSETUP */
    674. 

  674. #define _EBI_RDTIMING2_RDSETUP_MASK               0x3UL                                   /**< Bit mask for EBI_RDSETUP */
    675. 

  675. #define _EBI_RDTIMING2_RDSETUP_DEFAULT            0x00000003UL                            /**< Mode DEFAULT for EBI_RDTIMING2 */
    676. 

  676. #define EBI_RDTIMING2_RDSETUP_DEFAULT             (_EBI_RDTIMING2_RDSETUP_DEFAULT << 0)   /**< Shifted mode DEFAULT for EBI_RDTIMING2 */
    677. 

  677. #define _EBI_RDTIMING2_RDSTRB_SHIFT               8                                       /**< Shift value for EBI_RDSTRB */
    678. 

  678. #define _EBI_RDTIMING2_RDSTRB_MASK                0x3F00UL                                /**< Bit mask for EBI_RDSTRB */
    679. 

  679. #define _EBI_RDTIMING2_RDSTRB_DEFAULT             0x0000003FUL                            /**< Mode DEFAULT for EBI_RDTIMING2 */
    680. 

  680. #define EBI_RDTIMING2_RDSTRB_DEFAULT              (_EBI_RDTIMING2_RDSTRB_DEFAULT << 8)    /**< Shifted mode DEFAULT for EBI_RDTIMING2 */
    681. 

  681. #define _EBI_RDTIMING2_RDHOLD_SHIFT               16                                      /**< Shift value for EBI_RDHOLD */
    682. 

  682. #define _EBI_RDTIMING2_RDHOLD_MASK                0x30000UL                               /**< Bit mask for EBI_RDHOLD */
    683. 

  683. #define _EBI_RDTIMING2_RDHOLD_DEFAULT             0x00000003UL                            /**< Mode DEFAULT for EBI_RDTIMING2 */
    684. 

  684. #define EBI_RDTIMING2_RDHOLD_DEFAULT              (_EBI_RDTIMING2_RDHOLD_DEFAULT << 16)   /**< Shifted mode DEFAULT for EBI_RDTIMING2 */
    685. 

  685. #define EBI_RDTIMING2_HALFRE                      (0x1UL << 28)                           /**< Half Cycle REn Strobe Duration Enable */
    686. 

  686. #define _EBI_RDTIMING2_HALFRE_SHIFT               28                                      /**< Shift value for EBI_HALFRE */
    687. 

  687. #define _EBI_RDTIMING2_HALFRE_MASK                0x10000000UL                            /**< Bit mask for EBI_HALFRE */
    688. 

  688. #define _EBI_RDTIMING2_HALFRE_DEFAULT             0x00000000UL                            /**< Mode DEFAULT for EBI_RDTIMING2 */
    689. 

  689. #define EBI_RDTIMING2_HALFRE_DEFAULT              (_EBI_RDTIMING2_HALFRE_DEFAULT << 28)   /**< Shifted mode DEFAULT for EBI_RDTIMING2 */
    690. 

  690. #define EBI_RDTIMING2_PREFETCH                    (0x1UL << 29)                           /**< Prefetch Enable */
    691. 

  691. #define _EBI_RDTIMING2_PREFETCH_SHIFT             29                                      /**< Shift value for EBI_PREFETCH */
    692. 

  692. #define _EBI_RDTIMING2_PREFETCH_MASK              0x20000000UL                            /**< Bit mask for EBI_PREFETCH */
    693. 

  693. #define _EBI_RDTIMING2_PREFETCH_DEFAULT           0x00000000UL                            /**< Mode DEFAULT for EBI_RDTIMING2 */
    694. 

  694. #define EBI_RDTIMING2_PREFETCH_DEFAULT            (_EBI_RDTIMING2_PREFETCH_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_RDTIMING2 */
    695. 

  695. #define EBI_RDTIMING2_PAGEMODE                    (0x1UL << 30)                           /**< Page Mode Access Enable */
    696. 

  696. #define _EBI_RDTIMING2_PAGEMODE_SHIFT             30                                      /**< Shift value for EBI_PAGEMODE */
    697. 

  697. #define _EBI_RDTIMING2_PAGEMODE_MASK              0x40000000UL                            /**< Bit mask for EBI_PAGEMODE */
    698. 

  698. #define _EBI_RDTIMING2_PAGEMODE_DEFAULT           0x00000000UL                            /**< Mode DEFAULT for EBI_RDTIMING2 */
    699. 

  699. #define EBI_RDTIMING2_PAGEMODE_DEFAULT            (_EBI_RDTIMING2_PAGEMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for EBI_RDTIMING2 */
    700. 

  700. 

  701. /* Bit fields for EBI WRTIMING2 */
    702. 

  702. #define _EBI_WRTIMING2_RESETVALUE                 0x00033F03UL                           /**< Default value for EBI_WRTIMING2 */
    703. 

  703. #define _EBI_WRTIMING2_MASK                       0x30033F03UL                           /**< Mask for EBI_WRTIMING2 */
    704. 

  704. #define _EBI_WRTIMING2_WRSETUP_SHIFT              0                                      /**< Shift value for EBI_WRSETUP */
    705. 

  705. #define _EBI_WRTIMING2_WRSETUP_MASK               0x3UL                                  /**< Bit mask for EBI_WRSETUP */
    706. 

  706. #define _EBI_WRTIMING2_WRSETUP_DEFAULT            0x00000003UL                           /**< Mode DEFAULT for EBI_WRTIMING2 */
    707. 

  707. #define EBI_WRTIMING2_WRSETUP_DEFAULT             (_EBI_WRTIMING2_WRSETUP_DEFAULT << 0)  /**< Shifted mode DEFAULT for EBI_WRTIMING2 */
    708. 

  708. #define _EBI_WRTIMING2_WRSTRB_SHIFT               8                                      /**< Shift value for EBI_WRSTRB */
    709. 

  709. #define _EBI_WRTIMING2_WRSTRB_MASK                0x3F00UL                               /**< Bit mask for EBI_WRSTRB */
    710. 

  710. #define _EBI_WRTIMING2_WRSTRB_DEFAULT             0x0000003FUL                           /**< Mode DEFAULT for EBI_WRTIMING2 */
    711. 

  711. #define EBI_WRTIMING2_WRSTRB_DEFAULT              (_EBI_WRTIMING2_WRSTRB_DEFAULT << 8)   /**< Shifted mode DEFAULT for EBI_WRTIMING2 */
    712. 

  712. #define _EBI_WRTIMING2_WRHOLD_SHIFT               16                                     /**< Shift value for EBI_WRHOLD */
    713. 

  713. #define _EBI_WRTIMING2_WRHOLD_MASK                0x30000UL                              /**< Bit mask for EBI_WRHOLD */
    714. 

  714. #define _EBI_WRTIMING2_WRHOLD_DEFAULT             0x00000003UL                           /**< Mode DEFAULT for EBI_WRTIMING2 */
    715. 

  715. #define EBI_WRTIMING2_WRHOLD_DEFAULT              (_EBI_WRTIMING2_WRHOLD_DEFAULT << 16)  /**< Shifted mode DEFAULT for EBI_WRTIMING2 */
    716. 

  716. #define EBI_WRTIMING2_HALFWE                      (0x1UL << 28)                          /**< Half Cycle WEn Strobe Duration Enable */
    717. 

  717. #define _EBI_WRTIMING2_HALFWE_SHIFT               28                                     /**< Shift value for EBI_HALFWE */
    718. 

  718. #define _EBI_WRTIMING2_HALFWE_MASK                0x10000000UL                           /**< Bit mask for EBI_HALFWE */
    719. 

  719. #define _EBI_WRTIMING2_HALFWE_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for EBI_WRTIMING2 */
    720. 

  720. #define EBI_WRTIMING2_HALFWE_DEFAULT              (_EBI_WRTIMING2_HALFWE_DEFAULT << 28)  /**< Shifted mode DEFAULT for EBI_WRTIMING2 */
    721. 

  721. #define EBI_WRTIMING2_WBUFDIS                     (0x1UL << 29)                          /**< Write Buffer Disable */
    722. 

  722. #define _EBI_WRTIMING2_WBUFDIS_SHIFT              29                                     /**< Shift value for EBI_WBUFDIS */
    723. 

  723. #define _EBI_WRTIMING2_WBUFDIS_MASK               0x20000000UL                           /**< Bit mask for EBI_WBUFDIS */
    724. 

  724. #define _EBI_WRTIMING2_WBUFDIS_DEFAULT            0x00000000UL                           /**< Mode DEFAULT for EBI_WRTIMING2 */
    725. 

  725. #define EBI_WRTIMING2_WBUFDIS_DEFAULT             (_EBI_WRTIMING2_WBUFDIS_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_WRTIMING2 */
    726. 

  726. 

  727. /* Bit fields for EBI POLARITY2 */
    728. 

  728. #define _EBI_POLARITY2_RESETVALUE                 0x00000000UL                             /**< Default value for EBI_POLARITY2 */
    729. 

  729. #define _EBI_POLARITY2_MASK                       0x0000003FUL                             /**< Mask for EBI_POLARITY2 */
    730. 

  730. #define EBI_POLARITY2_CSPOL                       (0x1UL << 0)                             /**< Chip Select Polarity */
    731. 

  731. #define _EBI_POLARITY2_CSPOL_SHIFT                0                                        /**< Shift value for EBI_CSPOL */
    732. 

  732. #define _EBI_POLARITY2_CSPOL_MASK                 0x1UL                                    /**< Bit mask for EBI_CSPOL */
    733. 

  733. #define _EBI_POLARITY2_CSPOL_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for EBI_POLARITY2 */
    734. 

  734. #define _EBI_POLARITY2_CSPOL_ACTIVELOW            0x00000000UL                             /**< Mode ACTIVELOW for EBI_POLARITY2 */
    735. 

  735. #define _EBI_POLARITY2_CSPOL_ACTIVEHIGH           0x00000001UL                             /**< Mode ACTIVEHIGH for EBI_POLARITY2 */
    736. 

  736. #define EBI_POLARITY2_CSPOL_DEFAULT               (_EBI_POLARITY2_CSPOL_DEFAULT << 0)      /**< Shifted mode DEFAULT for EBI_POLARITY2 */
    737. 

  737. #define EBI_POLARITY2_CSPOL_ACTIVELOW             (_EBI_POLARITY2_CSPOL_ACTIVELOW << 0)    /**< Shifted mode ACTIVELOW for EBI_POLARITY2 */
    738. 

  738. #define EBI_POLARITY2_CSPOL_ACTIVEHIGH            (_EBI_POLARITY2_CSPOL_ACTIVEHIGH << 0)   /**< Shifted mode ACTIVEHIGH for EBI_POLARITY2 */
    739. 

  739. #define EBI_POLARITY2_REPOL                       (0x1UL << 1)                             /**< Read Enable Polarity */
    740. 

  740. #define _EBI_POLARITY2_REPOL_SHIFT                1                                        /**< Shift value for EBI_REPOL */
    741. 

  741. #define _EBI_POLARITY2_REPOL_MASK                 0x2UL                                    /**< Bit mask for EBI_REPOL */
    742. 

  742. #define _EBI_POLARITY2_REPOL_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for EBI_POLARITY2 */
    743. 

  743. #define _EBI_POLARITY2_REPOL_ACTIVELOW            0x00000000UL                             /**< Mode ACTIVELOW for EBI_POLARITY2 */
    744. 

  744. #define _EBI_POLARITY2_REPOL_ACTIVEHIGH           0x00000001UL                             /**< Mode ACTIVEHIGH for EBI_POLARITY2 */
    745. 

  745. #define EBI_POLARITY2_REPOL_DEFAULT               (_EBI_POLARITY2_REPOL_DEFAULT << 1)      /**< Shifted mode DEFAULT for EBI_POLARITY2 */
    746. 

  746. #define EBI_POLARITY2_REPOL_ACTIVELOW             (_EBI_POLARITY2_REPOL_ACTIVELOW << 1)    /**< Shifted mode ACTIVELOW for EBI_POLARITY2 */
    747. 

  747. #define EBI_POLARITY2_REPOL_ACTIVEHIGH            (_EBI_POLARITY2_REPOL_ACTIVEHIGH << 1)   /**< Shifted mode ACTIVEHIGH for EBI_POLARITY2 */
    748. 

  748. #define EBI_POLARITY2_WEPOL                       (0x1UL << 2)                             /**< Write Enable Polarity */
    749. 

  749. #define _EBI_POLARITY2_WEPOL_SHIFT                2                                        /**< Shift value for EBI_WEPOL */
    750. 

  750. #define _EBI_POLARITY2_WEPOL_MASK                 0x4UL                                    /**< Bit mask for EBI_WEPOL */
    751. 

  751. #define _EBI_POLARITY2_WEPOL_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for EBI_POLARITY2 */
    752. 

  752. #define _EBI_POLARITY2_WEPOL_ACTIVELOW            0x00000000UL                             /**< Mode ACTIVELOW for EBI_POLARITY2 */
    753. 

  753. #define _EBI_POLARITY2_WEPOL_ACTIVEHIGH           0x00000001UL                             /**< Mode ACTIVEHIGH for EBI_POLARITY2 */
    754. 

  754. #define EBI_POLARITY2_WEPOL_DEFAULT               (_EBI_POLARITY2_WEPOL_DEFAULT << 2)      /**< Shifted mode DEFAULT for EBI_POLARITY2 */
    755. 

  755. #define EBI_POLARITY2_WEPOL_ACTIVELOW             (_EBI_POLARITY2_WEPOL_ACTIVELOW << 2)    /**< Shifted mode ACTIVELOW for EBI_POLARITY2 */
    756. 

  756. #define EBI_POLARITY2_WEPOL_ACTIVEHIGH            (_EBI_POLARITY2_WEPOL_ACTIVEHIGH << 2)   /**< Shifted mode ACTIVEHIGH for EBI_POLARITY2 */
    757. 

  757. #define EBI_POLARITY2_ALEPOL                      (0x1UL << 3)                             /**< Address Latch Polarity */
    758. 

  758. #define _EBI_POLARITY2_ALEPOL_SHIFT               3                                        /**< Shift value for EBI_ALEPOL */
    759. 

  759. #define _EBI_POLARITY2_ALEPOL_MASK                0x8UL                                    /**< Bit mask for EBI_ALEPOL */
    760. 

  760. #define _EBI_POLARITY2_ALEPOL_DEFAULT             0x00000000UL                             /**< Mode DEFAULT for EBI_POLARITY2 */
    761. 

  761. #define _EBI_POLARITY2_ALEPOL_ACTIVELOW           0x00000000UL                             /**< Mode ACTIVELOW for EBI_POLARITY2 */
    762. 

  762. #define _EBI_POLARITY2_ALEPOL_ACTIVEHIGH          0x00000001UL                             /**< Mode ACTIVEHIGH for EBI_POLARITY2 */
    763. 

  763. #define EBI_POLARITY2_ALEPOL_DEFAULT              (_EBI_POLARITY2_ALEPOL_DEFAULT << 3)     /**< Shifted mode DEFAULT for EBI_POLARITY2 */
    764. 

  764. #define EBI_POLARITY2_ALEPOL_ACTIVELOW            (_EBI_POLARITY2_ALEPOL_ACTIVELOW << 3)   /**< Shifted mode ACTIVELOW for EBI_POLARITY2 */
    765. 

  765. #define EBI_POLARITY2_ALEPOL_ACTIVEHIGH           (_EBI_POLARITY2_ALEPOL_ACTIVEHIGH << 3)  /**< Shifted mode ACTIVEHIGH for EBI_POLARITY2 */
    766. 

  766. #define EBI_POLARITY2_ARDYPOL                     (0x1UL << 4)                             /**< ARDY Polarity */
    767. 

  767. #define _EBI_POLARITY2_ARDYPOL_SHIFT              4                                        /**< Shift value for EBI_ARDYPOL */
    768. 

  768. #define _EBI_POLARITY2_ARDYPOL_MASK               0x10UL                                   /**< Bit mask for EBI_ARDYPOL */
    769. 

  769. #define _EBI_POLARITY2_ARDYPOL_DEFAULT            0x00000000UL                             /**< Mode DEFAULT for EBI_POLARITY2 */
    770. 

  770. #define _EBI_POLARITY2_ARDYPOL_ACTIVELOW          0x00000000UL                             /**< Mode ACTIVELOW for EBI_POLARITY2 */
    771. 

  771. #define _EBI_POLARITY2_ARDYPOL_ACTIVEHIGH         0x00000001UL                             /**< Mode ACTIVEHIGH for EBI_POLARITY2 */
    772. 

  772. #define EBI_POLARITY2_ARDYPOL_DEFAULT             (_EBI_POLARITY2_ARDYPOL_DEFAULT << 4)    /**< Shifted mode DEFAULT for EBI_POLARITY2 */
    773. 

  773. #define EBI_POLARITY2_ARDYPOL_ACTIVELOW           (_EBI_POLARITY2_ARDYPOL_ACTIVELOW << 4)  /**< Shifted mode ACTIVELOW for EBI_POLARITY2 */
    774. 

  774. #define EBI_POLARITY2_ARDYPOL_ACTIVEHIGH          (_EBI_POLARITY2_ARDYPOL_ACTIVEHIGH << 4) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY2 */
    775. 

  775. #define EBI_POLARITY2_BLPOL                       (0x1UL << 5)                             /**< BL Polarity */
    776. 

  776. #define _EBI_POLARITY2_BLPOL_SHIFT                5                                        /**< Shift value for EBI_BLPOL */
    777. 

  777. #define _EBI_POLARITY2_BLPOL_MASK                 0x20UL                                   /**< Bit mask for EBI_BLPOL */
    778. 

  778. #define _EBI_POLARITY2_BLPOL_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for EBI_POLARITY2 */
    779. 

  779. #define _EBI_POLARITY2_BLPOL_ACTIVELOW            0x00000000UL                             /**< Mode ACTIVELOW for EBI_POLARITY2 */
    780. 

  780. #define _EBI_POLARITY2_BLPOL_ACTIVEHIGH           0x00000001UL                             /**< Mode ACTIVEHIGH for EBI_POLARITY2 */
    781. 

  781. #define EBI_POLARITY2_BLPOL_DEFAULT               (_EBI_POLARITY2_BLPOL_DEFAULT << 5)      /**< Shifted mode DEFAULT for EBI_POLARITY2 */
    782. 

  782. #define EBI_POLARITY2_BLPOL_ACTIVELOW             (_EBI_POLARITY2_BLPOL_ACTIVELOW << 5)    /**< Shifted mode ACTIVELOW for EBI_POLARITY2 */
    783. 

  783. #define EBI_POLARITY2_BLPOL_ACTIVEHIGH            (_EBI_POLARITY2_BLPOL_ACTIVEHIGH << 5)   /**< Shifted mode ACTIVEHIGH for EBI_POLARITY2 */
    784. 

  784. 

  785. /* Bit fields for EBI ADDRTIMING3 */
    786. 

  786. #define _EBI_ADDRTIMING3_RESETVALUE               0x00000303UL                              /**< Default value for EBI_ADDRTIMING3 */
    787. 

  787. #define _EBI_ADDRTIMING3_MASK                     0x10000303UL                              /**< Mask for EBI_ADDRTIMING3 */
    788. 

  788. #define _EBI_ADDRTIMING3_ADDRSETUP_SHIFT          0                                         /**< Shift value for EBI_ADDRSETUP */
    789. 

  789. #define _EBI_ADDRTIMING3_ADDRSETUP_MASK           0x3UL                                     /**< Bit mask for EBI_ADDRSETUP */
    790. 

  790. #define _EBI_ADDRTIMING3_ADDRSETUP_DEFAULT        0x00000003UL                              /**< Mode DEFAULT for EBI_ADDRTIMING3 */
    791. 

  791. #define EBI_ADDRTIMING3_ADDRSETUP_DEFAULT         (_EBI_ADDRTIMING3_ADDRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ADDRTIMING3 */
    792. 

  792. #define _EBI_ADDRTIMING3_ADDRHOLD_SHIFT           8                                         /**< Shift value for EBI_ADDRHOLD */
    793. 

  793. #define _EBI_ADDRTIMING3_ADDRHOLD_MASK            0x300UL                                   /**< Bit mask for EBI_ADDRHOLD */
    794. 

  794. #define _EBI_ADDRTIMING3_ADDRHOLD_DEFAULT         0x00000003UL                              /**< Mode DEFAULT for EBI_ADDRTIMING3 */
    795. 

  795. #define EBI_ADDRTIMING3_ADDRHOLD_DEFAULT          (_EBI_ADDRTIMING3_ADDRHOLD_DEFAULT << 8)  /**< Shifted mode DEFAULT for EBI_ADDRTIMING3 */
    796. 

  796. #define EBI_ADDRTIMING3_HALFALE                   (0x1UL << 28)                             /**< Half Cycle ALE Strobe Duration Enable */
    797. 

  797. #define _EBI_ADDRTIMING3_HALFALE_SHIFT            28                                        /**< Shift value for EBI_HALFALE */
    798. 

  798. #define _EBI_ADDRTIMING3_HALFALE_MASK             0x10000000UL                              /**< Bit mask for EBI_HALFALE */
    799. 

  799. #define _EBI_ADDRTIMING3_HALFALE_DEFAULT          0x00000000UL                              /**< Mode DEFAULT for EBI_ADDRTIMING3 */
    800. 

  800. #define EBI_ADDRTIMING3_HALFALE_DEFAULT           (_EBI_ADDRTIMING3_HALFALE_DEFAULT << 28)  /**< Shifted mode DEFAULT for EBI_ADDRTIMING3 */
    801. 

  801. 

  802. /* Bit fields for EBI RDTIMING3 */
    803. 

  803. #define _EBI_RDTIMING3_RESETVALUE                 0x00033F03UL                            /**< Default value for EBI_RDTIMING3 */
    804. 

  804. #define _EBI_RDTIMING3_MASK                       0x70033F03UL                            /**< Mask for EBI_RDTIMING3 */
    805. 

  805. #define _EBI_RDTIMING3_RDSETUP_SHIFT              0                                       /**< Shift value for EBI_RDSETUP */
    806. 

  806. #define _EBI_RDTIMING3_RDSETUP_MASK               0x3UL                                   /**< Bit mask for EBI_RDSETUP */
    807. 

  807. #define _EBI_RDTIMING3_RDSETUP_DEFAULT            0x00000003UL                            /**< Mode DEFAULT for EBI_RDTIMING3 */
    808. 

  808. #define EBI_RDTIMING3_RDSETUP_DEFAULT             (_EBI_RDTIMING3_RDSETUP_DEFAULT << 0)   /**< Shifted mode DEFAULT for EBI_RDTIMING3 */
    809. 

  809. #define _EBI_RDTIMING3_RDSTRB_SHIFT               8                                       /**< Shift value for EBI_RDSTRB */
    810. 

  810. #define _EBI_RDTIMING3_RDSTRB_MASK                0x3F00UL                                /**< Bit mask for EBI_RDSTRB */
    811. 

  811. #define _EBI_RDTIMING3_RDSTRB_DEFAULT             0x0000003FUL                            /**< Mode DEFAULT for EBI_RDTIMING3 */
    812. 

  812. #define EBI_RDTIMING3_RDSTRB_DEFAULT              (_EBI_RDTIMING3_RDSTRB_DEFAULT << 8)    /**< Shifted mode DEFAULT for EBI_RDTIMING3 */
    813. 

  813. #define _EBI_RDTIMING3_RDHOLD_SHIFT               16                                      /**< Shift value for EBI_RDHOLD */
    814. 

  814. #define _EBI_RDTIMING3_RDHOLD_MASK                0x30000UL                               /**< Bit mask for EBI_RDHOLD */
    815. 

  815. #define _EBI_RDTIMING3_RDHOLD_DEFAULT             0x00000003UL                            /**< Mode DEFAULT for EBI_RDTIMING3 */
    816. 

  816. #define EBI_RDTIMING3_RDHOLD_DEFAULT              (_EBI_RDTIMING3_RDHOLD_DEFAULT << 16)   /**< Shifted mode DEFAULT for EBI_RDTIMING3 */
    817. 

  817. #define EBI_RDTIMING3_HALFRE                      (0x1UL << 28)                           /**< Half Cycle REn Strobe Duration Enable */
    818. 

  818. #define _EBI_RDTIMING3_HALFRE_SHIFT               28                                      /**< Shift value for EBI_HALFRE */
    819. 

  819. #define _EBI_RDTIMING3_HALFRE_MASK                0x10000000UL                            /**< Bit mask for EBI_HALFRE */
    820. 

  820. #define _EBI_RDTIMING3_HALFRE_DEFAULT             0x00000000UL                            /**< Mode DEFAULT for EBI_RDTIMING3 */
    821. 

  821. #define EBI_RDTIMING3_HALFRE_DEFAULT              (_EBI_RDTIMING3_HALFRE_DEFAULT << 28)   /**< Shifted mode DEFAULT for EBI_RDTIMING3 */
    822. 

  822. #define EBI_RDTIMING3_PREFETCH                    (0x1UL << 29)                           /**< Prefetch Enable */
    823. 

  823. #define _EBI_RDTIMING3_PREFETCH_SHIFT             29                                      /**< Shift value for EBI_PREFETCH */
    824. 

  824. #define _EBI_RDTIMING3_PREFETCH_MASK              0x20000000UL                            /**< Bit mask for EBI_PREFETCH */
    825. 

  825. #define _EBI_RDTIMING3_PREFETCH_DEFAULT           0x00000000UL                            /**< Mode DEFAULT for EBI_RDTIMING3 */
    826. 

  826. #define EBI_RDTIMING3_PREFETCH_DEFAULT            (_EBI_RDTIMING3_PREFETCH_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_RDTIMING3 */
    827. 

  827. #define EBI_RDTIMING3_PAGEMODE                    (0x1UL << 30)                           /**< Page Mode Access Enable */
    828. 

  828. #define _EBI_RDTIMING3_PAGEMODE_SHIFT             30                                      /**< Shift value for EBI_PAGEMODE */
    829. 

  829. #define _EBI_RDTIMING3_PAGEMODE_MASK              0x40000000UL                            /**< Bit mask for EBI_PAGEMODE */
    830. 

  830. #define _EBI_RDTIMING3_PAGEMODE_DEFAULT           0x00000000UL                            /**< Mode DEFAULT for EBI_RDTIMING3 */
    831. 

  831. #define EBI_RDTIMING3_PAGEMODE_DEFAULT            (_EBI_RDTIMING3_PAGEMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for EBI_RDTIMING3 */
    832. 

  832. 

  833. /* Bit fields for EBI WRTIMING3 */
    834. 

  834. #define _EBI_WRTIMING3_RESETVALUE                 0x00033F03UL                           /**< Default value for EBI_WRTIMING3 */
    835. 

  835. #define _EBI_WRTIMING3_MASK                       0x30033F03UL                           /**< Mask for EBI_WRTIMING3 */
    836. 

  836. #define _EBI_WRTIMING3_WRSETUP_SHIFT              0                                      /**< Shift value for EBI_WRSETUP */
    837. 

  837. #define _EBI_WRTIMING3_WRSETUP_MASK               0x3UL                                  /**< Bit mask for EBI_WRSETUP */
    838. 

  838. #define _EBI_WRTIMING3_WRSETUP_DEFAULT            0x00000003UL                           /**< Mode DEFAULT for EBI_WRTIMING3 */
    839. 

  839. #define EBI_WRTIMING3_WRSETUP_DEFAULT             (_EBI_WRTIMING3_WRSETUP_DEFAULT << 0)  /**< Shifted mode DEFAULT for EBI_WRTIMING3 */
    840. 

  840. #define _EBI_WRTIMING3_WRSTRB_SHIFT               8                                      /**< Shift value for EBI_WRSTRB */
    841. 

  841. #define _EBI_WRTIMING3_WRSTRB_MASK                0x3F00UL                               /**< Bit mask for EBI_WRSTRB */
    842. 

  842. #define _EBI_WRTIMING3_WRSTRB_DEFAULT             0x0000003FUL                           /**< Mode DEFAULT for EBI_WRTIMING3 */
    843. 

  843. #define EBI_WRTIMING3_WRSTRB_DEFAULT              (_EBI_WRTIMING3_WRSTRB_DEFAULT << 8)   /**< Shifted mode DEFAULT for EBI_WRTIMING3 */
    844. 

  844. #define _EBI_WRTIMING3_WRHOLD_SHIFT               16                                     /**< Shift value for EBI_WRHOLD */
    845. 

  845. #define _EBI_WRTIMING3_WRHOLD_MASK                0x30000UL                              /**< Bit mask for EBI_WRHOLD */
    846. 

  846. #define _EBI_WRTIMING3_WRHOLD_DEFAULT             0x00000003UL                           /**< Mode DEFAULT for EBI_WRTIMING3 */
    847. 

  847. #define EBI_WRTIMING3_WRHOLD_DEFAULT              (_EBI_WRTIMING3_WRHOLD_DEFAULT << 16)  /**< Shifted mode DEFAULT for EBI_WRTIMING3 */
    848. 

  848. #define EBI_WRTIMING3_HALFWE                      (0x1UL << 28)                          /**< Half Cycle WEn Strobe Duration Enable */
    849. 

  849. #define _EBI_WRTIMING3_HALFWE_SHIFT               28                                     /**< Shift value for EBI_HALFWE */
    850. 

  850. #define _EBI_WRTIMING3_HALFWE_MASK                0x10000000UL                           /**< Bit mask for EBI_HALFWE */
    851. 

  851. #define _EBI_WRTIMING3_HALFWE_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for EBI_WRTIMING3 */
    852. 

  852. #define EBI_WRTIMING3_HALFWE_DEFAULT              (_EBI_WRTIMING3_HALFWE_DEFAULT << 28)  /**< Shifted mode DEFAULT for EBI_WRTIMING3 */
    853. 

  853. #define EBI_WRTIMING3_WBUFDIS                     (0x1UL << 29)                          /**< Write Buffer Disable */
    854. 

  854. #define _EBI_WRTIMING3_WBUFDIS_SHIFT              29                                     /**< Shift value for EBI_WBUFDIS */
    855. 

  855. #define _EBI_WRTIMING3_WBUFDIS_MASK               0x20000000UL                           /**< Bit mask for EBI_WBUFDIS */
    856. 

  856. #define _EBI_WRTIMING3_WBUFDIS_DEFAULT            0x00000000UL                           /**< Mode DEFAULT for EBI_WRTIMING3 */
    857. 

  857. #define EBI_WRTIMING3_WBUFDIS_DEFAULT             (_EBI_WRTIMING3_WBUFDIS_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_WRTIMING3 */
    858. 

  858. 

  859. /* Bit fields for EBI POLARITY3 */
    860. 

  860. #define _EBI_POLARITY3_RESETVALUE                 0x00000000UL                             /**< Default value for EBI_POLARITY3 */
    861. 

  861. #define _EBI_POLARITY3_MASK                       0x0000003FUL                             /**< Mask for EBI_POLARITY3 */
    862. 

  862. #define EBI_POLARITY3_CSPOL                       (0x1UL << 0)                             /**< Chip Select Polarity */
    863. 

  863. #define _EBI_POLARITY3_CSPOL_SHIFT                0                                        /**< Shift value for EBI_CSPOL */
    864. 

  864. #define _EBI_POLARITY3_CSPOL_MASK                 0x1UL                                    /**< Bit mask for EBI_CSPOL */
    865. 

  865. #define _EBI_POLARITY3_CSPOL_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for EBI_POLARITY3 */
    866. 

  866. #define _EBI_POLARITY3_CSPOL_ACTIVELOW            0x00000000UL                             /**< Mode ACTIVELOW for EBI_POLARITY3 */
    867. 

  867. #define _EBI_POLARITY3_CSPOL_ACTIVEHIGH           0x00000001UL                             /**< Mode ACTIVEHIGH for EBI_POLARITY3 */
    868. 

  868. #define EBI_POLARITY3_CSPOL_DEFAULT               (_EBI_POLARITY3_CSPOL_DEFAULT << 0)      /**< Shifted mode DEFAULT for EBI_POLARITY3 */
    869. 

  869. #define EBI_POLARITY3_CSPOL_ACTIVELOW             (_EBI_POLARITY3_CSPOL_ACTIVELOW << 0)    /**< Shifted mode ACTIVELOW for EBI_POLARITY3 */
    870. 

  870. #define EBI_POLARITY3_CSPOL_ACTIVEHIGH            (_EBI_POLARITY3_CSPOL_ACTIVEHIGH << 0)   /**< Shifted mode ACTIVEHIGH for EBI_POLARITY3 */
    871. 

  871. #define EBI_POLARITY3_REPOL                       (0x1UL << 1)                             /**< Read Enable Polarity */
    872. 

  872. #define _EBI_POLARITY3_REPOL_SHIFT                1                                        /**< Shift value for EBI_REPOL */
    873. 

  873. #define _EBI_POLARITY3_REPOL_MASK                 0x2UL                                    /**< Bit mask for EBI_REPOL */
    874. 

  874. #define _EBI_POLARITY3_REPOL_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for EBI_POLARITY3 */
    875. 

  875. #define _EBI_POLARITY3_REPOL_ACTIVELOW            0x00000000UL                             /**< Mode ACTIVELOW for EBI_POLARITY3 */
    876. 

  876. #define _EBI_POLARITY3_REPOL_ACTIVEHIGH           0x00000001UL                             /**< Mode ACTIVEHIGH for EBI_POLARITY3 */
    877. 

  877. #define EBI_POLARITY3_REPOL_DEFAULT               (_EBI_POLARITY3_REPOL_DEFAULT << 1)      /**< Shifted mode DEFAULT for EBI_POLARITY3 */
    878. 

  878. #define EBI_POLARITY3_REPOL_ACTIVELOW             (_EBI_POLARITY3_REPOL_ACTIVELOW << 1)    /**< Shifted mode ACTIVELOW for EBI_POLARITY3 */
    879. 

  879. #define EBI_POLARITY3_REPOL_ACTIVEHIGH            (_EBI_POLARITY3_REPOL_ACTIVEHIGH << 1)   /**< Shifted mode ACTIVEHIGH for EBI_POLARITY3 */
    880. 

  880. #define EBI_POLARITY3_WEPOL                       (0x1UL << 2)                             /**< Write Enable Polarity */
    881. 

  881. #define _EBI_POLARITY3_WEPOL_SHIFT                2                                        /**< Shift value for EBI_WEPOL */
    882. 

  882. #define _EBI_POLARITY3_WEPOL_MASK                 0x4UL                                    /**< Bit mask for EBI_WEPOL */
    883. 

  883. #define _EBI_POLARITY3_WEPOL_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for EBI_POLARITY3 */
    884. 

  884. #define _EBI_POLARITY3_WEPOL_ACTIVELOW            0x00000000UL                             /**< Mode ACTIVELOW for EBI_POLARITY3 */
    885. 

  885. #define _EBI_POLARITY3_WEPOL_ACTIVEHIGH           0x00000001UL                             /**< Mode ACTIVEHIGH for EBI_POLARITY3 */
    886. 

  886. #define EBI_POLARITY3_WEPOL_DEFAULT               (_EBI_POLARITY3_WEPOL_DEFAULT << 2)      /**< Shifted mode DEFAULT for EBI_POLARITY3 */
    887. 

  887. #define EBI_POLARITY3_WEPOL_ACTIVELOW             (_EBI_POLARITY3_WEPOL_ACTIVELOW << 2)    /**< Shifted mode ACTIVELOW for EBI_POLARITY3 */
    888. 

  888. #define EBI_POLARITY3_WEPOL_ACTIVEHIGH            (_EBI_POLARITY3_WEPOL_ACTIVEHIGH << 2)   /**< Shifted mode ACTIVEHIGH for EBI_POLARITY3 */
    889. 

  889. #define EBI_POLARITY3_ALEPOL                      (0x1UL << 3)                             /**< Address Latch Polarity */
    890. 

  890. #define _EBI_POLARITY3_ALEPOL_SHIFT               3                                        /**< Shift value for EBI_ALEPOL */
    891. 

  891. #define _EBI_POLARITY3_ALEPOL_MASK                0x8UL                                    /**< Bit mask for EBI_ALEPOL */
    892. 

  892. #define _EBI_POLARITY3_ALEPOL_DEFAULT             0x00000000UL                             /**< Mode DEFAULT for EBI_POLARITY3 */
    893. 

  893. #define _EBI_POLARITY3_ALEPOL_ACTIVELOW           0x00000000UL                             /**< Mode ACTIVELOW for EBI_POLARITY3 */
    894. 

  894. #define _EBI_POLARITY3_ALEPOL_ACTIVEHIGH          0x00000001UL                             /**< Mode ACTIVEHIGH for EBI_POLARITY3 */
    895. 

  895. #define EBI_POLARITY3_ALEPOL_DEFAULT              (_EBI_POLARITY3_ALEPOL_DEFAULT << 3)     /**< Shifted mode DEFAULT for EBI_POLARITY3 */
    896. 

  896. #define EBI_POLARITY3_ALEPOL_ACTIVELOW            (_EBI_POLARITY3_ALEPOL_ACTIVELOW << 3)   /**< Shifted mode ACTIVELOW for EBI_POLARITY3 */
    897. 

  897. #define EBI_POLARITY3_ALEPOL_ACTIVEHIGH           (_EBI_POLARITY3_ALEPOL_ACTIVEHIGH << 3)  /**< Shifted mode ACTIVEHIGH for EBI_POLARITY3 */
    898. 

  898. #define EBI_POLARITY3_ARDYPOL                     (0x1UL << 4)                             /**< ARDY Polarity */
    899. 

  899. #define _EBI_POLARITY3_ARDYPOL_SHIFT              4                                        /**< Shift value for EBI_ARDYPOL */
    900. 

  900. #define _EBI_POLARITY3_ARDYPOL_MASK               0x10UL                                   /**< Bit mask for EBI_ARDYPOL */
    901. 

  901. #define _EBI_POLARITY3_ARDYPOL_DEFAULT            0x00000000UL                             /**< Mode DEFAULT for EBI_POLARITY3 */
    902. 

  902. #define _EBI_POLARITY3_ARDYPOL_ACTIVELOW          0x00000000UL                             /**< Mode ACTIVELOW for EBI_POLARITY3 */
    903. 

  903. #define _EBI_POLARITY3_ARDYPOL_ACTIVEHIGH         0x00000001UL                             /**< Mode ACTIVEHIGH for EBI_POLARITY3 */
    904. 

  904. #define EBI_POLARITY3_ARDYPOL_DEFAULT             (_EBI_POLARITY3_ARDYPOL_DEFAULT << 4)    /**< Shifted mode DEFAULT for EBI_POLARITY3 */
    905. 

  905. #define EBI_POLARITY3_ARDYPOL_ACTIVELOW           (_EBI_POLARITY3_ARDYPOL_ACTIVELOW << 4)  /**< Shifted mode ACTIVELOW for EBI_POLARITY3 */
    906. 

  906. #define EBI_POLARITY3_ARDYPOL_ACTIVEHIGH          (_EBI_POLARITY3_ARDYPOL_ACTIVEHIGH << 4) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY3 */
    907. 

  907. #define EBI_POLARITY3_BLPOL                       (0x1UL << 5)                             /**< BL Polarity */
    908. 

  908. #define _EBI_POLARITY3_BLPOL_SHIFT                5                                        /**< Shift value for EBI_BLPOL */
    909. 

  909. #define _EBI_POLARITY3_BLPOL_MASK                 0x20UL                                   /**< Bit mask for EBI_BLPOL */
    910. 

  910. #define _EBI_POLARITY3_BLPOL_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for EBI_POLARITY3 */
    911. 

  911. #define _EBI_POLARITY3_BLPOL_ACTIVELOW            0x00000000UL                             /**< Mode ACTIVELOW for EBI_POLARITY3 */
    912. 

  912. #define _EBI_POLARITY3_BLPOL_ACTIVEHIGH           0x00000001UL                             /**< Mode ACTIVEHIGH for EBI_POLARITY3 */
    913. 

  913. #define EBI_POLARITY3_BLPOL_DEFAULT               (_EBI_POLARITY3_BLPOL_DEFAULT << 5)      /**< Shifted mode DEFAULT for EBI_POLARITY3 */
    914. 

  914. #define EBI_POLARITY3_BLPOL_ACTIVELOW             (_EBI_POLARITY3_BLPOL_ACTIVELOW << 5)    /**< Shifted mode ACTIVELOW for EBI_POLARITY3 */
    915. 

  915. #define EBI_POLARITY3_BLPOL_ACTIVEHIGH            (_EBI_POLARITY3_BLPOL_ACTIVEHIGH << 5)   /**< Shifted mode ACTIVEHIGH for EBI_POLARITY3 */
    916. 

  916. 

  917. /* Bit fields for EBI PAGECTRL */
    918. 

  918. #define _EBI_PAGECTRL_RESETVALUE                  0x00000700UL                           /**< Default value for EBI_PAGECTRL */
    919. 

  919. #define _EBI_PAGECTRL_MASK                        0x07F00713UL                           /**< Mask for EBI_PAGECTRL */
    920. 

  920. #define _EBI_PAGECTRL_PAGELEN_SHIFT               0                                      /**< Shift value for EBI_PAGELEN */
    921. 

  921. #define _EBI_PAGECTRL_PAGELEN_MASK                0x3UL                                  /**< Bit mask for EBI_PAGELEN */
    922. 

  922. #define _EBI_PAGECTRL_PAGELEN_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for EBI_PAGECTRL */
    923. 

  923. #define _EBI_PAGECTRL_PAGELEN_MEMBER4             0x00000000UL                           /**< Mode MEMBER4 for EBI_PAGECTRL */
    924. 

  924. #define _EBI_PAGECTRL_PAGELEN_MEMBER8             0x00000001UL                           /**< Mode MEMBER8 for EBI_PAGECTRL */
    925. 

  925. #define _EBI_PAGECTRL_PAGELEN_MEMBER16            0x00000002UL                           /**< Mode MEMBER16 for EBI_PAGECTRL */
    926. 

  926. #define _EBI_PAGECTRL_PAGELEN_MEMBER32            0x00000003UL                           /**< Mode MEMBER32 for EBI_PAGECTRL */
    927. 

  927. #define EBI_PAGECTRL_PAGELEN_DEFAULT              (_EBI_PAGECTRL_PAGELEN_DEFAULT << 0)   /**< Shifted mode DEFAULT for EBI_PAGECTRL */
    928. 

  928. #define EBI_PAGECTRL_PAGELEN_MEMBER4              (_EBI_PAGECTRL_PAGELEN_MEMBER4 << 0)   /**< Shifted mode MEMBER4 for EBI_PAGECTRL */
    929. 

  929. #define EBI_PAGECTRL_PAGELEN_MEMBER8              (_EBI_PAGECTRL_PAGELEN_MEMBER8 << 0)   /**< Shifted mode MEMBER8 for EBI_PAGECTRL */
    930. 

  930. #define EBI_PAGECTRL_PAGELEN_MEMBER16             (_EBI_PAGECTRL_PAGELEN_MEMBER16 << 0)  /**< Shifted mode MEMBER16 for EBI_PAGECTRL */
    931. 

  931. #define EBI_PAGECTRL_PAGELEN_MEMBER32             (_EBI_PAGECTRL_PAGELEN_MEMBER32 << 0)  /**< Shifted mode MEMBER32 for EBI_PAGECTRL */
    932. 

  932. #define EBI_PAGECTRL_INCHIT                       (0x1UL << 4)                           /**< Intrapage hit only on incremental addresses */
    933. 

  933. #define _EBI_PAGECTRL_INCHIT_SHIFT                4                                      /**< Shift value for EBI_INCHIT */
    934. 

  934. #define _EBI_PAGECTRL_INCHIT_MASK                 0x10UL                                 /**< Bit mask for EBI_INCHIT */
    935. 

  935. #define _EBI_PAGECTRL_INCHIT_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for EBI_PAGECTRL */
    936. 

  936. #define EBI_PAGECTRL_INCHIT_DEFAULT               (_EBI_PAGECTRL_INCHIT_DEFAULT << 4)    /**< Shifted mode DEFAULT for EBI_PAGECTRL */
    937. 

  937. #define _EBI_PAGECTRL_RDPA_SHIFT                  8                                      /**< Shift value for EBI_RDPA */
    938. 

  938. #define _EBI_PAGECTRL_RDPA_MASK                   0x700UL                                /**< Bit mask for EBI_RDPA */
    939. 

  939. #define _EBI_PAGECTRL_RDPA_DEFAULT                0x00000007UL                           /**< Mode DEFAULT for EBI_PAGECTRL */
    940. 

  940. #define EBI_PAGECTRL_RDPA_DEFAULT                 (_EBI_PAGECTRL_RDPA_DEFAULT << 8)      /**< Shifted mode DEFAULT for EBI_PAGECTRL */
    941. 

  941. #define _EBI_PAGECTRL_KEEPOPEN_SHIFT              20                                     /**< Shift value for EBI_KEEPOPEN */
    942. 

  942. #define _EBI_PAGECTRL_KEEPOPEN_MASK               0x7F00000UL                            /**< Bit mask for EBI_KEEPOPEN */
    943. 

  943. #define _EBI_PAGECTRL_KEEPOPEN_DEFAULT            0x00000000UL                           /**< Mode DEFAULT for EBI_PAGECTRL */
    944. 

  944. #define EBI_PAGECTRL_KEEPOPEN_DEFAULT             (_EBI_PAGECTRL_KEEPOPEN_DEFAULT << 20) /**< Shifted mode DEFAULT for EBI_PAGECTRL */
    945. 

  945. 

  946. /* Bit fields for EBI NANDCTRL */
    947. 

  947. #define _EBI_NANDCTRL_RESETVALUE                  0x00000000UL                         /**< Default value for EBI_NANDCTRL */
    948. 

  948. #define _EBI_NANDCTRL_MASK                        0x00000031UL                         /**< Mask for EBI_NANDCTRL */
    949. 

  949. #define EBI_NANDCTRL_EN                           (0x1UL << 0)                         /**< NAND Flash control enable */
    950. 

  950. #define _EBI_NANDCTRL_EN_SHIFT                    0                                    /**< Shift value for EBI_EN */
    951. 

  951. #define _EBI_NANDCTRL_EN_MASK                     0x1UL                                /**< Bit mask for EBI_EN */
    952. 

  952. #define _EBI_NANDCTRL_EN_DEFAULT                  0x00000000UL                         /**< Mode DEFAULT for EBI_NANDCTRL */
    953. 

  953. #define EBI_NANDCTRL_EN_DEFAULT                   (_EBI_NANDCTRL_EN_DEFAULT << 0)      /**< Shifted mode DEFAULT for EBI_NANDCTRL */
    954. 

  954. #define _EBI_NANDCTRL_BANKSEL_SHIFT               4                                    /**< Shift value for EBI_BANKSEL */
    955. 

  955. #define _EBI_NANDCTRL_BANKSEL_MASK                0x30UL                               /**< Bit mask for EBI_BANKSEL */
    956. 

  956. #define _EBI_NANDCTRL_BANKSEL_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for EBI_NANDCTRL */
    957. 

  957. #define _EBI_NANDCTRL_BANKSEL_BANK0               0x00000000UL                         /**< Mode BANK0 for EBI_NANDCTRL */
    958. 

  958. #define _EBI_NANDCTRL_BANKSEL_BANK1               0x00000001UL                         /**< Mode BANK1 for EBI_NANDCTRL */
    959. 

  959. #define _EBI_NANDCTRL_BANKSEL_BANK2               0x00000002UL                         /**< Mode BANK2 for EBI_NANDCTRL */
    960. 

  960. #define _EBI_NANDCTRL_BANKSEL_BANK3               0x00000003UL                         /**< Mode BANK3 for EBI_NANDCTRL */
    961. 

  961. #define EBI_NANDCTRL_BANKSEL_DEFAULT              (_EBI_NANDCTRL_BANKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_NANDCTRL */
    962. 

  962. #define EBI_NANDCTRL_BANKSEL_BANK0                (_EBI_NANDCTRL_BANKSEL_BANK0 << 4)   /**< Shifted mode BANK0 for EBI_NANDCTRL */
    963. 

  963. #define EBI_NANDCTRL_BANKSEL_BANK1                (_EBI_NANDCTRL_BANKSEL_BANK1 << 4)   /**< Shifted mode BANK1 for EBI_NANDCTRL */
    964. 

  964. #define EBI_NANDCTRL_BANKSEL_BANK2                (_EBI_NANDCTRL_BANKSEL_BANK2 << 4)   /**< Shifted mode BANK2 for EBI_NANDCTRL */
    965. 

  965. #define EBI_NANDCTRL_BANKSEL_BANK3                (_EBI_NANDCTRL_BANKSEL_BANK3 << 4)   /**< Shifted mode BANK3 for EBI_NANDCTRL */
    966. 

  966. 

  967. /* Bit fields for EBI CMD */
    968. 

  968. #define _EBI_CMD_RESETVALUE                       0x00000000UL                     /**< Default value for EBI_CMD */
    969. 

  969. #define _EBI_CMD_MASK                             0x00000007UL                     /**< Mask for EBI_CMD */
    970. 

  970. #define EBI_CMD_ECCSTART                          (0x1UL << 0)                     /**< Error Correction Code Generation Start */
    971. 

  971. #define _EBI_CMD_ECCSTART_SHIFT                   0                                /**< Shift value for EBI_ECCSTART */
    972. 

  972. #define _EBI_CMD_ECCSTART_MASK                    0x1UL                            /**< Bit mask for EBI_ECCSTART */
    973. 

  973. #define _EBI_CMD_ECCSTART_DEFAULT                 0x00000000UL                     /**< Mode DEFAULT for EBI_CMD */
    974. 

  974. #define EBI_CMD_ECCSTART_DEFAULT                  (_EBI_CMD_ECCSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_CMD */
    975. 

  975. #define EBI_CMD_ECCSTOP                           (0x1UL << 1)                     /**< Error Correction Code Generation Stop */
    976. 

  976. #define _EBI_CMD_ECCSTOP_SHIFT                    1                                /**< Shift value for EBI_ECCSTOP */
    977. 

  977. #define _EBI_CMD_ECCSTOP_MASK                     0x2UL                            /**< Bit mask for EBI_ECCSTOP */
    978. 

  978. #define _EBI_CMD_ECCSTOP_DEFAULT                  0x00000000UL                     /**< Mode DEFAULT for EBI_CMD */
    979. 

  979. #define EBI_CMD_ECCSTOP_DEFAULT                   (_EBI_CMD_ECCSTOP_DEFAULT << 1)  /**< Shifted mode DEFAULT for EBI_CMD */
    980. 

  980. #define EBI_CMD_ECCCLEAR                          (0x1UL << 2)                     /**< Error Correction Code Clear */
    981. 

  981. #define _EBI_CMD_ECCCLEAR_SHIFT                   2                                /**< Shift value for EBI_ECCCLEAR */
    982. 

  982. #define _EBI_CMD_ECCCLEAR_MASK                    0x4UL                            /**< Bit mask for EBI_ECCCLEAR */
    983. 

  983. #define _EBI_CMD_ECCCLEAR_DEFAULT                 0x00000000UL                     /**< Mode DEFAULT for EBI_CMD */
    984. 

  984. #define EBI_CMD_ECCCLEAR_DEFAULT                  (_EBI_CMD_ECCCLEAR_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_CMD */
    985. 

  985. 

  986. /* Bit fields for EBI STATUS */
    987. 

  987. #define _EBI_STATUS_RESETVALUE                    0x00000000UL                              /**< Default value for EBI_STATUS */
    988. 

  988. #define _EBI_STATUS_MASK                          0x00003711UL                              /**< Mask for EBI_STATUS */
    989. 

  989. #define EBI_STATUS_AHBACT                         (0x1UL << 0)                              /**< EBI Busy with AHB Transaction. */
    990. 

  990. #define _EBI_STATUS_AHBACT_SHIFT                  0                                         /**< Shift value for EBI_AHBACT */
    991. 

  991. #define _EBI_STATUS_AHBACT_MASK                   0x1UL                                     /**< Bit mask for EBI_AHBACT */
    992. 

  992. #define _EBI_STATUS_AHBACT_DEFAULT                0x00000000UL                              /**< Mode DEFAULT for EBI_STATUS */
    993. 

  993. #define EBI_STATUS_AHBACT_DEFAULT                 (_EBI_STATUS_AHBACT_DEFAULT << 0)         /**< Shifted mode DEFAULT for EBI_STATUS */
    994. 

  994. #define EBI_STATUS_ECCACT                         (0x1UL << 4)                              /**< EBI ECC Generation Active. */
    995. 

  995. #define _EBI_STATUS_ECCACT_SHIFT                  4                                         /**< Shift value for EBI_ECCACT */
    996. 

  996. #define _EBI_STATUS_ECCACT_MASK                   0x10UL                                    /**< Bit mask for EBI_ECCACT */
    997. 

  997. #define _EBI_STATUS_ECCACT_DEFAULT                0x00000000UL                              /**< Mode DEFAULT for EBI_STATUS */
    998. 

  998. #define EBI_STATUS_ECCACT_DEFAULT                 (_EBI_STATUS_ECCACT_DEFAULT << 4)         /**< Shifted mode DEFAULT for EBI_STATUS */
    999. 

  999. #define EBI_STATUS_TFTPIXEL0EMPTY                 (0x1UL << 8)                              /**< EBI_TFTPIXEL0 is empty. */
    1000. 

  1000. #define _EBI_STATUS_TFTPIXEL0EMPTY_SHIFT          8                                         /**< Shift value for EBI_TFTPIXEL0EMPTY */
    1001. 

  1001. #define _EBI_STATUS_TFTPIXEL0EMPTY_MASK           0x100UL                                   /**< Bit mask for EBI_TFTPIXEL0EMPTY */
    1002. 

  1002. #define _EBI_STATUS_TFTPIXEL0EMPTY_DEFAULT        0x00000000UL                              /**< Mode DEFAULT for EBI_STATUS */
    1003. 

  1003. #define EBI_STATUS_TFTPIXEL0EMPTY_DEFAULT         (_EBI_STATUS_TFTPIXEL0EMPTY_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_STATUS */
    1004. 

  1004. #define EBI_STATUS_TFTPIXEL1EMPTY                 (0x1UL << 9)                              /**< EBI_TFTPIXEL1 is empty. */
    1005. 

  1005. #define _EBI_STATUS_TFTPIXEL1EMPTY_SHIFT          9                                         /**< Shift value for EBI_TFTPIXEL1EMPTY */
    1006. 

  1006. #define _EBI_STATUS_TFTPIXEL1EMPTY_MASK           0x200UL                                   /**< Bit mask for EBI_TFTPIXEL1EMPTY */
    1007. 

  1007. #define _EBI_STATUS_TFTPIXEL1EMPTY_DEFAULT        0x00000000UL                              /**< Mode DEFAULT for EBI_STATUS */
    1008. 

  1008. #define EBI_STATUS_TFTPIXEL1EMPTY_DEFAULT         (_EBI_STATUS_TFTPIXEL1EMPTY_DEFAULT << 9) /**< Shifted mode DEFAULT for EBI_STATUS */
    1009. 

  1009. #define EBI_STATUS_TFTPIXELFULL                   (0x1UL << 10)                             /**< EBI_TFTPIXEL0 is full. */
    1010. 

  1010. #define _EBI_STATUS_TFTPIXELFULL_SHIFT            10                                        /**< Shift value for EBI_TFTPIXELFULL */
    1011. 

  1011. #define _EBI_STATUS_TFTPIXELFULL_MASK             0x400UL                                   /**< Bit mask for EBI_TFTPIXELFULL */
    1012. 

  1012. #define _EBI_STATUS_TFTPIXELFULL_DEFAULT          0x00000000UL                              /**< Mode DEFAULT for EBI_STATUS */
    1013. 

  1013. #define EBI_STATUS_TFTPIXELFULL_DEFAULT           (_EBI_STATUS_TFTPIXELFULL_DEFAULT << 10)  /**< Shifted mode DEFAULT for EBI_STATUS */
    1014. 

  1014. #define EBI_STATUS_DDACT                          (0x1UL << 12)                             /**< EBI Busy with Direct Drive Transactions. */
    1015. 

  1015. #define _EBI_STATUS_DDACT_SHIFT                   12                                        /**< Shift value for EBI_DDACT */
    1016. 

  1016. #define _EBI_STATUS_DDACT_MASK                    0x1000UL                                  /**< Bit mask for EBI_DDACT */
    1017. 

  1017. #define _EBI_STATUS_DDACT_DEFAULT                 0x00000000UL                              /**< Mode DEFAULT for EBI_STATUS */
    1018. 

  1018. #define EBI_STATUS_DDACT_DEFAULT                  (_EBI_STATUS_DDACT_DEFAULT << 12)         /**< Shifted mode DEFAULT for EBI_STATUS */
    1019. 

  1019. #define EBI_STATUS_TFTDDEMPTY                     (0x1UL << 13)                             /**< EBI_TFTDD register is empty. */
    1020. 

  1020. #define _EBI_STATUS_TFTDDEMPTY_SHIFT              13                                        /**< Shift value for EBI_TFTDDEMPTY */
    1021. 

  1021. #define _EBI_STATUS_TFTDDEMPTY_MASK               0x2000UL                                  /**< Bit mask for EBI_TFTDDEMPTY */
    1022. 

  1022. #define _EBI_STATUS_TFTDDEMPTY_DEFAULT            0x00000000UL                              /**< Mode DEFAULT for EBI_STATUS */
    1023. 

  1023. #define EBI_STATUS_TFTDDEMPTY_DEFAULT             (_EBI_STATUS_TFTDDEMPTY_DEFAULT << 13)    /**< Shifted mode DEFAULT for EBI_STATUS */
    1024. 

  1024. 

  1025. /* Bit fields for EBI ECCPARITY */
    1026. 

  1026. #define _EBI_ECCPARITY_RESETVALUE                 0x00000000UL                            /**< Default value for EBI_ECCPARITY */
    1027. 

  1027. #define _EBI_ECCPARITY_MASK                       0xFFFFFFFFUL                            /**< Mask for EBI_ECCPARITY */
    1028. 

  1028. #define _EBI_ECCPARITY_ECCPARITY_SHIFT            0                                       /**< Shift value for EBI_ECCPARITY */
    1029. 

  1029. #define _EBI_ECCPARITY_ECCPARITY_MASK             0xFFFFFFFFUL                            /**< Bit mask for EBI_ECCPARITY */
    1030. 

  1030. #define _EBI_ECCPARITY_ECCPARITY_DEFAULT          0x00000000UL                            /**< Mode DEFAULT for EBI_ECCPARITY */
    1031. 

  1031. #define EBI_ECCPARITY_ECCPARITY_DEFAULT           (_EBI_ECCPARITY_ECCPARITY_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ECCPARITY */
    1032. 

  1032. 

  1033. /* Bit fields for EBI TFTCTRL */
    1034. 

  1034. #define _EBI_TFTCTRL_RESETVALUE                   0x00000000UL                               /**< Default value for EBI_TFTCTRL */
    1035. 

  1035. #define _EBI_TFTCTRL_MASK                         0x01311F1FUL                               /**< Mask for EBI_TFTCTRL */
    1036. 

  1036. #define _EBI_TFTCTRL_DD_SHIFT                     0                                          /**< Shift value for EBI_DD */
    1037. 

  1037. #define _EBI_TFTCTRL_DD_MASK                      0x3UL                                      /**< Bit mask for EBI_DD */
    1038. 

  1038. #define _EBI_TFTCTRL_DD_DEFAULT                   0x00000000UL                               /**< Mode DEFAULT for EBI_TFTCTRL */
    1039. 

  1039. #define _EBI_TFTCTRL_DD_DISABLED                  0x00000000UL                               /**< Mode DISABLED for EBI_TFTCTRL */
    1040. 

  1040. #define _EBI_TFTCTRL_DD_INTERNAL                  0x00000001UL                               /**< Mode INTERNAL for EBI_TFTCTRL */
    1041. 

  1041. #define _EBI_TFTCTRL_DD_EXTERNAL                  0x00000002UL                               /**< Mode EXTERNAL for EBI_TFTCTRL */
    1042. 

  1042. #define EBI_TFTCTRL_DD_DEFAULT                    (_EBI_TFTCTRL_DD_DEFAULT << 0)             /**< Shifted mode DEFAULT for EBI_TFTCTRL */
    1043. 

  1043. #define EBI_TFTCTRL_DD_DISABLED                   (_EBI_TFTCTRL_DD_DISABLED << 0)            /**< Shifted mode DISABLED for EBI_TFTCTRL */
    1044. 

  1044. #define EBI_TFTCTRL_DD_INTERNAL                   (_EBI_TFTCTRL_DD_INTERNAL << 0)            /**< Shifted mode INTERNAL for EBI_TFTCTRL */
    1045. 

  1045. #define EBI_TFTCTRL_DD_EXTERNAL                   (_EBI_TFTCTRL_DD_EXTERNAL << 0)            /**< Shifted mode EXTERNAL for EBI_TFTCTRL */
    1046. 

  1046. #define _EBI_TFTCTRL_MASKBLEND_SHIFT              2                                          /**< Shift value for EBI_MASKBLEND */
    1047. 

  1047. #define _EBI_TFTCTRL_MASKBLEND_MASK               0x1CUL                                     /**< Bit mask for EBI_MASKBLEND */
    1048. 

  1048. #define _EBI_TFTCTRL_MASKBLEND_DEFAULT            0x00000000UL                               /**< Mode DEFAULT for EBI_TFTCTRL */
    1049. 

  1049. #define _EBI_TFTCTRL_MASKBLEND_DISABLED           0x00000000UL                               /**< Mode DISABLED for EBI_TFTCTRL */
    1050. 

  1050. #define _EBI_TFTCTRL_MASKBLEND_IMASK              0x00000001UL                               /**< Mode IMASK for EBI_TFTCTRL */
    1051. 

  1051. #define _EBI_TFTCTRL_MASKBLEND_IALPHA             0x00000002UL                               /**< Mode IALPHA for EBI_TFTCTRL */
    1052. 

  1052. #define _EBI_TFTCTRL_MASKBLEND_IMASKIALPHA        0x00000003UL                               /**< Mode IMASKIALPHA for EBI_TFTCTRL */
    1053. 

  1053. #define _EBI_TFTCTRL_MASKBLEND_EMASK              0x00000005UL                               /**< Mode EMASK for EBI_TFTCTRL */
    1054. 

  1054. #define _EBI_TFTCTRL_MASKBLEND_EALPHA             0x00000006UL                               /**< Mode EALPHA for EBI_TFTCTRL */
    1055. 

  1055. #define _EBI_TFTCTRL_MASKBLEND_EMASKEALPHA        0x00000007UL                               /**< Mode EMASKEALPHA for EBI_TFTCTRL */
    1056. 

  1056. #define EBI_TFTCTRL_MASKBLEND_DEFAULT             (_EBI_TFTCTRL_MASKBLEND_DEFAULT << 2)      /**< Shifted mode DEFAULT for EBI_TFTCTRL */
    1057. 

  1057. #define EBI_TFTCTRL_MASKBLEND_DISABLED            (_EBI_TFTCTRL_MASKBLEND_DISABLED << 2)     /**< Shifted mode DISABLED for EBI_TFTCTRL */
    1058. 

  1058. #define EBI_TFTCTRL_MASKBLEND_IMASK               (_EBI_TFTCTRL_MASKBLEND_IMASK << 2)        /**< Shifted mode IMASK for EBI_TFTCTRL */
    1059. 

  1059. #define EBI_TFTCTRL_MASKBLEND_IALPHA              (_EBI_TFTCTRL_MASKBLEND_IALPHA << 2)       /**< Shifted mode IALPHA for EBI_TFTCTRL */
    1060. 

  1060. #define EBI_TFTCTRL_MASKBLEND_IMASKIALPHA         (_EBI_TFTCTRL_MASKBLEND_IMASKIALPHA << 2)  /**< Shifted mode IMASKIALPHA for EBI_TFTCTRL */
    1061. 

  1061. #define EBI_TFTCTRL_MASKBLEND_EMASK               (_EBI_TFTCTRL_MASKBLEND_EMASK << 2)        /**< Shifted mode EMASK for EBI_TFTCTRL */
    1062. 

  1062. #define EBI_TFTCTRL_MASKBLEND_EALPHA              (_EBI_TFTCTRL_MASKBLEND_EALPHA << 2)       /**< Shifted mode EALPHA for EBI_TFTCTRL */
    1063. 

  1063. #define EBI_TFTCTRL_MASKBLEND_EMASKEALPHA         (_EBI_TFTCTRL_MASKBLEND_EMASKEALPHA << 2)  /**< Shifted mode EMASKEALPHA for EBI_TFTCTRL */
    1064. 

  1064. #define EBI_TFTCTRL_SHIFTDCLKEN                   (0x1UL << 8)                               /**< TFT EBI_DCLK Shift Enable */
    1065. 

  1065. #define _EBI_TFTCTRL_SHIFTDCLKEN_SHIFT            8                                          /**< Shift value for EBI_SHIFTDCLKEN */
    1066. 

  1066. #define _EBI_TFTCTRL_SHIFTDCLKEN_MASK             0x100UL                                    /**< Bit mask for EBI_SHIFTDCLKEN */
    1067. 

  1067. #define _EBI_TFTCTRL_SHIFTDCLKEN_DEFAULT          0x00000000UL                               /**< Mode DEFAULT for EBI_TFTCTRL */
    1068. 

  1068. #define EBI_TFTCTRL_SHIFTDCLKEN_DEFAULT           (_EBI_TFTCTRL_SHIFTDCLKEN_DEFAULT << 8)    /**< Shifted mode DEFAULT for EBI_TFTCTRL */
    1069. 

  1069. #define EBI_TFTCTRL_FBCTRIG                       (0x1UL << 9)                               /**< TFT Frame Base Copy Trigger */
    1070. 

  1070. #define _EBI_TFTCTRL_FBCTRIG_SHIFT                9                                          /**< Shift value for EBI_FBCTRIG */
    1071. 

  1071. #define _EBI_TFTCTRL_FBCTRIG_MASK                 0x200UL                                    /**< Bit mask for EBI_FBCTRIG */
    1072. 

  1072. #define _EBI_TFTCTRL_FBCTRIG_DEFAULT              0x00000000UL                               /**< Mode DEFAULT for EBI_TFTCTRL */
    1073. 

  1073. #define _EBI_TFTCTRL_FBCTRIG_VSYNC                0x00000000UL                               /**< Mode VSYNC for EBI_TFTCTRL */
    1074. 

  1074. #define _EBI_TFTCTRL_FBCTRIG_HSYNC                0x00000001UL                               /**< Mode HSYNC for EBI_TFTCTRL */
    1075. 

  1075. #define EBI_TFTCTRL_FBCTRIG_DEFAULT               (_EBI_TFTCTRL_FBCTRIG_DEFAULT << 9)        /**< Shifted mode DEFAULT for EBI_TFTCTRL */
    1076. 

  1076. #define EBI_TFTCTRL_FBCTRIG_VSYNC                 (_EBI_TFTCTRL_FBCTRIG_VSYNC << 9)          /**< Shifted mode VSYNC for EBI_TFTCTRL */
    1077. 

  1077. #define EBI_TFTCTRL_FBCTRIG_HSYNC                 (_EBI_TFTCTRL_FBCTRIG_HSYNC << 9)          /**< Shifted mode HSYNC for EBI_TFTCTRL */
    1078. 

  1078. #define _EBI_TFTCTRL_INTERLEAVE_SHIFT             10                                         /**< Shift value for EBI_INTERLEAVE */
    1079. 

  1079. #define _EBI_TFTCTRL_INTERLEAVE_MASK              0xC00UL                                    /**< Bit mask for EBI_INTERLEAVE */
    1080. 

  1080. #define _EBI_TFTCTRL_INTERLEAVE_DEFAULT           0x00000000UL                               /**< Mode DEFAULT for EBI_TFTCTRL */
    1081. 

  1081. #define _EBI_TFTCTRL_INTERLEAVE_UNLIMITED         0x00000000UL                               /**< Mode UNLIMITED for EBI_TFTCTRL */
    1082. 

  1082. #define _EBI_TFTCTRL_INTERLEAVE_ONEPERDCLK        0x00000001UL                               /**< Mode ONEPERDCLK for EBI_TFTCTRL */
    1083. 

  1083. #define _EBI_TFTCTRL_INTERLEAVE_PORCH             0x00000002UL                               /**< Mode PORCH for EBI_TFTCTRL */
    1084. 

  1084. #define EBI_TFTCTRL_INTERLEAVE_DEFAULT            (_EBI_TFTCTRL_INTERLEAVE_DEFAULT << 10)    /**< Shifted mode DEFAULT for EBI_TFTCTRL */
    1085. 

  1085. #define EBI_TFTCTRL_INTERLEAVE_UNLIMITED          (_EBI_TFTCTRL_INTERLEAVE_UNLIMITED << 10)  /**< Shifted mode UNLIMITED for EBI_TFTCTRL */
    1086. 

  1086. #define EBI_TFTCTRL_INTERLEAVE_ONEPERDCLK         (_EBI_TFTCTRL_INTERLEAVE_ONEPERDCLK << 10) /**< Shifted mode ONEPERDCLK for EBI_TFTCTRL */
    1087. 

  1087. #define EBI_TFTCTRL_INTERLEAVE_PORCH              (_EBI_TFTCTRL_INTERLEAVE_PORCH << 10)      /**< Shifted mode PORCH for EBI_TFTCTRL */
    1088. 

  1088. #define EBI_TFTCTRL_COLOR1SRC                     (0x1UL << 12)                              /**< Masking/Alpha Blending Color1 Source */
    1089. 

  1089. #define _EBI_TFTCTRL_COLOR1SRC_SHIFT              12                                         /**< Shift value for EBI_COLOR1SRC */
    1090. 

  1090. #define _EBI_TFTCTRL_COLOR1SRC_MASK               0x1000UL                                   /**< Bit mask for EBI_COLOR1SRC */
    1091. 

  1091. #define _EBI_TFTCTRL_COLOR1SRC_DEFAULT            0x00000000UL                               /**< Mode DEFAULT for EBI_TFTCTRL */
    1092. 

  1092. #define _EBI_TFTCTRL_COLOR1SRC_MEM                0x00000000UL                               /**< Mode MEM for EBI_TFTCTRL */
    1093. 

  1093. #define _EBI_TFTCTRL_COLOR1SRC_PIXEL1             0x00000001UL                               /**< Mode PIXEL1 for EBI_TFTCTRL */
    1094. 

  1094. #define EBI_TFTCTRL_COLOR1SRC_DEFAULT             (_EBI_TFTCTRL_COLOR1SRC_DEFAULT << 12)     /**< Shifted mode DEFAULT for EBI_TFTCTRL */
    1095. 

  1095. #define EBI_TFTCTRL_COLOR1SRC_MEM                 (_EBI_TFTCTRL_COLOR1SRC_MEM << 12)         /**< Shifted mode MEM for EBI_TFTCTRL */
    1096. 

  1096. #define EBI_TFTCTRL_COLOR1SRC_PIXEL1              (_EBI_TFTCTRL_COLOR1SRC_PIXEL1 << 12)      /**< Shifted mode PIXEL1 for EBI_TFTCTRL */
    1097. 

  1097. #define EBI_TFTCTRL_WIDTH                         (0x1UL << 16)                              /**< TFT Transaction Width */
    1098. 

  1098. #define _EBI_TFTCTRL_WIDTH_SHIFT                  16                                         /**< Shift value for EBI_WIDTH */
    1099. 

  1099. #define _EBI_TFTCTRL_WIDTH_MASK                   0x10000UL                                  /**< Bit mask for EBI_WIDTH */
    1100. 

  1100. #define _EBI_TFTCTRL_WIDTH_DEFAULT                0x00000000UL                               /**< Mode DEFAULT for EBI_TFTCTRL */
    1101. 

  1101. #define _EBI_TFTCTRL_WIDTH_BYTE                   0x00000000UL                               /**< Mode BYTE for EBI_TFTCTRL */
    1102. 

  1102. #define _EBI_TFTCTRL_WIDTH_HALFWORD               0x00000001UL                               /**< Mode HALFWORD for EBI_TFTCTRL */
    1103. 

  1103. #define EBI_TFTCTRL_WIDTH_DEFAULT                 (_EBI_TFTCTRL_WIDTH_DEFAULT << 16)         /**< Shifted mode DEFAULT for EBI_TFTCTRL */
    1104. 

  1104. #define EBI_TFTCTRL_WIDTH_BYTE                    (_EBI_TFTCTRL_WIDTH_BYTE << 16)            /**< Shifted mode BYTE for EBI_TFTCTRL */
    1105. 

  1105. #define EBI_TFTCTRL_WIDTH_HALFWORD                (_EBI_TFTCTRL_WIDTH_HALFWORD << 16)        /**< Shifted mode HALFWORD for EBI_TFTCTRL */
    1106. 

  1106. #define _EBI_TFTCTRL_BANKSEL_SHIFT                20                                         /**< Shift value for EBI_BANKSEL */
    1107. 

  1107. #define _EBI_TFTCTRL_BANKSEL_MASK                 0x300000UL                                 /**< Bit mask for EBI_BANKSEL */
    1108. 

  1108. #define _EBI_TFTCTRL_BANKSEL_DEFAULT              0x00000000UL                               /**< Mode DEFAULT for EBI_TFTCTRL */
    1109. 

  1109. #define _EBI_TFTCTRL_BANKSEL_BANK0                0x00000000UL                               /**< Mode BANK0 for EBI_TFTCTRL */
    1110. 

  1110. #define _EBI_TFTCTRL_BANKSEL_BANK1                0x00000001UL                               /**< Mode BANK1 for EBI_TFTCTRL */
    1111. 

  1111. #define _EBI_TFTCTRL_BANKSEL_BANK2                0x00000002UL                               /**< Mode BANK2 for EBI_TFTCTRL */
    1112. 

  1112. #define _EBI_TFTCTRL_BANKSEL_BANK3                0x00000003UL                               /**< Mode BANK3 for EBI_TFTCTRL */
    1113. 

  1113. #define EBI_TFTCTRL_BANKSEL_DEFAULT               (_EBI_TFTCTRL_BANKSEL_DEFAULT << 20)       /**< Shifted mode DEFAULT for EBI_TFTCTRL */
    1114. 

  1114. #define EBI_TFTCTRL_BANKSEL_BANK0                 (_EBI_TFTCTRL_BANKSEL_BANK0 << 20)         /**< Shifted mode BANK0 for EBI_TFTCTRL */
    1115. 

  1115. #define EBI_TFTCTRL_BANKSEL_BANK1                 (_EBI_TFTCTRL_BANKSEL_BANK1 << 20)         /**< Shifted mode BANK1 for EBI_TFTCTRL */
    1116. 

  1116. #define EBI_TFTCTRL_BANKSEL_BANK2                 (_EBI_TFTCTRL_BANKSEL_BANK2 << 20)         /**< Shifted mode BANK2 for EBI_TFTCTRL */
    1117. 

  1117. #define EBI_TFTCTRL_BANKSEL_BANK3                 (_EBI_TFTCTRL_BANKSEL_BANK3 << 20)         /**< Shifted mode BANK3 for EBI_TFTCTRL */
    1118. 

  1118. #define EBI_TFTCTRL_RGBMODE                       (0x1UL << 24)                              /**< TFT RGB Mode */
    1119. 

  1119. #define _EBI_TFTCTRL_RGBMODE_SHIFT                24                                         /**< Shift value for EBI_RGBMODE */
    1120. 

  1120. #define _EBI_TFTCTRL_RGBMODE_MASK                 0x1000000UL                                /**< Bit mask for EBI_RGBMODE */
    1121. 

  1121. #define _EBI_TFTCTRL_RGBMODE_DEFAULT              0x00000000UL                               /**< Mode DEFAULT for EBI_TFTCTRL */
    1122. 

  1122. #define _EBI_TFTCTRL_RGBMODE_RGB565               0x00000000UL                               /**< Mode RGB565 for EBI_TFTCTRL */
    1123. 

  1123. #define _EBI_TFTCTRL_RGBMODE_RGB555               0x00000001UL                               /**< Mode RGB555 for EBI_TFTCTRL */
    1124. 

  1124. #define EBI_TFTCTRL_RGBMODE_DEFAULT               (_EBI_TFTCTRL_RGBMODE_DEFAULT << 24)       /**< Shifted mode DEFAULT for EBI_TFTCTRL */
    1125. 

  1125. #define EBI_TFTCTRL_RGBMODE_RGB565                (_EBI_TFTCTRL_RGBMODE_RGB565 << 24)        /**< Shifted mode RGB565 for EBI_TFTCTRL */
    1126. 

  1126. #define EBI_TFTCTRL_RGBMODE_RGB555                (_EBI_TFTCTRL_RGBMODE_RGB555 << 24)        /**< Shifted mode RGB555 for EBI_TFTCTRL */
    1127. 

  1127. 

  1128. /* Bit fields for EBI TFTSTATUS */
    1129. 

  1129. #define _EBI_TFTSTATUS_RESETVALUE                 0x00000000UL                        /**< Default value for EBI_TFTSTATUS */
    1130. 

  1130. #define _EBI_TFTSTATUS_MASK                       0x07FF07FFUL                        /**< Mask for EBI_TFTSTATUS */
    1131. 

  1131. #define _EBI_TFTSTATUS_HCNT_SHIFT                 0                                   /**< Shift value for EBI_HCNT */
    1132. 

  1132. #define _EBI_TFTSTATUS_HCNT_MASK                  0x7FFUL                             /**< Bit mask for EBI_HCNT */
    1133. 

  1133. #define _EBI_TFTSTATUS_HCNT_DEFAULT               0x00000000UL                        /**< Mode DEFAULT for EBI_TFTSTATUS */
    1134. 

  1134. #define EBI_TFTSTATUS_HCNT_DEFAULT                (_EBI_TFTSTATUS_HCNT_DEFAULT << 0)  /**< Shifted mode DEFAULT for EBI_TFTSTATUS */
    1135. 

  1135. #define _EBI_TFTSTATUS_VCNT_SHIFT                 16                                  /**< Shift value for EBI_VCNT */
    1136. 

  1136. #define _EBI_TFTSTATUS_VCNT_MASK                  0x7FF0000UL                         /**< Bit mask for EBI_VCNT */
    1137. 

  1137. #define _EBI_TFTSTATUS_VCNT_DEFAULT               0x00000000UL                        /**< Mode DEFAULT for EBI_TFTSTATUS */
    1138. 

  1138. #define EBI_TFTSTATUS_VCNT_DEFAULT                (_EBI_TFTSTATUS_VCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_TFTSTATUS */
    1139. 

  1139. 

  1140. /* Bit fields for EBI TFTFRAMEBASE */
    1141. 

  1141. #define _EBI_TFTFRAMEBASE_RESETVALUE              0x00000000UL                               /**< Default value for EBI_TFTFRAMEBASE */
    1142. 

  1142. #define _EBI_TFTFRAMEBASE_MASK                    0x0FFFFFFFUL                               /**< Mask for EBI_TFTFRAMEBASE */
    1143. 

  1143. #define _EBI_TFTFRAMEBASE_FRAMEBASE_SHIFT         0                                          /**< Shift value for EBI_FRAMEBASE */
    1144. 

  1144. #define _EBI_TFTFRAMEBASE_FRAMEBASE_MASK          0xFFFFFFFUL                                /**< Bit mask for EBI_FRAMEBASE */
    1145. 

  1145. #define _EBI_TFTFRAMEBASE_FRAMEBASE_DEFAULT       0x00000000UL                               /**< Mode DEFAULT for EBI_TFTFRAMEBASE */
    1146. 

  1146. #define EBI_TFTFRAMEBASE_FRAMEBASE_DEFAULT        (_EBI_TFTFRAMEBASE_FRAMEBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTFRAMEBASE */
    1147. 

  1147. 

  1148. /* Bit fields for EBI TFTSTRIDE */
    1149. 

  1149. #define _EBI_TFTSTRIDE_RESETVALUE                 0x00000000UL                          /**< Default value for EBI_TFTSTRIDE */
    1150. 

  1150. #define _EBI_TFTSTRIDE_MASK                       0x00000FFFUL                          /**< Mask for EBI_TFTSTRIDE */
    1151. 

  1151. #define _EBI_TFTSTRIDE_HSTRIDE_SHIFT              0                                     /**< Shift value for EBI_HSTRIDE */
    1152. 

  1152. #define _EBI_TFTSTRIDE_HSTRIDE_MASK               0xFFFUL                               /**< Bit mask for EBI_HSTRIDE */
    1153. 

  1153. #define _EBI_TFTSTRIDE_HSTRIDE_DEFAULT            0x00000000UL                          /**< Mode DEFAULT for EBI_TFTSTRIDE */
    1154. 

  1154. #define EBI_TFTSTRIDE_HSTRIDE_DEFAULT             (_EBI_TFTSTRIDE_HSTRIDE_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTSTRIDE */
    1155. 

  1155. 

  1156. /* Bit fields for EBI TFTSIZE */
    1157. 

  1157. #define _EBI_TFTSIZE_RESETVALUE                   0x00000000UL                     /**< Default value for EBI_TFTSIZE */
    1158. 

  1158. #define _EBI_TFTSIZE_MASK                         0x03FF03FFUL                     /**< Mask for EBI_TFTSIZE */
    1159. 

  1159. #define _EBI_TFTSIZE_HSZ_SHIFT                    0                                /**< Shift value for EBI_HSZ */
    1160. 

  1160. #define _EBI_TFTSIZE_HSZ_MASK                     0x3FFUL                          /**< Bit mask for EBI_HSZ */
    1161. 

  1161. #define _EBI_TFTSIZE_HSZ_DEFAULT                  0x00000000UL                     /**< Mode DEFAULT for EBI_TFTSIZE */
    1162. 

  1162. #define EBI_TFTSIZE_HSZ_DEFAULT                   (_EBI_TFTSIZE_HSZ_DEFAULT << 0)  /**< Shifted mode DEFAULT for EBI_TFTSIZE */
    1163. 

  1163. #define _EBI_TFTSIZE_VSZ_SHIFT                    16                               /**< Shift value for EBI_VSZ */
    1164. 

  1164. #define _EBI_TFTSIZE_VSZ_MASK                     0x3FF0000UL                      /**< Bit mask for EBI_VSZ */
    1165. 

  1165. #define _EBI_TFTSIZE_VSZ_DEFAULT                  0x00000000UL                     /**< Mode DEFAULT for EBI_TFTSIZE */
    1166. 

  1166. #define EBI_TFTSIZE_VSZ_DEFAULT                   (_EBI_TFTSIZE_VSZ_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_TFTSIZE */
    1167. 

  1167. 

  1168. /* Bit fields for EBI TFTHPORCH */
    1169. 

  1169. #define _EBI_TFTHPORCH_RESETVALUE                 0x00000000UL                              /**< Default value for EBI_TFTHPORCH */
    1170. 

  1170. #define _EBI_TFTHPORCH_MASK                       0x33FCFF7FUL                              /**< Mask for EBI_TFTHPORCH */
    1171. 

  1171. #define _EBI_TFTHPORCH_HSYNC_SHIFT                0                                         /**< Shift value for EBI_HSYNC */
    1172. 

  1172. #define _EBI_TFTHPORCH_HSYNC_MASK                 0x7FUL                                    /**< Bit mask for EBI_HSYNC */
    1173. 

  1173. #define _EBI_TFTHPORCH_HSYNC_DEFAULT              0x00000000UL                              /**< Mode DEFAULT for EBI_TFTHPORCH */
    1174. 

  1174. #define EBI_TFTHPORCH_HSYNC_DEFAULT               (_EBI_TFTHPORCH_HSYNC_DEFAULT << 0)       /**< Shifted mode DEFAULT for EBI_TFTHPORCH */
    1175. 

  1175. #define _EBI_TFTHPORCH_HFPORCH_SHIFT              8                                         /**< Shift value for EBI_HFPORCH */
    1176. 

  1176. #define _EBI_TFTHPORCH_HFPORCH_MASK               0xFF00UL                                  /**< Bit mask for EBI_HFPORCH */
    1177. 

  1177. #define _EBI_TFTHPORCH_HFPORCH_DEFAULT            0x00000000UL                              /**< Mode DEFAULT for EBI_TFTHPORCH */
    1178. 

  1178. #define EBI_TFTHPORCH_HFPORCH_DEFAULT             (_EBI_TFTHPORCH_HFPORCH_DEFAULT << 8)     /**< Shifted mode DEFAULT for EBI_TFTHPORCH */
    1179. 

  1179. #define _EBI_TFTHPORCH_HBPORCH_SHIFT              18                                        /**< Shift value for EBI_HBPORCH */
    1180. 

  1180. #define _EBI_TFTHPORCH_HBPORCH_MASK               0x3FC0000UL                               /**< Bit mask for EBI_HBPORCH */
    1181. 

  1181. #define _EBI_TFTHPORCH_HBPORCH_DEFAULT            0x00000000UL                              /**< Mode DEFAULT for EBI_TFTHPORCH */
    1182. 

  1182. #define EBI_TFTHPORCH_HBPORCH_DEFAULT             (_EBI_TFTHPORCH_HBPORCH_DEFAULT << 18)    /**< Shifted mode DEFAULT for EBI_TFTHPORCH */
    1183. 

  1183. #define _EBI_TFTHPORCH_HSYNCSTART_SHIFT           28                                        /**< Shift value for EBI_HSYNCSTART */
    1184. 

  1184. #define _EBI_TFTHPORCH_HSYNCSTART_MASK            0x30000000UL                              /**< Bit mask for EBI_HSYNCSTART */
    1185. 

  1185. #define _EBI_TFTHPORCH_HSYNCSTART_DEFAULT         0x00000000UL                              /**< Mode DEFAULT for EBI_TFTHPORCH */
    1186. 

  1186. #define EBI_TFTHPORCH_HSYNCSTART_DEFAULT          (_EBI_TFTHPORCH_HSYNCSTART_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_TFTHPORCH */
    1187. 

  1187. 

  1188. /* Bit fields for EBI TFTVPORCH */
    1189. 

  1189. #define _EBI_TFTVPORCH_RESETVALUE                 0x00000000UL                           /**< Default value for EBI_TFTVPORCH */
    1190. 

  1190. #define _EBI_TFTVPORCH_MASK                       0x03FCFF7FUL                           /**< Mask for EBI_TFTVPORCH */
    1191. 

  1191. #define _EBI_TFTVPORCH_VSYNC_SHIFT                0                                      /**< Shift value for EBI_VSYNC */
    1192. 

  1192. #define _EBI_TFTVPORCH_VSYNC_MASK                 0x7FUL                                 /**< Bit mask for EBI_VSYNC */
    1193. 

  1193. #define _EBI_TFTVPORCH_VSYNC_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for EBI_TFTVPORCH */
    1194. 

  1194. #define EBI_TFTVPORCH_VSYNC_DEFAULT               (_EBI_TFTVPORCH_VSYNC_DEFAULT << 0)    /**< Shifted mode DEFAULT for EBI_TFTVPORCH */
    1195. 

  1195. #define _EBI_TFTVPORCH_VFPORCH_SHIFT              8                                      /**< Shift value for EBI_VFPORCH */
    1196. 

  1196. #define _EBI_TFTVPORCH_VFPORCH_MASK               0xFF00UL                               /**< Bit mask for EBI_VFPORCH */
    1197. 

  1197. #define _EBI_TFTVPORCH_VFPORCH_DEFAULT            0x00000000UL                           /**< Mode DEFAULT for EBI_TFTVPORCH */
    1198. 

  1198. #define EBI_TFTVPORCH_VFPORCH_DEFAULT             (_EBI_TFTVPORCH_VFPORCH_DEFAULT << 8)  /**< Shifted mode DEFAULT for EBI_TFTVPORCH */
    1199. 

  1199. #define _EBI_TFTVPORCH_VBPORCH_SHIFT              18                                     /**< Shift value for EBI_VBPORCH */
    1200. 

  1200. #define _EBI_TFTVPORCH_VBPORCH_MASK               0x3FC0000UL                            /**< Bit mask for EBI_VBPORCH */
    1201. 

  1201. #define _EBI_TFTVPORCH_VBPORCH_DEFAULT            0x00000000UL                           /**< Mode DEFAULT for EBI_TFTVPORCH */
    1202. 

  1202. #define EBI_TFTVPORCH_VBPORCH_DEFAULT             (_EBI_TFTVPORCH_VBPORCH_DEFAULT << 18) /**< Shifted mode DEFAULT for EBI_TFTVPORCH */
    1203. 

  1203. 

  1204. /* Bit fields for EBI TFTTIMING */
    1205. 

  1205. #define _EBI_TFTTIMING_RESETVALUE                 0x00000000UL                             /**< Default value for EBI_TFTTIMING */
    1206. 

  1206. #define _EBI_TFTTIMING_MASK                       0x337FF7FFUL                             /**< Mask for EBI_TFTTIMING */
    1207. 

  1207. #define _EBI_TFTTIMING_DCLKPERIOD_SHIFT           0                                        /**< Shift value for EBI_DCLKPERIOD */
    1208. 

  1208. #define _EBI_TFTTIMING_DCLKPERIOD_MASK            0x7FFUL                                  /**< Bit mask for EBI_DCLKPERIOD */
    1209. 

  1209. #define _EBI_TFTTIMING_DCLKPERIOD_DEFAULT         0x00000000UL                             /**< Mode DEFAULT for EBI_TFTTIMING */
    1210. 

  1210. #define EBI_TFTTIMING_DCLKPERIOD_DEFAULT          (_EBI_TFTTIMING_DCLKPERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTTIMING */
    1211. 

  1211. #define _EBI_TFTTIMING_TFTSTART_SHIFT             12                                       /**< Shift value for EBI_TFTSTART */
    1212. 

  1212. #define _EBI_TFTTIMING_TFTSTART_MASK              0x7FF000UL                               /**< Bit mask for EBI_TFTSTART */
    1213. 

  1213. #define _EBI_TFTTIMING_TFTSTART_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for EBI_TFTTIMING */
    1214. 

  1214. #define EBI_TFTTIMING_TFTSTART_DEFAULT            (_EBI_TFTTIMING_TFTSTART_DEFAULT << 12)  /**< Shifted mode DEFAULT for EBI_TFTTIMING */
    1215. 

  1215. #define _EBI_TFTTIMING_TFTSETUP_SHIFT             24                                       /**< Shift value for EBI_TFTSETUP */
    1216. 

  1216. #define _EBI_TFTTIMING_TFTSETUP_MASK              0x3000000UL                              /**< Bit mask for EBI_TFTSETUP */
    1217. 

  1217. #define _EBI_TFTTIMING_TFTSETUP_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for EBI_TFTTIMING */
    1218. 

  1218. #define EBI_TFTTIMING_TFTSETUP_DEFAULT            (_EBI_TFTTIMING_TFTSETUP_DEFAULT << 24)  /**< Shifted mode DEFAULT for EBI_TFTTIMING */
    1219. 

  1219. #define _EBI_TFTTIMING_TFTHOLD_SHIFT              28                                       /**< Shift value for EBI_TFTHOLD */
    1220. 

  1220. #define _EBI_TFTTIMING_TFTHOLD_MASK               0x30000000UL                             /**< Bit mask for EBI_TFTHOLD */
    1221. 

  1221. #define _EBI_TFTTIMING_TFTHOLD_DEFAULT            0x00000000UL                             /**< Mode DEFAULT for EBI_TFTTIMING */
    1222. 

  1222. #define EBI_TFTTIMING_TFTHOLD_DEFAULT             (_EBI_TFTTIMING_TFTHOLD_DEFAULT << 28)   /**< Shifted mode DEFAULT for EBI_TFTTIMING */
    1223. 

  1223. 

  1224. /* Bit fields for EBI TFTPOLARITY */
    1225. 

  1225. #define _EBI_TFTPOLARITY_RESETVALUE               0x00000000UL                                  /**< Default value for EBI_TFTPOLARITY */
    1226. 

  1226. #define _EBI_TFTPOLARITY_MASK                     0x0000001FUL                                  /**< Mask for EBI_TFTPOLARITY */
    1227. 

  1227. #define EBI_TFTPOLARITY_CSPOL                     (0x1UL << 0)                                  /**< TFT Chip Select Polarity */
    1228. 

  1228. #define _EBI_TFTPOLARITY_CSPOL_SHIFT              0                                             /**< Shift value for EBI_CSPOL */
    1229. 

  1229. #define _EBI_TFTPOLARITY_CSPOL_MASK               0x1UL                                         /**< Bit mask for EBI_CSPOL */
    1230. 

  1230. #define _EBI_TFTPOLARITY_CSPOL_DEFAULT            0x00000000UL                                  /**< Mode DEFAULT for EBI_TFTPOLARITY */
    1231. 

  1231. #define _EBI_TFTPOLARITY_CSPOL_ACTIVELOW          0x00000000UL                                  /**< Mode ACTIVELOW for EBI_TFTPOLARITY */
    1232. 

  1232. #define _EBI_TFTPOLARITY_CSPOL_ACTIVEHIGH         0x00000001UL                                  /**< Mode ACTIVEHIGH for EBI_TFTPOLARITY */
    1233. 

  1233. #define EBI_TFTPOLARITY_CSPOL_DEFAULT             (_EBI_TFTPOLARITY_CSPOL_DEFAULT << 0)         /**< Shifted mode DEFAULT for EBI_TFTPOLARITY */
    1234. 

  1234. #define EBI_TFTPOLARITY_CSPOL_ACTIVELOW           (_EBI_TFTPOLARITY_CSPOL_ACTIVELOW << 0)       /**< Shifted mode ACTIVELOW for EBI_TFTPOLARITY */
    1235. 

  1235. #define EBI_TFTPOLARITY_CSPOL_ACTIVEHIGH          (_EBI_TFTPOLARITY_CSPOL_ACTIVEHIGH << 0)      /**< Shifted mode ACTIVEHIGH for EBI_TFTPOLARITY */
    1236. 

  1236. #define EBI_TFTPOLARITY_DCLKPOL                   (0x1UL << 1)                                  /**< TFT DCLK Polarity */
    1237. 

  1237. #define _EBI_TFTPOLARITY_DCLKPOL_SHIFT            1                                             /**< Shift value for EBI_DCLKPOL */
    1238. 

  1238. #define _EBI_TFTPOLARITY_DCLKPOL_MASK             0x2UL                                         /**< Bit mask for EBI_DCLKPOL */
    1239. 

  1239. #define _EBI_TFTPOLARITY_DCLKPOL_DEFAULT          0x00000000UL                                  /**< Mode DEFAULT for EBI_TFTPOLARITY */
    1240. 

  1240. #define _EBI_TFTPOLARITY_DCLKPOL_ACTIVEFALLING    0x00000000UL                                  /**< Mode ACTIVEFALLING for EBI_TFTPOLARITY */
    1241. 

  1241. #define _EBI_TFTPOLARITY_DCLKPOL_ACTIVERISING     0x00000001UL                                  /**< Mode ACTIVERISING for EBI_TFTPOLARITY */
    1242. 

  1242. #define EBI_TFTPOLARITY_DCLKPOL_DEFAULT           (_EBI_TFTPOLARITY_DCLKPOL_DEFAULT << 1)       /**< Shifted mode DEFAULT for EBI_TFTPOLARITY */
    1243. 

  1243. #define EBI_TFTPOLARITY_DCLKPOL_ACTIVEFALLING     (_EBI_TFTPOLARITY_DCLKPOL_ACTIVEFALLING << 1) /**< Shifted mode ACTIVEFALLING for EBI_TFTPOLARITY */
    1244. 

  1244. #define EBI_TFTPOLARITY_DCLKPOL_ACTIVERISING      (_EBI_TFTPOLARITY_DCLKPOL_ACTIVERISING << 1)  /**< Shifted mode ACTIVERISING for EBI_TFTPOLARITY */
    1245. 

  1245. #define EBI_TFTPOLARITY_DATAENPOL                 (0x1UL << 2)                                  /**< TFT DATAEN Polarity */
    1246. 

  1246. #define _EBI_TFTPOLARITY_DATAENPOL_SHIFT          2                                             /**< Shift value for EBI_DATAENPOL */
    1247. 

  1247. #define _EBI_TFTPOLARITY_DATAENPOL_MASK           0x4UL                                         /**< Bit mask for EBI_DATAENPOL */
    1248. 

  1248. #define _EBI_TFTPOLARITY_DATAENPOL_DEFAULT        0x00000000UL                                  /**< Mode DEFAULT for EBI_TFTPOLARITY */
    1249. 

  1249. #define _EBI_TFTPOLARITY_DATAENPOL_ACTIVELOW      0x00000000UL                                  /**< Mode ACTIVELOW for EBI_TFTPOLARITY */
    1250. 

  1250. #define _EBI_TFTPOLARITY_DATAENPOL_ACTIVEHIGH     0x00000001UL                                  /**< Mode ACTIVEHIGH for EBI_TFTPOLARITY */
    1251. 

  1251. #define EBI_TFTPOLARITY_DATAENPOL_DEFAULT         (_EBI_TFTPOLARITY_DATAENPOL_DEFAULT << 2)     /**< Shifted mode DEFAULT for EBI_TFTPOLARITY */
    1252. 

  1252. #define EBI_TFTPOLARITY_DATAENPOL_ACTIVELOW       (_EBI_TFTPOLARITY_DATAENPOL_ACTIVELOW << 2)   /**< Shifted mode ACTIVELOW for EBI_TFTPOLARITY */
    1253. 

  1253. #define EBI_TFTPOLARITY_DATAENPOL_ACTIVEHIGH      (_EBI_TFTPOLARITY_DATAENPOL_ACTIVEHIGH << 2)  /**< Shifted mode ACTIVEHIGH for EBI_TFTPOLARITY */
    1254. 

  1254. #define EBI_TFTPOLARITY_HSYNCPOL                  (0x1UL << 3)                                  /**< Address Latch Polarity */
    1255. 

  1255. #define _EBI_TFTPOLARITY_HSYNCPOL_SHIFT           3                                             /**< Shift value for EBI_HSYNCPOL */
    1256. 

  1256. #define _EBI_TFTPOLARITY_HSYNCPOL_MASK            0x8UL                                         /**< Bit mask for EBI_HSYNCPOL */
    1257. 

  1257. #define _EBI_TFTPOLARITY_HSYNCPOL_DEFAULT         0x00000000UL                                  /**< Mode DEFAULT for EBI_TFTPOLARITY */
    1258. 

  1258. #define _EBI_TFTPOLARITY_HSYNCPOL_ACTIVELOW       0x00000000UL                                  /**< Mode ACTIVELOW for EBI_TFTPOLARITY */
    1259. 

  1259. #define _EBI_TFTPOLARITY_HSYNCPOL_ACTIVEHIGH      0x00000001UL                                  /**< Mode ACTIVEHIGH for EBI_TFTPOLARITY */
    1260. 

  1260. #define EBI_TFTPOLARITY_HSYNCPOL_DEFAULT          (_EBI_TFTPOLARITY_HSYNCPOL_DEFAULT << 3)      /**< Shifted mode DEFAULT for EBI_TFTPOLARITY */
    1261. 

  1261. #define EBI_TFTPOLARITY_HSYNCPOL_ACTIVELOW        (_EBI_TFTPOLARITY_HSYNCPOL_ACTIVELOW << 3)    /**< Shifted mode ACTIVELOW for EBI_TFTPOLARITY */
    1262. 

  1262. #define EBI_TFTPOLARITY_HSYNCPOL_ACTIVEHIGH       (_EBI_TFTPOLARITY_HSYNCPOL_ACTIVEHIGH << 3)   /**< Shifted mode ACTIVEHIGH for EBI_TFTPOLARITY */
    1263. 

  1263. #define EBI_TFTPOLARITY_VSYNCPOL                  (0x1UL << 4)                                  /**< VSYNC Polarity */
    1264. 

  1264. #define _EBI_TFTPOLARITY_VSYNCPOL_SHIFT           4                                             /**< Shift value for EBI_VSYNCPOL */
    1265. 

  1265. #define _EBI_TFTPOLARITY_VSYNCPOL_MASK            0x10UL                                        /**< Bit mask for EBI_VSYNCPOL */
    1266. 

  1266. #define _EBI_TFTPOLARITY_VSYNCPOL_DEFAULT         0x00000000UL                                  /**< Mode DEFAULT for EBI_TFTPOLARITY */
    1267. 

  1267. #define _EBI_TFTPOLARITY_VSYNCPOL_ACTIVELOW       0x00000000UL                                  /**< Mode ACTIVELOW for EBI_TFTPOLARITY */
    1268. 

  1268. #define _EBI_TFTPOLARITY_VSYNCPOL_ACTIVEHIGH      0x00000001UL                                  /**< Mode ACTIVEHIGH for EBI_TFTPOLARITY */
    1269. 

  1269. #define EBI_TFTPOLARITY_VSYNCPOL_DEFAULT          (_EBI_TFTPOLARITY_VSYNCPOL_DEFAULT << 4)      /**< Shifted mode DEFAULT for EBI_TFTPOLARITY */
    1270. 

  1270. #define EBI_TFTPOLARITY_VSYNCPOL_ACTIVELOW        (_EBI_TFTPOLARITY_VSYNCPOL_ACTIVELOW << 4)    /**< Shifted mode ACTIVELOW for EBI_TFTPOLARITY */
    1271. 

  1271. #define EBI_TFTPOLARITY_VSYNCPOL_ACTIVEHIGH       (_EBI_TFTPOLARITY_VSYNCPOL_ACTIVEHIGH << 4)   /**< Shifted mode ACTIVEHIGH for EBI_TFTPOLARITY */
    1272. 

  1272. 

  1273. /* Bit fields for EBI TFTDD */
    1274. 

  1274. #define _EBI_TFTDD_RESETVALUE                     0x00000000UL                   /**< Default value for EBI_TFTDD */
    1275. 

  1275. #define _EBI_TFTDD_MASK                           0x0000FFFFUL                   /**< Mask for EBI_TFTDD */
    1276. 

  1276. #define _EBI_TFTDD_DATA_SHIFT                     0                              /**< Shift value for EBI_DATA */
    1277. 

  1277. #define _EBI_TFTDD_DATA_MASK                      0xFFFFUL                       /**< Bit mask for EBI_DATA */
    1278. 

  1278. #define _EBI_TFTDD_DATA_DEFAULT                   0x00000000UL                   /**< Mode DEFAULT for EBI_TFTDD */
    1279. 

  1279. #define EBI_TFTDD_DATA_DEFAULT                    (_EBI_TFTDD_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTDD */
    1280. 

  1280. 

  1281. /* Bit fields for EBI TFTALPHA */
    1282. 

  1282. #define _EBI_TFTALPHA_RESETVALUE                  0x00000000UL                       /**< Default value for EBI_TFTALPHA */
    1283. 

  1283. #define _EBI_TFTALPHA_MASK                        0x000001FFUL                       /**< Mask for EBI_TFTALPHA */
    1284. 

  1284. #define _EBI_TFTALPHA_ALPHA_SHIFT                 0                                  /**< Shift value for EBI_ALPHA */
    1285. 

  1285. #define _EBI_TFTALPHA_ALPHA_MASK                  0x1FFUL                            /**< Bit mask for EBI_ALPHA */
    1286. 

  1286. #define _EBI_TFTALPHA_ALPHA_DEFAULT               0x00000000UL                       /**< Mode DEFAULT for EBI_TFTALPHA */
    1287. 

  1287. #define EBI_TFTALPHA_ALPHA_DEFAULT                (_EBI_TFTALPHA_ALPHA_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTALPHA */
    1288. 

  1288. 

  1289. /* Bit fields for EBI TFTPIXEL0 */
    1290. 

  1290. #define _EBI_TFTPIXEL0_RESETVALUE                 0x00000000UL                       /**< Default value for EBI_TFTPIXEL0 */
    1291. 

  1291. #define _EBI_TFTPIXEL0_MASK                       0x0000FFFFUL                       /**< Mask for EBI_TFTPIXEL0 */
    1292. 

  1292. #define _EBI_TFTPIXEL0_DATA_SHIFT                 0                                  /**< Shift value for EBI_DATA */
    1293. 

  1293. #define _EBI_TFTPIXEL0_DATA_MASK                  0xFFFFUL                           /**< Bit mask for EBI_DATA */
    1294. 

  1294. #define _EBI_TFTPIXEL0_DATA_DEFAULT               0x00000000UL                       /**< Mode DEFAULT for EBI_TFTPIXEL0 */
    1295. 

  1295. #define EBI_TFTPIXEL0_DATA_DEFAULT                (_EBI_TFTPIXEL0_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTPIXEL0 */
    1296. 

  1296. 

  1297. /* Bit fields for EBI TFTPIXEL1 */
    1298. 

  1298. #define _EBI_TFTPIXEL1_RESETVALUE                 0x00000000UL                       /**< Default value for EBI_TFTPIXEL1 */
    1299. 

  1299. #define _EBI_TFTPIXEL1_MASK                       0x0000FFFFUL                       /**< Mask for EBI_TFTPIXEL1 */
    1300. 

  1300. #define _EBI_TFTPIXEL1_DATA_SHIFT                 0                                  /**< Shift value for EBI_DATA */
    1301. 

  1301. #define _EBI_TFTPIXEL1_DATA_MASK                  0xFFFFUL                           /**< Bit mask for EBI_DATA */
    1302. 

  1302. #define _EBI_TFTPIXEL1_DATA_DEFAULT               0x00000000UL                       /**< Mode DEFAULT for EBI_TFTPIXEL1 */
    1303. 

  1303. #define EBI_TFTPIXEL1_DATA_DEFAULT                (_EBI_TFTPIXEL1_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTPIXEL1 */
    1304. 

  1304. 

  1305. /* Bit fields for EBI TFTPIXEL */
    1306. 

  1306. #define _EBI_TFTPIXEL_RESETVALUE                  0x00000000UL                      /**< Default value for EBI_TFTPIXEL */
    1307. 

  1307. #define _EBI_TFTPIXEL_MASK                        0x0000FFFFUL                      /**< Mask for EBI_TFTPIXEL */
    1308. 

  1308. #define _EBI_TFTPIXEL_DATA_SHIFT                  0                                 /**< Shift value for EBI_DATA */
    1309. 

  1309. #define _EBI_TFTPIXEL_DATA_MASK                   0xFFFFUL                          /**< Bit mask for EBI_DATA */
    1310. 

  1310. #define _EBI_TFTPIXEL_DATA_DEFAULT                0x00000000UL                      /**< Mode DEFAULT for EBI_TFTPIXEL */
    1311. 

  1311. #define EBI_TFTPIXEL_DATA_DEFAULT                 (_EBI_TFTPIXEL_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTPIXEL */
    1312. 

  1312. 

  1313. /* Bit fields for EBI TFTMASK */
    1314. 

  1314. #define _EBI_TFTMASK_RESETVALUE                   0x00000000UL                        /**< Default value for EBI_TFTMASK */
    1315. 

  1315. #define _EBI_TFTMASK_MASK                         0x0000FFFFUL                        /**< Mask for EBI_TFTMASK */
    1316. 

  1316. #define _EBI_TFTMASK_TFTMASK_SHIFT                0                                   /**< Shift value for EBI_TFTMASK */
    1317. 

  1317. #define _EBI_TFTMASK_TFTMASK_MASK                 0xFFFFUL                            /**< Bit mask for EBI_TFTMASK */
    1318. 

  1318. #define _EBI_TFTMASK_TFTMASK_DEFAULT              0x00000000UL                        /**< Mode DEFAULT for EBI_TFTMASK */
    1319. 

  1319. #define EBI_TFTMASK_TFTMASK_DEFAULT               (_EBI_TFTMASK_TFTMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTMASK */
    1320. 

  1320. 

  1321. /* Bit fields for EBI IF */
    1322. 

  1322. #define _EBI_IF_RESETVALUE                        0x00000000UL                   /**< Default value for EBI_IF */
    1323. 

  1323. #define _EBI_IF_MASK                              0x0000003FUL                   /**< Mask for EBI_IF */
    1324. 

  1324. #define EBI_IF_VSYNC                              (0x1UL << 0)                   /**< Vertical Sync Interrupt Flag */
    1325. 

  1325. #define _EBI_IF_VSYNC_SHIFT                       0                              /**< Shift value for EBI_VSYNC */
    1326. 

  1326. #define _EBI_IF_VSYNC_MASK                        0x1UL                          /**< Bit mask for EBI_VSYNC */
    1327. 

  1327. #define _EBI_IF_VSYNC_DEFAULT                     0x00000000UL                   /**< Mode DEFAULT for EBI_IF */
    1328. 

  1328. #define EBI_IF_VSYNC_DEFAULT                      (_EBI_IF_VSYNC_DEFAULT << 0)   /**< Shifted mode DEFAULT for EBI_IF */
    1329. 

  1329. #define EBI_IF_HSYNC                              (0x1UL << 1)                   /**< Horizontal Sync Interrupt Flag */
    1330. 

  1330. #define _EBI_IF_HSYNC_SHIFT                       1                              /**< Shift value for EBI_HSYNC */
    1331. 

  1331. #define _EBI_IF_HSYNC_MASK                        0x2UL                          /**< Bit mask for EBI_HSYNC */
    1332. 

  1332. #define _EBI_IF_HSYNC_DEFAULT                     0x00000000UL                   /**< Mode DEFAULT for EBI_IF */
    1333. 

  1333. #define EBI_IF_HSYNC_DEFAULT                      (_EBI_IF_HSYNC_DEFAULT << 1)   /**< Shifted mode DEFAULT for EBI_IF */
    1334. 

  1334. #define EBI_IF_VBPORCH                            (0x1UL << 2)                   /**< Vertical Back Porch Interrupt Flag */
    1335. 

  1335. #define _EBI_IF_VBPORCH_SHIFT                     2                              /**< Shift value for EBI_VBPORCH */
    1336. 

  1336. #define _EBI_IF_VBPORCH_MASK                      0x4UL                          /**< Bit mask for EBI_VBPORCH */
    1337. 

  1337. #define _EBI_IF_VBPORCH_DEFAULT                   0x00000000UL                   /**< Mode DEFAULT for EBI_IF */
    1338. 

  1338. #define EBI_IF_VBPORCH_DEFAULT                    (_EBI_IF_VBPORCH_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_IF */
    1339. 

  1339. #define EBI_IF_VFPORCH                            (0x1UL << 3)                   /**< Vertical Front Porch Interrupt Flag */
    1340. 

  1340. #define _EBI_IF_VFPORCH_SHIFT                     3                              /**< Shift value for EBI_VFPORCH */
    1341. 

  1341. #define _EBI_IF_VFPORCH_MASK                      0x8UL                          /**< Bit mask for EBI_VFPORCH */
    1342. 

  1342. #define _EBI_IF_VFPORCH_DEFAULT                   0x00000000UL                   /**< Mode DEFAULT for EBI_IF */
    1343. 

  1343. #define EBI_IF_VFPORCH_DEFAULT                    (_EBI_IF_VFPORCH_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_IF */
    1344. 

  1344. #define EBI_IF_DDEMPTY                            (0x1UL << 4)                   /**< Direct Drive Data Empty Interrupt Flag */
    1345. 

  1345. #define _EBI_IF_DDEMPTY_SHIFT                     4                              /**< Shift value for EBI_DDEMPTY */
    1346. 

  1346. #define _EBI_IF_DDEMPTY_MASK                      0x10UL                         /**< Bit mask for EBI_DDEMPTY */
    1347. 

  1347. #define _EBI_IF_DDEMPTY_DEFAULT                   0x00000000UL                   /**< Mode DEFAULT for EBI_IF */
    1348. 

  1348. #define EBI_IF_DDEMPTY_DEFAULT                    (_EBI_IF_DDEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_IF */
    1349. 

  1349. #define EBI_IF_DDJIT                              (0x1UL << 5)                   /**< Direct Drive Jitter Interrupt Flag */
    1350. 

  1350. #define _EBI_IF_DDJIT_SHIFT                       5                              /**< Shift value for EBI_DDJIT */
    1351. 

  1351. #define _EBI_IF_DDJIT_MASK                        0x20UL                         /**< Bit mask for EBI_DDJIT */
    1352. 

  1352. #define _EBI_IF_DDJIT_DEFAULT                     0x00000000UL                   /**< Mode DEFAULT for EBI_IF */
    1353. 

  1353. #define EBI_IF_DDJIT_DEFAULT                      (_EBI_IF_DDJIT_DEFAULT << 5)   /**< Shifted mode DEFAULT for EBI_IF */
    1354. 

  1354. 

  1355. /* Bit fields for EBI IFS */
    1356. 

  1356. #define _EBI_IFS_RESETVALUE                       0x00000000UL                    /**< Default value for EBI_IFS */
    1357. 

  1357. #define _EBI_IFS_MASK                             0x0000003FUL                    /**< Mask for EBI_IFS */
    1358. 

  1358. #define EBI_IFS_VSYNC                             (0x1UL << 0)                    /**< Vertical Sync Interrupt Flag Set */
    1359. 

  1359. #define _EBI_IFS_VSYNC_SHIFT                      0                               /**< Shift value for EBI_VSYNC */
    1360. 

  1360. #define _EBI_IFS_VSYNC_MASK                       0x1UL                           /**< Bit mask for EBI_VSYNC */
    1361. 

  1361. #define _EBI_IFS_VSYNC_DEFAULT                    0x00000000UL                    /**< Mode DEFAULT for EBI_IFS */
    1362. 

  1362. #define EBI_IFS_VSYNC_DEFAULT                     (_EBI_IFS_VSYNC_DEFAULT << 0)   /**< Shifted mode DEFAULT for EBI_IFS */
    1363. 

  1363. #define EBI_IFS_HSYNC                             (0x1UL << 1)                    /**< Horizontal Sync Interrupt Flag Set */
    1364. 

  1364. #define _EBI_IFS_HSYNC_SHIFT                      1                               /**< Shift value for EBI_HSYNC */
    1365. 

  1365. #define _EBI_IFS_HSYNC_MASK                       0x2UL                           /**< Bit mask for EBI_HSYNC */
    1366. 

  1366. #define _EBI_IFS_HSYNC_DEFAULT                    0x00000000UL                    /**< Mode DEFAULT for EBI_IFS */
    1367. 

  1367. #define EBI_IFS_HSYNC_DEFAULT                     (_EBI_IFS_HSYNC_DEFAULT << 1)   /**< Shifted mode DEFAULT for EBI_IFS */
    1368. 

  1368. #define EBI_IFS_VBPORCH                           (0x1UL << 2)                    /**< Vertical Back Porch Interrupt Flag Set */
    1369. 

  1369. #define _EBI_IFS_VBPORCH_SHIFT                    2                               /**< Shift value for EBI_VBPORCH */
    1370. 

  1370. #define _EBI_IFS_VBPORCH_MASK                     0x4UL                           /**< Bit mask for EBI_VBPORCH */
    1371. 

  1371. #define _EBI_IFS_VBPORCH_DEFAULT                  0x00000000UL                    /**< Mode DEFAULT for EBI_IFS */
    1372. 

  1372. #define EBI_IFS_VBPORCH_DEFAULT                   (_EBI_IFS_VBPORCH_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_IFS */
    1373. 

  1373. #define EBI_IFS_VFPORCH                           (0x1UL << 3)                    /**< Vertical Front Porch Interrupt Flag Set */
    1374. 

  1374. #define _EBI_IFS_VFPORCH_SHIFT                    3                               /**< Shift value for EBI_VFPORCH */
    1375. 

  1375. #define _EBI_IFS_VFPORCH_MASK                     0x8UL                           /**< Bit mask for EBI_VFPORCH */
    1376. 

  1376. #define _EBI_IFS_VFPORCH_DEFAULT                  0x00000000UL                    /**< Mode DEFAULT for EBI_IFS */
    1377. 

  1377. #define EBI_IFS_VFPORCH_DEFAULT                   (_EBI_IFS_VFPORCH_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_IFS */
    1378. 

  1378. #define EBI_IFS_DDEMPTY                           (0x1UL << 4)                    /**< Direct Drive Data Empty Interrupt Flag Set */
    1379. 

  1379. #define _EBI_IFS_DDEMPTY_SHIFT                    4                               /**< Shift value for EBI_DDEMPTY */
    1380. 

  1380. #define _EBI_IFS_DDEMPTY_MASK                     0x10UL                          /**< Bit mask for EBI_DDEMPTY */
    1381. 

  1381. #define _EBI_IFS_DDEMPTY_DEFAULT                  0x00000000UL                    /**< Mode DEFAULT for EBI_IFS */
    1382. 

  1382. #define EBI_IFS_DDEMPTY_DEFAULT                   (_EBI_IFS_DDEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_IFS */
    1383. 

  1383. #define EBI_IFS_DDJIT                             (0x1UL << 5)                    /**< Direct Drive Jitter Interrupt Flag Set */
    1384. 

  1384. #define _EBI_IFS_DDJIT_SHIFT                      5                               /**< Shift value for EBI_DDJIT */
    1385. 

  1385. #define _EBI_IFS_DDJIT_MASK                       0x20UL                          /**< Bit mask for EBI_DDJIT */
    1386. 

  1386. #define _EBI_IFS_DDJIT_DEFAULT                    0x00000000UL                    /**< Mode DEFAULT for EBI_IFS */
    1387. 

  1387. #define EBI_IFS_DDJIT_DEFAULT                     (_EBI_IFS_DDJIT_DEFAULT << 5)   /**< Shifted mode DEFAULT for EBI_IFS */
    1388. 

  1388. 

  1389. /* Bit fields for EBI IFC */
    1390. 

  1390. #define _EBI_IFC_RESETVALUE                       0x00000000UL                    /**< Default value for EBI_IFC */
    1391. 

  1391. #define _EBI_IFC_MASK                             0x0000003FUL                    /**< Mask for EBI_IFC */
    1392. 

  1392. #define EBI_IFC_VSYNC                             (0x1UL << 0)                    /**< Vertical Sync Interrupt Flag Clear */
    1393. 

  1393. #define _EBI_IFC_VSYNC_SHIFT                      0                               /**< Shift value for EBI_VSYNC */
    1394. 

  1394. #define _EBI_IFC_VSYNC_MASK                       0x1UL                           /**< Bit mask for EBI_VSYNC */
    1395. 

  1395. #define _EBI_IFC_VSYNC_DEFAULT                    0x00000000UL                    /**< Mode DEFAULT for EBI_IFC */
    1396. 

  1396. #define EBI_IFC_VSYNC_DEFAULT                     (_EBI_IFC_VSYNC_DEFAULT << 0)   /**< Shifted mode DEFAULT for EBI_IFC */
    1397. 

  1397. #define EBI_IFC_HSYNC                             (0x1UL << 1)                    /**< Horizontal Sync Interrupt Flag Clear */
    1398. 

  1398. #define _EBI_IFC_HSYNC_SHIFT                      1                               /**< Shift value for EBI_HSYNC */
    1399. 

  1399. #define _EBI_IFC_HSYNC_MASK                       0x2UL                           /**< Bit mask for EBI_HSYNC */
    1400. 

  1400. #define _EBI_IFC_HSYNC_DEFAULT                    0x00000000UL                    /**< Mode DEFAULT for EBI_IFC */
    1401. 

  1401. #define EBI_IFC_HSYNC_DEFAULT                     (_EBI_IFC_HSYNC_DEFAULT << 1)   /**< Shifted mode DEFAULT for EBI_IFC */
    1402. 

  1402. #define EBI_IFC_VBPORCH                           (0x1UL << 2)                    /**< Vertical Back Porch Interrupt Flag Clear */
    1403. 

  1403. #define _EBI_IFC_VBPORCH_SHIFT                    2                               /**< Shift value for EBI_VBPORCH */
    1404. 

  1404. #define _EBI_IFC_VBPORCH_MASK                     0x4UL                           /**< Bit mask for EBI_VBPORCH */
    1405. 

  1405. #define _EBI_IFC_VBPORCH_DEFAULT                  0x00000000UL                    /**< Mode DEFAULT for EBI_IFC */
    1406. 

  1406. #define EBI_IFC_VBPORCH_DEFAULT                   (_EBI_IFC_VBPORCH_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_IFC */
    1407. 

  1407. #define EBI_IFC_VFPORCH                           (0x1UL << 3)                    /**< Vertical Front Porch Interrupt Flag Clear */
    1408. 

  1408. #define _EBI_IFC_VFPORCH_SHIFT                    3                               /**< Shift value for EBI_VFPORCH */
    1409. 

  1409. #define _EBI_IFC_VFPORCH_MASK                     0x8UL                           /**< Bit mask for EBI_VFPORCH */
    1410. 

  1410. #define _EBI_IFC_VFPORCH_DEFAULT                  0x00000000UL                    /**< Mode DEFAULT for EBI_IFC */
    1411. 

  1411. #define EBI_IFC_VFPORCH_DEFAULT                   (_EBI_IFC_VFPORCH_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_IFC */
    1412. 

  1412. #define EBI_IFC_DDEMPTY                           (0x1UL << 4)                    /**< Direct Drive Data Empty Interrupt Flag Clear */
    1413. 

  1413. #define _EBI_IFC_DDEMPTY_SHIFT                    4                               /**< Shift value for EBI_DDEMPTY */
    1414. 

  1414. #define _EBI_IFC_DDEMPTY_MASK                     0x10UL                          /**< Bit mask for EBI_DDEMPTY */
    1415. 

  1415. #define _EBI_IFC_DDEMPTY_DEFAULT                  0x00000000UL                    /**< Mode DEFAULT for EBI_IFC */
    1416. 

  1416. #define EBI_IFC_DDEMPTY_DEFAULT                   (_EBI_IFC_DDEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_IFC */
    1417. 

  1417. #define EBI_IFC_DDJIT                             (0x1UL << 5)                    /**< Direct Drive Jitter Interrupt Flag Clear */
    1418. 

  1418. #define _EBI_IFC_DDJIT_SHIFT                      5                               /**< Shift value for EBI_DDJIT */
    1419. 

  1419. #define _EBI_IFC_DDJIT_MASK                       0x20UL                          /**< Bit mask for EBI_DDJIT */
    1420. 

  1420. #define _EBI_IFC_DDJIT_DEFAULT                    0x00000000UL                    /**< Mode DEFAULT for EBI_IFC */
    1421. 

  1421. #define EBI_IFC_DDJIT_DEFAULT                     (_EBI_IFC_DDJIT_DEFAULT << 5)   /**< Shifted mode DEFAULT for EBI_IFC */
    1422. 

  1422. 

  1423. /* Bit fields for EBI IEN */
    1424. 

  1424. #define _EBI_IEN_RESETVALUE                       0x00000000UL                    /**< Default value for EBI_IEN */
    1425. 

  1425. #define _EBI_IEN_MASK                             0x0000003FUL                    /**< Mask for EBI_IEN */
    1426. 

  1426. #define EBI_IEN_VSYNC                             (0x1UL << 0)                    /**< Vertical Sync Interrupt Enable */
    1427. 

  1427. #define _EBI_IEN_VSYNC_SHIFT                      0                               /**< Shift value for EBI_VSYNC */
    1428. 

  1428. #define _EBI_IEN_VSYNC_MASK                       0x1UL                           /**< Bit mask for EBI_VSYNC */
    1429. 

  1429. #define _EBI_IEN_VSYNC_DEFAULT                    0x00000000UL                    /**< Mode DEFAULT for EBI_IEN */
    1430. 

  1430. #define EBI_IEN_VSYNC_DEFAULT                     (_EBI_IEN_VSYNC_DEFAULT << 0)   /**< Shifted mode DEFAULT for EBI_IEN */
    1431. 

  1431. #define EBI_IEN_HSYNC                             (0x1UL << 1)                    /**< Horizontal Sync Interrupt Enable */
    1432. 

  1432. #define _EBI_IEN_HSYNC_SHIFT                      1                               /**< Shift value for EBI_HSYNC */
    1433. 

  1433. #define _EBI_IEN_HSYNC_MASK                       0x2UL                           /**< Bit mask for EBI_HSYNC */
    1434. 

  1434. #define _EBI_IEN_HSYNC_DEFAULT                    0x00000000UL                    /**< Mode DEFAULT for EBI_IEN */
    1435. 

  1435. #define EBI_IEN_HSYNC_DEFAULT                     (_EBI_IEN_HSYNC_DEFAULT << 1)   /**< Shifted mode DEFAULT for EBI_IEN */
    1436. 

  1436. #define EBI_IEN_VBPORCH                           (0x1UL << 2)                    /**< Vertical Back Porch Interrupt Enable */
    1437. 

  1437. #define _EBI_IEN_VBPORCH_SHIFT                    2                               /**< Shift value for EBI_VBPORCH */
    1438. 

  1438. #define _EBI_IEN_VBPORCH_MASK                     0x4UL                           /**< Bit mask for EBI_VBPORCH */
    1439. 

  1439. #define _EBI_IEN_VBPORCH_DEFAULT                  0x00000000UL                    /**< Mode DEFAULT for EBI_IEN */
    1440. 

  1440. #define EBI_IEN_VBPORCH_DEFAULT                   (_EBI_IEN_VBPORCH_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_IEN */
    1441. 

  1441. #define EBI_IEN_VFPORCH                           (0x1UL << 3)                    /**< Vertical Front Porch Interrupt Enable */
    1442. 

  1442. #define _EBI_IEN_VFPORCH_SHIFT                    3                               /**< Shift value for EBI_VFPORCH */
    1443. 

  1443. #define _EBI_IEN_VFPORCH_MASK                     0x8UL                           /**< Bit mask for EBI_VFPORCH */
    1444. 

  1444. #define _EBI_IEN_VFPORCH_DEFAULT                  0x00000000UL                    /**< Mode DEFAULT for EBI_IEN */
    1445. 

  1445. #define EBI_IEN_VFPORCH_DEFAULT                   (_EBI_IEN_VFPORCH_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_IEN */
    1446. 

  1446. #define EBI_IEN_DDEMPTY                           (0x1UL << 4)                    /**< Direct Drive Data Empty Interrupt Enable */
    1447. 

  1447. #define _EBI_IEN_DDEMPTY_SHIFT                    4                               /**< Shift value for EBI_DDEMPTY */
    1448. 

  1448. #define _EBI_IEN_DDEMPTY_MASK                     0x10UL                          /**< Bit mask for EBI_DDEMPTY */
    1449. 

  1449. #define _EBI_IEN_DDEMPTY_DEFAULT                  0x00000000UL                    /**< Mode DEFAULT for EBI_IEN */
    1450. 

  1450. #define EBI_IEN_DDEMPTY_DEFAULT                   (_EBI_IEN_DDEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_IEN */
    1451. 

  1451. #define EBI_IEN_DDJIT                             (0x1UL << 5)                    /**< Direct Drive Jitter Interrupt Enable */
    1452. 

  1452. #define _EBI_IEN_DDJIT_SHIFT                      5                               /**< Shift value for EBI_DDJIT */
    1453. 

  1453. #define _EBI_IEN_DDJIT_MASK                       0x20UL                          /**< Bit mask for EBI_DDJIT */
    1454. 

  1454. #define _EBI_IEN_DDJIT_DEFAULT                    0x00000000UL                    /**< Mode DEFAULT for EBI_IEN */
    1455. 

  1455. #define EBI_IEN_DDJIT_DEFAULT                     (_EBI_IEN_DDJIT_DEFAULT << 5)   /**< Shifted mode DEFAULT for EBI_IEN */
    1456. 

  1456. 

  1457. /** @} End of group EFM32GG_EBI */
    1458. 

  1458. 

  1459.