Inicio Explorar Ayuda
Registro Iniciar sesión
lqb
/
rt-thread
espejo de https://gitee.com/rtthread/rt-thread.git
1
0
Fork 0
Archivos Incidencias 0 Wiki
Rama: stable-v2.0.x
Ramas Etiquetas
rt-thread
/
bsp
/
rx
/
RPDL
/
r_pdl_cgc.h

r_pdl_cgc.h 1.4 KB
Permalink Histórico Raw

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364 
  1. /*""FILE COMMENT""*******************************************************
    2. 

  2. * System Name	: CGC API
    3. 

  3. * File Name		: r_pdl_cgc.h
    4. 

  4. * Version		: 1.02
    5. 

  5. * Contents		: CGC header
    6. 

  6. * Customer		:
    7. 

  7. * Model			:
    8. 

  8. * Order			:
    9. 

  9. * CPU			: RX
    10. 

  10. * Compiler		: RXC
    11. 

  11. * OS			:
    12. 

  12. * Programmer	:
    13. 

  13. * Note			:
    14. 

  14. ************************************************************************
    15. 

  15. * Copyright, 2011. Renesas Electronics Corporation
    16. 

  16. * and Renesas Solutions Corporation
    17. 

  17. ************************************************************************
    18. 

  18. * History		: 2011.04.08
    19. 

  19. *				: Ver 1.02
    20. 

  20. *				: CS-5 release.
    21. 

  21. *""FILE COMMENT END""**************************************************/
    22. 

  22. 

  23. #ifndef R_PDL_CGC_H
    24. 

  24. #define R_PDL_CGC_H
    25. 

  25. 

  26. #include "r_pdl_common_defs_RX62Nxx.h"
    27. 

  27. 

  28. /* Function prototypes */
    29. 

  29. bool R_CGC_Set(
    30. 

  30. 	uint32_t,
    31. 

  31. 	uint32_t,
    32. 

  32. 	uint32_t,
    33. 

  33. 	uint32_t,
    34. 

  34. 	uint16_t
    35. 

  35. );
    36. 

  36. 

  37. bool R_CGC_Control(
    38. 

  38. 	uint16_t
    39. 

  39. );
    40. 

  40. 

  41. bool R_CGC_GetStatus(
    42. 

  42. 	uint8_t *
    43. 

  43. );
    44. 

  44. 

  45. /* BCLK pin putput control */
    46. 

  46. #define PDL_CGC_BCLK_DISABLE		0x0001u
    47. 

  47. #define PDL_CGC_BCLK_DIV_1			0x0002u
    48. 

  48. #define PDL_CGC_BCLK_DIV_2			0x0004u
    49. 

  49. #define PDL_CGC_BCLK_HIGH			0x0008u
    50. 

  50. 

  51. /* SDCLK pin putput control */
    52. 

  52. #define PDL_CGC_SDCLK_DISABLE		0x0010u
    53. 

  53. #define PDL_CGC_SDCLK_ENABLE		0x0020u
    54. 

  54. 

  55. /* Oscillation Stop Detection control */
    56. 

  56. #define PDL_CGC_OSC_STOP_ENABLE		0x0040u
    57. 

  57. #define PDL_CGC_OSC_STOP_DISABLE	0x0080u
    58. 

  58. 

  59. /* Sub-clock oscillator control */
    60. 

  60. #define PDL_CGC_SUB_CLOCK_ENABLE	0x0100u
    61. 

  61. #define PDL_CGC_SUB_CLOCK_DISABLE	0x0200u
    62. 

  62. 

  63. #endif
    64. 

  64. /* End of file */
    65.