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GD32F30x_usbfs_driver
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usb_regs.h

usb_regs.h 43 KB
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  1. /*!
    2. 

  2.     \file  usb_regs.h
    3. 

  3.     \brief USB FS cell registers definition and handle macros
    4. 

  4. */
    5. 

  5. 

  6. /*
    7. 

  7.     Copyright (C) 2017 GigaDevice
    8. 

  8. 

  9.     2017-02-10, V1.0.0, firmware for GD32F30x
    10. 

  10. */
    11. 

  11. 

  12. #ifndef USB_REGS_H
    13. 

  13. #define USB_REGS_H
    14. 

  14. 

  15. #include "usb_conf.h"
    16. 

  16. 

  17. #define USBFS                     USBFS_BASE                              /*!< base address of USBFS registers */
    18. 

  18. 

  19. /* registers location definitions */
    20. 

  20. #define LOCATE_DIEPTFLEN(x)       (0x104U + 4U * ((x) - 1U))              /*!< locate device IN endpoint-x transfer length registers */
    21. 

  21. #define LOCATE_HCHCTL(x)          (0x500U + 0x20U * (x))                  /*!< locate host channel-x control registers */
    22. 

  22. #define LOCATE_HCHSTCTL(x)        (0x504U + 0x20U * (x))                  /*!< locate host channel-x split transaction control registers */
    23. 

  23. #define LOCATE_HCHINTF(x)         (0x508U + 0x20U * (x))                  /*!< locate host channel-x interrupt flag registers */
    24. 

  24. #define LOCATE_HCHINTEN(x)        (0x50CU + 0x20U * (x))                  /*!< locate host channel-x interrupt enable registers */
    25. 

  25. #define LOCATE_HCHLEN(x)          (0x510U + 0x20U * (x))                  /*!< locate host channel-x transfer length registers */
    26. 

  26. #define LOCATE_HCHDMAADDR(x)      (0x514U + 0x20U * (x))                  /*!< locate host channel-x DMA address registers */
    27. 

  27. #define LOCATE_DIEPCTL(x)         (0x900U + 0x20U * (x))                  /*!< locate device IN endpoint-x control registers */
    28. 

  28. #define LOCATE_DOEPCTL(x)         (0xB00U + 0x20U * (x))                  /*!< locate device OUT endpoint-x control registers */
    29. 

  29. #define LOCATE_DIEPINTF(x)        (0x908U + 0x20U * (x))                  /*!< locate device IN endpoint-x interrupt flag registers */
    30. 

  30. #define LOCATE_DOEPINTF(x)        (0xB08U + 0x20U * (x))                  /*!< locate device OUT endpoint-x interrupt flag registers */
    31. 

  31. #define LOCATE_DIEPLEN(x)         (0x910U + 0x20U * (x))                  /*!< locate device IN endpoint-x transfer length registers */
    32. 

  32. #define LOCATE_DOEPLEN(x)         (0xB10U + 0x20U * (x))                  /*!< locate device OUT endpoint-x transfer length registers */
    33. 

  33. #define LOCATE_DIEPxDMAADDR(x)    (0x914U + 0x20U * (x))                  /*!< locate device IN endpoint-x DMA address registers */
    34. 

  34. #define LOCATE_DOEPxDMAADDR(x)    (0xB14U + 0x20U * (x))                  /*!< locate device OUT endpoint-x DMA address registers */
    35. 

  35. #define LOCATE_DIEPxTFSTAT(x)     (0x918U + 0x20U * (x))                  /*!< locate Device IN endpoint-x transmit FIFO status register */
    36. 

  36. #define LOCATE_FIFO(x)            (((x) + 1U) << 12U)                     /*!< locate FIFO-x memory */
    37. 

  37. 

  38. /* registers definitions */
    39. 

  39. #define USB_GOTGCS                REG32(((USBFS) + 0x0000U))               /*!< global OTG control and status register */
    40. 

  40. #define USB_GOTGINTF              REG32(((USBFS) + 0x0004U))               /*!< global OTG interrupt flag register */
    41. 

  41. #define USB_GAHBCS                REG32(((USBFS) + 0x0008U))               /*!< global AHB control and status register */
    42. 

  42. #define USB_GUSBCS                REG32(((USBFS) + 0x000CU))               /*!< global USB control and status register */
    43. 

  43. #define USB_GRSTCTL               REG32(((USBFS) + 0x0010U))               /*!< global reset control register */
    44. 

  44. #define USB_GINTF                 REG32(((USBFS) + 0x0014U))               /*!< global interrupt flag register */
    45. 

  45. #define USB_GINTEN                REG32(((USBFS) + 0x0018U))               /*!< global interrupt enable register */
    46. 

  46. #define USB_GRSTATR               REG32(((USBFS) + 0x001CU))               /*!< global receive status read register */
    47. 

  47. #define USB_GRSTATP               REG32(((USBFS) + 0x0020U))               /*!< global receive status read and pop register */
    48. 

  48. #define USB_GRFLEN                REG32(((USBFS) + 0x0024U))               /*!< global receive FIFO length register */
    49. 

  49. #define USB_HNPTFLEN              REG32(((USBFS) + 0x0028U))               /*!< host non-periodic transmit FIFO length register */
    50. 

  50. #define USB_DIEP0TFLEN            REG32(((USBFS) + 0x0028U))               /*!< device IN endpoint 0 transmit FIFO length register */
    51. 

  51. #define USB_HNPTFQSTAT            REG32(((USBFS) + 0x002CU))               /*!< host non-periodic transmint FIFO/queue status register */
    52. 

  52. #define USB_GCCFG                 REG32(((USBFS) + 0x0038U))               /*!< global core configuration register */
    53. 

  53. #define USB_CID                   REG32(((USBFS) + 0x003CU))               /*!< core id register */
    54. 

  54. #define USB_HPTFLEN               REG32(((USBFS) + 0x0100U))               /*!< host periodic transmit FIFO length register */
    55. 

  55. #define USB_DIEPxTFLEN(x)         REG32(((USBFS) + LOCATE_DIEPTFLEN(x)))   /*!< device IN endpoint transmit FIFO length register */
    56. 

  56. 

  57. #define USB_HCTL                  REG32(((USBFS) + 0x0400U))               /*!< host control register */
    58. 

  58. #define USB_HFT                   REG32(((USBFS) + 0x0404U))               /*!< host frame interval register */
    59. 

  59. #define USB_HFINFR                REG32(((USBFS) + 0x0408U))               /*!< host frame information remaining register */
    60. 

  60. #define USB_HPTFQSTAT             REG32(((USBFS) + 0x0410U))               /*!< host periodic transmit FIFO/queue status register */
    61. 

  61. #define USB_HACHINT               REG32(((USBFS) + 0x0414U))               /*!< host all channels interrupt register */
    62. 

  62. #define USB_HACHINTEN             REG32(((USBFS) + 0x0418U))               /*!< host all channels interrupt enable register */
    63. 

  63. #define USB_HPCS                  REG32(((USBFS) + 0x0440U))               /*!< host port control and status register */
    64. 

  64. #define USB_HCHxCTL(x)            REG32(((USBFS) + LOCATE_HCHCTL(x)))      /*!< host channel-x control register */
    65. 

  65. #define USB_HCHxSTCTL(x)          REG32(((USBFS) + LOCATE_HCHSTCTL(x)))    /*!< host channel-x split transaction control register */
    66. 

  66. #define USB_HCHxINTF(x)           REG32(((USBFS) + LOCATE_HCHINTF(x)))     /*!< host channel-x interrupt flag register */
    67. 

  67. #define USB_HCHxINTEN(x)          REG32(((USBFS) + LOCATE_HCHINTEN(x)))    /*!< host channel-x interrupt enable register */
    68. 

  68. #define USB_HCHxLEN(x)            REG32(((USBFS) + LOCATE_HCHLEN(x)))      /*!< host channel-x tranfer length register */
    69. 

  69. #define USB_HCHxDMAADDR(x)        REG32(((USBFS) + LOCATE_HCHDMAADDR(x)))  /*!< host channel-x DMA address register */
    70. 

  70. 

  71. #define USB_DCFG                  REG32(((USBFS) + 0x0800U))               /*!< device configuration register */
    72. 

  72. #define USB_DCTL                  REG32(((USBFS) + 0x0804U))               /*!< device control register */
    73. 

  73. #define USB_DSTAT                 REG32(((USBFS) + 0x0808U))               /*!< device status register */
    74. 

  74. #define USB_DIEPINTEN             REG32(((USBFS) + 0x0810U))               /*!< device IN endpoint common interrupt enable register */
    75. 

  75. #define USB_DOEPINTEN             REG32(((USBFS) + 0x0814U))               /*!< device OUT endpoint common interrupt enable register */
    76. 

  76. #define USB_DAEPINT               REG32(((USBFS) + 0x0818U))               /*!< device all endpoints interrupt register */
    77. 

  77. #define USB_DAEPINTEN             REG32(((USBFS) + 0x081CU))               /*!< device all endpoints interrupt enable register */
    78. 

  78. #define USB_DVBUSDT               REG32(((USBFS) + 0x0828U))               /*!< device vbus discharge time register */
    79. 

  79. #define USB_DVBUSPT               REG32(((USBFS) + 0x082CU))               /*!< device vbus pulsing time register */
    80. 

  80. #define USB_DIEPFEINTEN           REG32(((USBFS) + 0x0834U))               /*!< device IN endpoint FIFO empty interrupt enable register */
    81. 

  81. #define USB_DEP1INT               REG32(((USBFS) + 0x0838U))               /*!< device endpoint 1 interrupt register */
    82. 

  82. #define USB_DEP1INTEN             REG32(((USBFS) + 0x083CU))               /*!< device endpoint 1 interrupt enable register */
    83. 

  83. #define USB_DIEP1INTEN            REG32(((USBFS) + 0x0844U))               /*!< device IN endpoint 1 interrupt enable register */
    84. 

  84. #define USB_DOEP1INTEN            REG32(((USBFS) + 0x0884U))               /*!< device OUT endpoint 1 interrupt enable register */
    85. 

  85. #define USB_DIEP0CTL              REG32(((USBFS) + 0x0900U))               /*!< device IN endpoint 0 control register */
    86. 

  86. #define USB_DIEP0LEN              REG32(((USBFS) + 0x0910U))               /*!< device IN endpoint 0 transfer length register */
    87. 

  87. #define USB_DOEP0CTL              REG32(((USBFS) + 0x0B00U))               /*!< device OUT endpoint 0 control register */
    88. 

  88. #define USB_DOEP0LEN              REG32(((USBFS) + 0x0B10U))               /*!< device OUT endpoint 0 transfer length register */
    89. 

  89. #define USB_DIEPxCTL(x)           REG32(((USBFS) + LOCATE_DIEPCTL(x)))     /*!< device IN endpoint-x control register */
    90. 

  90. #define USB_DOEPxCTL(x)           REG32(((USBFS) + LOCATE_DOEPCTL(x)))     /*!< device OUT endpoint-x control register */
    91. 

  91. #define USB_DIEPxINTF(x)          REG32(((USBFS) + LOCATE_DIEPINTF(x)))    /*!< device IN endpoint-x interrupt flag register */
    92. 

  92. #define USB_DOEPxINTF(x)          REG32(((USBFS) + LOCATE_DOEPINTF(x)))    /*!< device OUT endpoint-x interrupt flag register */
    93. 

  93. #define USB_DIEPxLEN(x)           REG32(((USBFS) + LOCATE_DIEPLEN(x)))     /*!< device IN endpoint-x transfer length register */
    94. 

  94. #define USB_DOEPxLEN(x)           REG32(((USBFS) + LOCATE_DOEPLEN(x)))     /*!< device OUT endpoint-x transfer length register */
    95. 

  95. #define USB_DIEPxDMAADDR(x)       REG32(((USBFS) + LOCATE_DIEPxDMAADDR(x)))/*!< device IN endpoint-x DMA address register */
    96. 

  96. #define USB_DOEPxDMAADDR(x)       REG32(((USBFS) + LOCATE_DOEPxDMAADDR(x)))/*!< device OUT endpoint-x DMA address register */
    97. 

  97. #define USB_DIEPxTFSTAT(x)        REG32(((USBFS) + LOCATE_DIEPxTFSTAT(x))) /*!< device IN endpoint-x transmit FIFO status register */
    98. 

  98. 

  99. #define USB_PWRCLKCTL             REG32(((USBFS) + 0x0E00U))               /*!< power and clock register */
    100. 

  100. 

  101. #define USB_FIFO(x)               (&REG32(((USBFS) + LOCATE_FIFO(x))))     /*!< FIFO memory */
    102. 

  102. 

  103. /* global OTG control and status register bits definitions */
    104. 

  104. #define GOTGCS_BSV                BIT(19)             /*!< B-Session Valid */
    105. 

  105. #define GOTGCS_ASV                BIT(18)             /*!< A-session valid */
    106. 

  106. #define GOTGCS_DI                 BIT(17)             /*!< debounce interval */
    107. 

  107. #define GOTGCS_CIDPS              BIT(16)             /*!< id pin status */
    108. 

  108. #define GOTGCS_DHNPEN             BIT(11)             /*!< device HNP enable */
    109. 

  109. #define GOTGCS_HHNPEN             BIT(10)             /*!< host HNP enable */
    110. 

  110. #define GOTGCS_HNPREQ             BIT(9)              /*!< HNP request */
    111. 

  111. #define GOTGCS_HNPS               BIT(8)              /*!< HNP successes */
    112. 

  112. #define GOTGCS_SRPREQ             BIT(1)              /*!< SRP request */
    113. 

  113. #define GOTGCS_SRPS               BIT(0)              /*!< SRP successes */
    114. 

  114. 

  115. /* global OTG interrupt flag register bits definitions */
    116. 

  116. #define GOTGINTF_DF               BIT(19)             /*!< debounce finish */
    117. 

  117. #define GOTGINTF_ADTO             BIT(18)             /*!< A-device timeout */
    118. 

  118. #define GOTGINTF_HNPDET           BIT(17)             /*!< host negotiation request detected */
    119. 

  119. #define GOTGINTF_HNPEND           BIT(9)              /*!< HNP end */
    120. 

  120. #define GOTGINTF_SRPEND           BIT(8)              /*!< SRP end */
    121. 

  121. #define GOTGINTF_SESEND           BIT(2)              /*!< session end */
    122. 

  122. 

  123. /* global AHB control and status register bits definitions */
    124. 

  124. #define GAHBCS_PTXFTH             BIT(8)              /*!< periodic Tx FIFO threshold */
    125. 

  125. #define GAHBCS_TXFTH              BIT(7)              /*!< tx FIFO threshold */
    126. 

  126. #define GAHBCS_DMAEN              BIT(5)              /*!< DMA function Enable */
    127. 

  127. #define GAHBCS_BURST              BITS(1, 4)          /*!< the AHB burst type used by DMA */
    128. 

  128. #define GAHBCS_GINTEN             BIT(0)              /*!< global interrupt enable */
    129. 

  129. 

  130. /* global USB control and status register bits definitions */
    131. 

  131. #define GUSBCS_FDM                BIT(30)             /*!< force device mode */
    132. 

  132. #define GUSBCS_FHM                BIT(29)             /*!< force host mode */
    133. 

  133. #define GUSBCS_ULPIEOI            BIT(21)             /*!< ULPI external over-current indicator */
    134. 

  134. #define GUSBCS_ULPIEVD            BIT(20)             /*!< ULPI external VBUS driver */
    135. 

  135. #define GUSBCS_UTT                BITS(10, 13)        /*!< USB turnaround time */
    136. 

  136. #define GUSBCS_HNPCEN             BIT(9)              /*!< HNP capability enable */
    137. 

  137. #define GUSBCS_SRPCEN             BIT(8)              /*!< SRP capability enable */
    138. 

  138. #define GUSBCS_EMBPHY             BIT(6)              /*!< embedded PHY selected */
    139. 

  139. #define GUSBCS_TOC                BITS(0, 2)          /*!< timeout calibration */
    140. 

  140. 

  141. /* global reset control register bits definitions */
    142. 

  142. #define GRSTCTL_DMAIDL            BIT(31)             /*!< DMA idle state */
    143. 

  143. #define GRSTCTL_DMABSY            BIT(30)             /*!< DMA busy */
    144. 

  144. #define GRSTCTL_TXFNUM            BITS(6, 10)         /*!< tx FIFO number */
    145. 

  145. #define GRSTCTL_TXFF              BIT(5)              /*!< tx FIFO flush */
    146. 

  146. #define GRSTCTL_RXFF              BIT(4)              /*!< rx FIFO flush */
    147. 

  147. #define GRSTCTL_HFCRST            BIT(2)              /*!< host frame counter reset */
    148. 

  148. #define GRSTCTL_HCSRST            BIT(1)              /*!< HCLK soft reset */
    149. 

  149. #define GRSTCTL_CSRST             BIT(0)              /*!< core soft reset */
    150. 

  150. 

  151. /* global interrupt flag register bits definitions */
    152. 

  152. #define GINTF_WKUPIF              BIT(31)             /*!< wakeup interrupt flag */
    153. 

  153. #define GINTF_SESIF               BIT(30)             /*!< session interrupt flag */
    154. 

  154. #define GINTF_DISCIF              BIT(29)             /*!< disconnect interrupt flag */
    155. 

  155. #define GINTF_IDPSC               BIT(28)             /*!< id pin status change */
    156. 

  156. #define GINTF_PTXFEIF             BIT(26)             /*!< periodic tx FIFO empty interrupt flag */
    157. 

  157. #define GINTF_HCIF                BIT(25)             /*!< host channels interrupt flag */
    158. 

  158. #define GINTF_HPIF                BIT(24)             /*!< host port interrupt flag */
    159. 

  159. #define GINTF_PXNCIF              BIT(21)             /*!< periodic transfer not complete interrupt flag */
    160. 

  160. #define GINTF_ISOONCIF            BIT(21)             /*!< isochronous OUT transfer not complete interrupt flag */
    161. 

  161. #define GINTF_ISOINCIF            BIT(20)             /*!< isochronous IN transfer not complete interrupt flag */
    162. 

  162. #define GINTF_OEPIF               BIT(19)             /*!< OUT endpoint interrupt flag */
    163. 

  163. #define GINTF_IEPIF               BIT(18)             /*!< IN endpoint interrupt flag */
    164. 

  164. #define GINTF_EOPFIF              BIT(15)             /*!< end of periodic frame interrupt flag */
    165. 

  165. #define GINTF_ISOOPDIF            BIT(14)             /*!< isochronous OUT packet dropped interrupt flag */
    166. 

  166. #define GINTF_ENUMFIF             BIT(13)             /*!< enumeration finished */
    167. 

  167. #define GINTF_RST                 BIT(12)             /*!< USB reset */
    168. 

  168. #define GINTF_SP                  BIT(11)             /*!< USB suspend */
    169. 

  169. #define GINTF_ESP                 BIT(10)             /*!< early suspend */
    170. 

  170. #define GINTF_GONAK               BIT(7)              /*!< global OUT NAK effective */
    171. 

  171. #define GINTF_GNPINAK             BIT(6)              /*!< global IN non-periodic NAK effective */
    172. 

  172. #define GINTF_NPTXFEIF            BIT(5)              /*!< non-periodic tx FIFO empty interrupt flag */
    173. 

  173. #define GINTF_RXFNEIF             BIT(4)              /*!< rx FIFO non-empty interrupt flag */
    174. 

  174. #define GINTF_SOF                 BIT(3)              /*!< start of frame */
    175. 

  175. #define GINTF_OTGIF               BIT(2)              /*!< OTG interrupt flag */
    176. 

  176. #define GINTF_MFIF                BIT(1)              /*!< mode fault interrupt flag */
    177. 

  177. #define GINTF_COPM                BIT(0)              /*!< current operation mode */
    178. 

  178. 

  179. /* global interrupt enable register bits definitions */
    180. 

  180. #define GINTEN_WKUPIE             BIT(31)             /*!< wakeup interrupt enable */
    181. 

  181. #define GINTEN_SESIE              BIT(30)             /*!< session interrupt enable */
    182. 

  182. #define GINTEN_DISCIE             BIT(29)             /*!< disconnect interrupt enable */
    183. 

  183. #define GINTEN_IDPSCIE            BIT(28)             /*!< id pin status change interrupt enable */
    184. 

  184. #define GINTEN_PTXFEIE            BIT(26)             /*!< periodic tx FIFO empty interrupt enable */
    185. 

  185. #define GINTEN_HCIE               BIT(25)             /*!< host channels interrupt enable */
    186. 

  186. #define GINTEN_HPIE               BIT(24)             /*!< host port interrupt enable */
    187. 

  187. #define GINTEN_IPXIE              BIT(21)             /*!< periodic transfer not complete interrupt enable */
    188. 

  188. #define GINTEN_ISOONCIE           BIT(21)             /*!< isochronous OUT transfer not complete interrupt enable */
    189. 

  189. #define GINTEN_ISOINCIE           BIT(20)             /*!< isochronous IN transfer not complete interrupt enable */
    190. 

  190. #define GINTEN_OEPIE              BIT(19)             /*!< OUT endpoints interrupt enable */
    191. 

  191. #define GINTEN_IEPIE              BIT(18)             /*!< IN endpoints interrupt enable */
    192. 

  192. #define GINTEN_EOPFIE             BIT(15)             /*!< end of periodic frame interrupt enable */
    193. 

  193. #define GINTEN_ISOOPDIE           BIT(14)             /*!< isochronous OUT packet dropped interrupt enable */
    194. 

  194. #define GINTEN_ENUMFIE            BIT(13)             /*!< enumeration finish enable */
    195. 

  195. #define GINTEN_RSTIE              BIT(12)             /*!< USB reset interrupt enable */
    196. 

  196. #define GINTEN_SPIE               BIT(11)             /*!< USB suspend interrupt enable */
    197. 

  197. #define GINTEN_ESPIE              BIT(10)             /*!< early suspend interrupt enable */
    198. 

  198. #define GINTEN_GONAKIE            BIT(7)              /*!< global OUT NAK effective interrupt enable */
    199. 

  199. #define GINTEN_GNPINAKIE          BIT(6)              /*!< global non-periodic IN NAK effective interrupt enable */
    200. 

  200. #define GINTEN_NPTXFEIE           BIT(5)              /*!< non-periodic Tx FIFO empty interrupt enable */
    201. 

  201. #define GINTEN_RXFNEIE            BIT(4)              /*!< receive FIFO non-empty interrupt enable */
    202. 

  202. #define GINTEN_SOFIE              BIT(3)              /*!< start of frame interrupt enable */
    203. 

  203. #define GINTEN_OTGIE              BIT(2)              /*!< OTG interrupt enable */
    204. 

  204. #define GINTEN_MFIE               BIT(1)              /*!< mode fault interrupt enable */
    205. 

  205. 

  206. /* global receive status read and pop register bits definitions */
    207. 

  207. #define GRSTATRP_RPCKST           BITS(17, 20)        /*!< received packet status */
    208. 

  208. #define GRSTATRP_DPID             BITS(15, 16)        /*!< data PID */
    209. 

  209. #define GRSTATRP_BCOUNT           BITS(4, 14)         /*!< byte count */
    210. 

  210. #define GRSTATRP_CNUM             BITS(0, 3)          /*!< channel number */
    211. 

  211. #define GRSTATRP_EPNUM            BITS(0, 3)          /*!< endpoint number */
    212. 

  212. 

  213. /* global receive FIFO length register bits definitions */
    214. 

  214. #define GRFLEN_RXFD               BITS(0, 15)         /*!< rx FIFO depth */
    215. 

  215. 

  216. /* host non-periodic transmit FIFO length register bits definitions */
    217. 

  217. #define HNPTFLEN_HNPTXFD          BITS(16, 31)        /*!< non-periodic Tx FIFO depth */
    218. 

  218. #define HNPTFLEN_HNPTXRSAR        BITS(0, 15)         /*!< non-periodic Tx RAM start address */
    219. 

  219. 

  220. /* IN endpoint 0 transmit FIFO length register bits definitions */
    221. 

  221. #define DIEP0TFLEN_IEP0TXFD       BITS(16, 31)        /*!< IN Endpoint 0 Tx FIFO depth */
    222. 

  222. #define DIEP0TFLEN_IEP0TXRSAR     BITS(0, 15)         /*!< IN Endpoint 0 TX RAM start address */
    223. 

  223. 

  224. /* host non-periodic transmit FIFO/queue status register bits definitions */
    225. 

  225. #define HNPTFQSTAT_NPTXRQTOP      BITS(24, 30)        /*!< top entry of the non-periodic Tx request queue */
    226. 

  226. #define HNPTFQSTAT_NPTXRQS        BITS(16, 23)        /*!< non-periodic Tx request queue space */
    227. 

  227. #define HNPTFQSTAT_NPTXFS         BITS(0, 15)         /*!< non-periodic Tx FIFO space */
    228. 

  228. #define HNPTFQSTAT_CNUM           BITS(27, 30)        /*!< channel number*/
    229. 

  229. #define HNPTFQSTAT_EPNUM          BITS(27, 30)        /*!< endpoint number */
    230. 

  230. #define HNPTFQSTAT_TYPE           BITS(25, 26)        /*!< token type */
    231. 

  231. #define HNPTFQSTAT_TMF            BIT(24)             /*!< terminate flag */
    232. 

  232. 

  233. /* global core configuration register bits definitions */
    234. 

  234. #define GCCFG_VBUSIG              BIT(21)             /*!< vbus ignored */
    235. 

  235. #define GCCFG_SOFOEN              BIT(20)             /*!< SOF output enable */
    236. 

  236. #define GCCFG_VBUSBCEN            BIT(19)             /*!< the VBUS B-device comparer enable */
    237. 

  237. #define GCCFG_VBUSACEN            BIT(18)             /*!< the VBUS A-device comparer enable */
    238. 

  238. #define GCCFG_PWRON               BIT(16)             /*!< power on */
    239. 

  239. 

  240. /* core ID register bits definitions */
    241. 

  241. #define CID_CID                   BITS(0, 31)         /*!< core ID */
    242. 

  242. 

  243. /* host periodic transmit FIFO length register bits definitions */
    244. 

  244. #define HPTFLEN_HPTXFD            BITS(16, 31)        /*!< host periodic Tx FIFO depth */
    245. 

  245. #define HPTFLEN_HPTXFSAR          BITS(0, 15)         /*!< host periodic Tx RAM start address */
    246. 

  246. 

  247. /* device IN endpoint transmit FIFO length register bits definitions */
    248. 

  248. #define DIEPTFLEN_IEPTXFD         BITS(16, 31)        /*!< IN endpoint Tx FIFO x depth */
    249. 

  249. #define DIEPTFLEN_IEPTXRSAR       BITS(0, 15)         /*!< IN endpoint FIFOx Tx x RAM start address */
    250. 

  250. 

  251. /* host control register bits definitions */
    252. 

  252. #define HCTL_SPDFSLS              BIT(2)              /*!< speed limited to FS and LS */
    253. 

  253. #define HCTL_CLKSEL               BITS(0, 1)          /*!< clock select for USB clock */
    254. 

  254. 

  255. /* host frame interval register bits definitions */
    256. 

  256. #define HFT_FRI                   BITS(0, 15)         /*!< frame interval */
    257. 

  257. 

  258. /* host frame information remaining register bits definitions */
    259. 

  259. #define HFINFR_FRT                BITS(16, 31)        /*!< frame remaining time */
    260. 

  260. #define HFINFR_FRNUM              BITS(0, 15)         /*!< frame number */
    261. 

  261. 

  262. /* host periodic transmit FIFO/queue status register bits definitions */
    263. 

  263. #define HPTFQSTAT_PTXREQT         BITS(24, 31)        /*!< top entry of the periodic Tx request queue */
    264. 

  264. #define HPTFQSTAT_PTXREQS         BITS(16, 23)        /*!< periodic Tx request queue space */
    265. 

  265. #define HPTFQSTAT_PTXFS           BITS(0, 15)         /*!< periodic Tx FIFO space */
    266. 

  266. #define HPTFQSTAT_OEFRM           BIT(31)             /*!< odd/eveb frame */
    267. 

  267. #define HPTFQSTAT_CNUM            BITS(27, 30)        /*!< channel number */
    268. 

  268. #define HPTFQSTAT_EPNUM           BITS(27, 30)        /*!< endpoint number */
    269. 

  269. #define HPTFQSTAT_TYPE            BITS(25, 26)        /*!< token type */
    270. 

  270. #define HPTFQSTAT_TMF             BIT(24)             /*!< terminate flag */
    271. 

  271. 

  272. /* host all channels interrupt register bits definitions */
    273. 

  273. #define HACHINT_HACHINT           BITS(0, 11)         /*!< host all channel interrupts */
    274. 

  274. 

  275. /* host all channels interrupt enable register bits definitions */
    276. 

  276. #define HACHINTEN_CINTEN          BITS(0, 11)         /*!< channel interrupt enable */
    277. 

  277. 

  278. /* host port control and status register bits definitions */
    279. 

  279. #define HPCS_PS                   BITS(17, 18)        /*!< port speed */
    280. 

  280. #define HPCS_PP                   BIT(12)             /*!< port power */
    281. 

  281. #define HPCS_PLST                 BITS(10, 11)        /*!< port line status */
    282. 

  282. #define HPCS_PRST                 BIT(8)              /*!< port reset */
    283. 

  283. #define HPCS_PSP                  BIT(7)              /*!< port suspend */
    284. 

  284. #define HPCS_PREM                 BIT(6)              /*!< port resume */
    285. 

  285. #define HPCS_PEDC                 BIT(3)              /*!< port enable/disable change */
    286. 

  286. #define HPCS_PE                   BIT(2)              /*!< port enable */
    287. 

  287. #define HPCS_PCD                  BIT(1)              /*!< port connect detected */
    288. 

  288. #define HPCS_PCST                 BIT(0)              /*!< port connect status */
    289. 

  289. 

  290. /* host channel-x control register bits definitions */
    291. 

  291. #define HCHCTL_CEN                BIT(31)             /*!< channel enable */
    292. 

  292. #define HCHCTL_CDIS               BIT(30)             /*!< channel disable */
    293. 

  293. #define HCHCTL_ODDFRM             BIT(29)             /*!< odd frame */
    294. 

  294. #define HCHCTL_DAR                BITS(22, 28)        /*!< device address */
    295. 

  295. #define HCHCTL_MPC                BITS(20, 21)        /*!< multiple packet count */
    296. 

  296. #define HCHCTL_EPTYPE             BITS(18, 19)        /*!< endpoint type */
    297. 

  297. #define HCHCTL_LSD                BIT(17)             /*!< low-speed device */
    298. 

  298. #define HCHCTL_EPDIR              BIT(15)             /*!< endpoint direction */
    299. 

  299. #define HCHCTL_EPNUM              BITS(11, 14)        /*!< endpoint number */
    300. 

  300. #define HCHCTL_MPL                BITS(0, 10)         /*!< maximum packet length */
    301. 

  301. 

  302. /* host channel-x split transaction register bits definitions */
    303. 

  303. #define HCHSTCTL_SPLEN            BIT(31)             /*!< enable high-speed split transaction */
    304. 

  304. #define HCHSTCTL_CSPLT            BIT(16)             /*!< complete-split enable */
    305. 

  305. #define HCHSTCTL_ISOPCE           BITS(14, 15)        /*!< isochronous OUT payload continuation encoding */
    306. 

  306. #define HCHSTCTL_HADDR            BITS(7, 13)         /*!< HUB address */
    307. 

  307. #define HCHSTCTL_PADDR            BITS(0, 6)          /*!< port address */
    308. 

  308. 

  309. /* host channel-x interrupt flag register bits definitions */
    310. 

  310. #define HCHINTF_DTER              BIT(10)             /*!< data toggle error */
    311. 

  311. #define HCHINTF_REQOVR            BIT(9)              /*!< request queue overrun */
    312. 

  312. #define HCHINTF_BBER              BIT(8)              /*!< babble error */
    313. 

  313. #define HCHINTF_USBER             BIT(7)              /*!< USB bus Error */
    314. 

  314. #define HCHINTF_NYET              BIT(6)              /*!< NYET */
    315. 

  315. #define HCHINTF_ACK               BIT(5)              /*!< ACK */
    316. 

  316. #define HCHINTF_NAK               BIT(4)              /*!< NAK */
    317. 

  317. #define HCHINTF_STALL             BIT(3)              /*!< STALL */
    318. 

  318. #define HCHINTF_DMAER             BIT(2)              /*!< DMA error */
    319. 

  319. #define HCHINTF_CH                BIT(1)              /*!< channel halted */
    320. 

  320. #define HCHINTF_TF                BIT(0)              /*!< transfer finished */
    321. 

  321. 

  322. /* host channel-x interrupt enable register bits definitions */
    323. 

  323. #define HCHINTEN_DTERIE           BIT(10)             /*!< data toggle error interrupt enable */
    324. 

  324. #define HCHINTEN_REQOVRIE         BIT(9)              /*!< request queue overrun interrupt enable */
    325. 

  325. #define HCHINTEN_BBERIE           BIT(8)              /*!< babble error interrupt enable */
    326. 

  326. #define HCHINTEN_USBERIE          BIT(7)              /*!< USB bus error interrupt enable */
    327. 

  327. #define HCHINTEN_NYETIE           BIT(6)              /*!< NYET interrupt enable */
    328. 

  328. #define HCHINTEN_ACKIE            BIT(5)              /*!< ACK interrupt enable */
    329. 

  329. #define HCHINTEN_NAKIE            BIT(4)              /*!< NAK interrupt enable */
    330. 

  330. #define HCHINTEN_STALLIE          BIT(3)              /*!< STALL interrupt enable */
    331. 

  331. #define HCHINTEN_DMAERIE          BIT(2)              /*!< DMA error interrupt enable */
    332. 

  332. #define HCHINTEN_CHIE             BIT(1)              /*!< channel halted interrupt enable */
    333. 

  333. #define HCHINTEN_TFIE             BIT(0)              /*!< transfer finished interrupt enable */
    334. 

  334. 

  335. /* host channel-x transfer length register bits definitions */
    336. 

  336. #define HCHLEN_PING               BIT(31)             /*!< PING token request */
    337. 

  337. #define HCHLEN_DPID               BITS(29, 30)        /*!< data PID */
    338. 

  338. #define HCHLEN_PCNT               BITS(19, 28)        /*!< packet count */
    339. 

  339. #define HCHLEN_TLEN               BITS(0, 18)         /*!< transfer length */
    340. 

  340. 

  341. /* host channel-x DMA address register bits definitions */
    342. 

  342. #define HCHDMAADDR_DMAADDR        BITS(0, 31)         /*!< DMA address */
    343. 

  343. 

  344. /* device control and status registers */
    345. 

  345. /* device configuration registers bits definitions */
    346. 

  346. #define DCFG_EOPFT                BITS(11, 12)        /*!< end of periodic frame time */
    347. 

  347. #define DCFG_DAR                  BITS(4, 10)         /*!< device address */
    348. 

  348. #define DCFG_NZLSOH               BIT(2)              /*!< non-zero-length status OUT handshake */
    349. 

  349. #define DCFG_DS                   BITS(0, 1)          /*!< device speed */
    350. 

  350. 

  351. /* device control registers bits definitions */
    352. 

  352. #define DCTL_POIF                 BIT(11)             /*!< power-on initialization finished */
    353. 

  353. #define DCTL_CGONAK               BIT(10)             /*!< clear global OUT NAK */
    354. 

  354. #define DCTL_SGONAK               BIT(9)              /*!< set global OUT NAK */
    355. 

  355. #define DCTL_CGINAK               BIT(8)              /*!< clear global IN NAK */
    356. 

  356. #define DCTL_SGINAK               BIT(7)              /*!< set global IN NAK */
    357. 

  357. #define DCTL_GONS                 BIT(3)              /*!< global OUT NAK status */
    358. 

  358. #define DCTL_GINS                 BIT(2)              /*!< global IN NAK status */
    359. 

  359. #define DCTL_SD                   BIT(1)              /*!< soft disconnect */
    360. 

  360. #define DCTL_RWKUP                BIT(0)              /*!< remote wakeup */
    361. 

  361. 

  362. /* device status registers bits definitions */
    363. 

  363. #define DSTAT_FNRSOF              BITS(8, 21)         /*!< the frame number of the received SOF. */
    364. 

  364. #define DSTAT_ES                  BITS(1, 2)          /*!< enumerated speed */
    365. 

  365. #define DSTAT_SPST                BIT(0)              /*!< suspend status */
    366. 

  366. 

  367. /* device IN endpoint common interrupt enable registers bits definitions */
    368. 

  368. #define DIEPINTEN_NAKEN           BIT(13)             /*!< NAK handshake sent by USBHS interrupt enable bit */
    369. 

  369. #define DIEPINTEN_TXFEEN          BIT(7)              /*!< transmit FIFO empty interrupt enable bit */
    370. 

  370. #define DIEPINTEN_IEPNEEN         BIT(6)              /*!< IN endpoint NAK effective interrupt enable bit */
    371. 

  371. #define DIEPINTEN_EPTXFUDEN       BIT(4)              /*!< endpoint Tx FIFO underrun interrupt enable bit */
    372. 

  372. #define DIEPINTEN_CITOEN          BIT(3)              /*!< control In Timeout interrupt enable bit */
    373. 

  373. #define DIEPINTEN_EPDISEN         BIT(1)              /*!< endpoint disabled interrupt enable bit */
    374. 

  374. #define DIEPINTEN_TFEN            BIT(0)              /*!< transfer finished interrupt enable bit */ 
    375. 

  375. 

  376. /* device OUT endpoint common interrupt enable registers bits definitions */
    377. 

  377. #define DOEPINTEN_NYETEN          BIT(14)             /*!< NYET handshake is sent interrupt enable bit */
    378. 

  378. #define DOEPINTEN_BTBSTPEN        BIT(6)              /*!< back-to-back SETUP packets interrupt enable bit */
    379. 

  379. #define DOEPINTEN_EPRXFOVREN      BIT(4)              /*!< endpoint Rx FIFO overrun interrupt enable bit */
    380. 

  380. #define DOEPINTEN_STPFEN          BIT(3)              /*!< SETUP phase finished interrupt enable bit */
    381. 

  381. #define DOEPINTEN_EPDISEN         BIT(1)              /*!< endpoint disabled interrupt enable bit */
    382. 

  382. #define DOEPINTEN_TFEN            BIT(0)              /*!< transfer finished interrupt enable bit */
    383. 

  383. 

  384. /* device all endpoints interrupt registers bits definitions */
    385. 

  385. #define DAEPINT_OEPITB            BITS(16, 21)        /*!< device all OUT endpoint interrupt bits */
    386. 

  386. #define DAEPINT_IEPITB            BITS(0, 5)          /*!< device all IN endpoint interrupt bits */
    387. 

  387. 

  388. /* device all endpoints interrupt enable registers bits definitions */
    389. 

  389. #define DAEPINTEN_OEPIE           BITS(16, 21)        /*!< OUT endpoint interrupt enable */
    390. 

  390. #define DAEPINTEN_IEPIE           BITS(0, 3)          /*!< IN endpoint interrupt enable */
    391. 

  391. 

  392. /* device Vbus discharge time registers bits definitions */
    393. 

  393. #define DVBUSDT_DVBUSDT           BITS(0, 15)         /*!< device VBUS discharge time */
    394. 

  394. 

  395. /* device Vbus pulsing time registers bits definitions */
    396. 

  396. #define DVBUSPT_DVBUSPT           BITS(0, 11)         /*!< device VBUS pulsing time */
    397. 

  397. 

  398. /* device IN endpoint FIFO empty interrupt enable register bits definitions */
    399. 

  399. #define DIEPFEINTEN_IEPTXFEIE     BITS(0, 5)          /*!< IN endpoint Tx FIFO empty interrupt enable bits */
    400. 

  400. 

  401. /* device endpoint 1 interrupt register bits definitions */
    402. 

  402. #define DEP1INT_OEP1INT           BIT(17)             /*!< OUT Endpoint 1 interrupt */
    403. 

  403. #define DEP1INT_IEP1INT           BIT(1)              /*!< IN Endpoint 1 interrupt */
    404. 

  404. 

  405. /* device endpoint 1 interrupt register enable bits definitions */
    406. 

  406. #define DEP1INTEN_OEP1INTEN       BIT(17)             /*!< OUT Endpoint 1 interrupt enable */
    407. 

  407. #define DEP1INTEN_IEP1INTEN       BIT(1)              /*!< IN Endpoint 1 interrupt enable */
    408. 

  408. 

  409. /* device IN endpoint 1 interrupt enable register bits definitions */
    410. 

  410. #define DIEP1INTEN_NAKEN          BIT(13)             /*!< NAK handshake sent by USBHS interrupt enable bit */
    411. 

  411. #define DIEP1INTEN_IEPNEEN        BIT(6)              /*!< IN endpoint NAK effective interrupt enable bit */
    412. 

  412. #define DIEP1INTEN_EPTXFUDEN      BIT(4)              /*!< endpoint Tx FIFO underrun interrupt enable bit */
    413. 

  413. #define DIEP1INTEN_CITOEN         BIT(3)              /*!< control In Timeout interrupt enable bit */
    414. 

  414. #define DIEP1INTEN_EPDISEN        BIT(1)              /*!< endpoint disabled interrupt enable bit */
    415. 

  415. #define DIEP1INTEN_TFEN           BIT(0)              /*!< transfer finished interrupt enable bit */
    416. 

  416. 

  417. /* device OUT endpoint 1 interrupt enable register bits definitions */
    418. 

  418. #define DOEP1INTEN_NYETEN         BIT(14)             /*!< NYET handshake is sent interrupt enable bit */
    419. 

  419. #define DOEP1INTEN_BTBSTPEN       BIT(6)              /*!< back-to-back SETUP packets interrupt enable bit */
    420. 

  420. #define DOEP1INTEN_EPRXOVREN      BIT(4)              /*!< endpoint Rx FIFO over run interrupt enable bit */
    421. 

  421. #define DOEP1INTEN_STPFEN         BIT(3)              /*!< SETUP phase finished interrupt enable bit */
    422. 

  422. #define DOEP1INTEN_EPDISEN        BIT(1)              /*!< endpoint disabled interrupt enable bit */
    423. 

  423. #define DOEP1INTEN_TFEN           BIT(0)              /*!< back-to-back SETUP packets interrupt enable bit */
    424. 

  424. 

  425. /* device endpoint 0 control register bits definitions */
    426. 

  426. #define DEP0CTL_EPEN              BIT(31)             /*!< endpoint enable */
    427. 

  427. #define DEP0CTL_EPD               BIT(30)             /*!< endpoint disable */
    428. 

  428. #define DEP0CTL_SNAK              BIT(27)             /*!< set NAK */
    429. 

  429. #define DEP0CTL_CNAK              BIT(26)             /*!< clear NAK */
    430. 

  430. #define DIEP0CTL_TXFNUM           BITS(22, 25)        /*!< tx FIFO number */
    431. 

  431. #define DEP0CTL_STALL             BIT(21)             /*!< STALL handshake */
    432. 

  432. #define DOEP0CTL_SNOOP            BIT(20)             /*!< snoop mode */
    433. 

  433. #define DEP0CTL_EPTYPE            BITS(18, 19)        /*!< endpoint type */
    434. 

  434. #define DEP0CTL_NAKS              BIT(17)             /*!< NAK status */
    435. 

  435. #define DEP0CTL_EPACT             BIT(15)             /*!< endpoint active */
    436. 

  436. #define DEP0CTL_MPL               BITS(0, 1)          /*!< maximum packet length */
    437. 

  437. 

  438. /* device endpoint x control register bits definitions */
    439. 

  439. #define DEPCTL_EPEN               BIT(31)             /*!< endpoint enable */
    440. 

  440. #define DEPCTL_EPD                BIT(30)             /*!< endpoint disable */
    441. 

  441. #define DEPCTL_SODDFRM            BIT(29)             /*!< set odd frame */
    442. 

  442. #define DEPCTL_SD1PID             BIT(29)             /*!< set DATA1 PID */
    443. 

  443. #define DEPCTL_SEVNFRM            BIT(28)             /*!< set even frame */
    444. 

  444. #define DEPCTL_SD0PID             BIT(28)             /*!< set DATA0 PID */
    445. 

  445. #define DEPCTL_SNAK               BIT(27)             /*!< set NAK */
    446. 

  446. #define DEPCTL_CNAK               BIT(26)             /*!< clear NAK */
    447. 

  447. #define DIEPCTL_TXFNUM            BITS(22, 25)        /*!< tx FIFO number */
    448. 

  448. #define DEPCTL_STALL              BIT(21)             /*!< STALL handshake */
    449. 

  449. #define DOEPCTL_SNOOP             BIT(20)             /*!< snoop mode */
    450. 

  450. #define DEPCTL_EPTYPE             BITS(18, 19)        /*!< endpoint type */
    451. 

  451. #define DEPCTL_NAKS               BIT(17)             /*!< NAK status */
    452. 

  452. #define DEPCTL_EOFRM              BIT(16)             /*!< even/odd frame */
    453. 

  453. #define DEPCTL_DPID               BIT(16)             /*!< endpoint data PID */
    454. 

  454. #define DEPCTL_EPACT              BIT(15)             /*!< endpoint active */
    455. 

  455. #define DEPCTL_MPL                BITS(0, 10)         /*!< maximum packet length */
    456. 

  456. 

  457. /* device IN endpoint-x interrupt flag register bits definitions */
    458. 

  458. #define DIEPINTF_NAK              BIT(13)             /*!< NAK handshake sent by USBHS */
    459. 

  459. #define DIEPINTF_TXFE             BIT(7)              /*!< transmit FIFO empty */
    460. 

  460. #define DIEPINTF_IEPNE            BIT(6)              /*!< IN endpoint NAK effective */
    461. 

  461. #define DIEPINTF_EPTXFUD          BIT(4)              /*!< endpoint Tx FIFO underrun */
    462. 

  462. #define DIEPINTF_CITO             BIT(3)              /*!< control In Timeout interrupt */
    463. 

  463. #define DIEPINTF_EPDIS            BIT(1)              /*!< endpoint disabled */
    464. 

  464. #define DIEPINTF_TF               BIT(0)              /*!< transfer finished */
    465. 

  465. 

  466. /* device OUT endpoint-x interrupt flag register bits definitions */
    467. 

  467. #define DOEPINTF_NYET             BIT(14)             /*!< NYET handshake is sent */
    468. 

  468. #define DOEPINTF_BTBSTP           BIT(6)              /*!< back-to-back SETUP packets */
    469. 

  469. #define DOEPINTF_EPRXFOVR         BIT(4)              /*!< endpoint Rx FIFO overrun */
    470. 

  470. #define DOEPINTF_STPF             BIT(3)              /*!< SETUP phase finished */
    471. 

  471. #define DOEPINTF_EPDIS            BIT(1)              /*!< endpoint disabled */
    472. 

  472. #define DOEPINTF_TF               BIT(0)              /*!< transfer finished */
    473. 

  473. 

  474. /* device IN endpoint 0 transfer length register bits definitions */
    475. 

  475. #define DIEP0LEN_PCNT             BITS(19, 20)        /*!< packet count */
    476. 

  476. #define DIEP0LEN_TLEN             BITS(0, 6)          /*!< transfer length */
    477. 

  477. 

  478. /* device OUT endpoint 0 transfer length register bits definitions */
    479. 

  479. #define DOEP0LEN_STPCNT           BITS(29, 30)        /*!< SETUP packet count */
    480. 

  480. #define DOEP0LEN_PCNT             BIT(19)             /*!< packet count */
    481. 

  481. #define DOEP0LEN_TLEN             BITS(0, 6)          /*!< transfer length */
    482. 

  482. 

  483. /* device OUT endpoint-x transfer length register bits definitions */
    484. 

  484. #define DOEPLEN_RXDPID            BITS(29, 30)        /*!< received data PID */
    485. 

  485. #define DOEPLEN_STPCNT            BITS(29, 30)        /*!< SETUP packet count */
    486. 

  486. #define DIEPLEN_MCNT              BITS(29, 30)        /*!< multi count */
    487. 

  487. #define DEPLEN_PCNT               BITS(19, 28)        /*!< packet count */
    488. 

  488. #define DEPLEN_TLEN               BITS(0, 18)         /*!< transfer length */
    489. 

  489. 

  490. /* device IN endpoint-x DMA address register bits definitions */
    491. 

  491. #define DIEPDMAADDR_DMAADDR       BITS(0, 31)         /*!< DMA address */
    492. 

  492. 

  493. /* device OUT endpoint-x DMA address register bits definitions */
    494. 

  494. #define DOEPDMAADDR_DMAADDR       BITS(0, 31)         /*!< DMA address */
    495. 

  495. 

  496. /* device IN endpoint-x transmit FIFO status register bits definitions */
    497. 

  497. #define DIEPTFSTAT_IEPTFS         BITS(0, 15)         /*!< IN endpoint¡¯s Tx FIFO space remaining */
    498. 

  498. 

  499. /* USB power and clock registers bits definition */
    500. 

  500. #define PWRCLKCTL_SHCLK           BIT(1)              /*!< stop HCLK */
    501. 

  501. #define PWRCLKCTL_SUCLK           BIT(0)              /*!< stop the USB clock */
    502. 

  502. 

  503. /* register options defines */
    504. 

  504. #define DCFG_DEVSPEED(regval)     (DCFG_DS & ((regval) << 0U))      /*!< device speed configuration */
    505. 

  505. 

  506. #define USB_SPEED_EXP_HIGH        DCFG_DEVSPEED(0U)                 /*!< device external PHY high speed */
    507. 

  507. #define USB_SPEED_EXP_FULL        DCFG_DEVSPEED(1U)                 /*!< device external PHY full speed */
    508. 

  508. #define USB_SPEED_INP_FULL        DCFG_DEVSPEED(3U)                 /*!< device internal PHY full speed */
    509. 

  509. 

  510. #define GAHBCS_TFEL(regval)       (GAHBCS_TXFTH & ((regval) << 7U)) /*!< device speed configuration */
    511. 

  511. 

  512. #define TXFIFO_EMPTY_HALF         GAHBCS_TFEL(0U)                   /*!< Tx FIFO half empty */
    513. 

  513. #define TXFIFO_EMPTY              GAHBCS_TFEL(1U)                   /*!< Tx FIFO completely empty */
    514. 

  514. 

  515. #define GAHBCS_DMAINCR(regval)    (GAHBCS_BURST & ((regval) << 1U)) /*!< AHB burst type used by DMA*/
    516. 

  516. 

  517. #define DMA_INCR0                 GAHBCS_DMAINCR(0U)                /*!< single burst type used by DMA*/
    518. 

  518. #define DMA_INCR1                 GAHBCS_DMAINCR(1U)                /*!< 4-beat incrementing burst type used by DMA*/
    519. 

  519. #define DMA_INCR4                 GAHBCS_DMAINCR(3U)                /*!< 8-beat incrementing burst type used by DMA*/
    520. 

  520. #define DMA_INCR8                 GAHBCS_DMAINCR(5U)                /*!< 16-beat incrementing burst type used by DMA*/
    521. 

  521. #define DMA_INCR16                GAHBCS_DMAINCR(7U)                /*!< 32-beat incrementing burst type used by DMA*/
    522. 

  522. 

  523. #define DCFG_PFRI(regval)         (DCFG_EOPFT & ((regval) << 11U))  /*!< end of periodic frame time configuration */
    524. 

  524. 

  525. #define FRAME_INTERVAL_80         DCFG_PFRI(0U)                     /*!< 80% of the frame time */
    526. 

  526. #define FRAME_INTERVAL_85         DCFG_PFRI(1U)                     /*!< 85% of the frame time */
    527. 

  527. #define FRAME_INTERVAL_90         DCFG_PFRI(2U)                     /*!< 90% of the frame time */
    528. 

  528. #define FRAME_INTERVAL_95         DCFG_PFRI(3U)                     /*!< 95% of the frame time */
    529. 

  529. 

  530. #define DEP0_MPL(regval)          (DEP0CTL_MPL & ((regval) << 0U))   /*!< maximum packet length configuration */
    531. 

  531. 

  532. #define EP0MPL_64                 DEP0_MPL(0U)                   /*!< maximum packet length 64 bytes */
    533. 

  533. #define EP0MPL_32                 DEP0_MPL(1U)                   /*!< maximum packet length 32 bytes */
    534. 

  534. #define EP0MPL_16                 DEP0_MPL(2U)                   /*!< maximum packet length 16 bytes */
    535. 

  535. #define EP0MPL_8                  DEP0_MPL(3U)                   /*!< maximum packet length 8 bytes */
    536. 

  536. 

  537. /* endpoints address */
    538. 

  538. 

  539. /* first bit is direction(0 for Rx and 1 for Tx) */
    540. 

  540. #define EP0_OUT                   ((uint8_t)0x00U)                  /*!< endpoint out 0 */
    541. 

  541. #define EP0_IN                    ((uint8_t)0x80U)                  /*!< endpoint in 0 */
    542. 

  542. #define EP1_OUT                   ((uint8_t)0x01U)                  /*!< endpoint out 1 */
    543. 

  543. #define EP1_IN                    ((uint8_t)0x81U)                  /*!< endpoint in 1 */
    544. 

  544. #define EP2_OUT                   ((uint8_t)0x02U)                  /*!< endpoint out 2 */
    545. 

  545. #define EP2_IN                    ((uint8_t)0x82U)                  /*!< endpoint in 2 */
    546. 

  546. #define EP3_OUT                   ((uint8_t)0x03U)                  /*!< endpoint out 3 */
    547. 

  547. #define EP3_IN                    ((uint8_t)0x83U)                  /*!< endpoint in 3 */
    548. 

  548. 

  549. /* enable global interrupt */
    550. 

  550. #define USB_GLOBAL_INT_ENABLE()       (USB_GAHBCS |= GAHBCS_GINTEN)
    551. 

  551. 

  552. /* disable global interrupt */
    553. 

  553. #define USB_GLOBAL_INT_DISABLE()      (USB_GAHBCS &= ~GAHBCS_GINTEN)
    554. 

  554. 

  555. /* get current operation mode */
    556. 

  556. #define USB_CURRENT_MODE_GET()        (USB_GINTF & GINTF_COPM)
    557. 

  557. 

  558. /* read global interrupt flag */
    559. 

  559. #define USB_CORE_INTR_READ(x) \
    560. 

  560. do { \
    561. 

  561.     uint32_t global_intf = USB_GINTF; \
    562. 

  562.     (x) = global_intf & USB_GINTEN; \
    563. 

  563. } while(0)
    564. 

  564. 

  565. /* read global interrupt flag */
    566. 

  566. #define USB_DAOEP_INTR_READ(x) \
    567. 

  567. do { \
    568. 

  568.     uint32_t dev_all_ep_inten = USB_DAEPINTEN; \
    569. 

  569.     uint32_t dev_all_ep_int = USB_DAEPINT; \
    570. 

  570.     uint32_t out_ep_intb = DAEPINT_OEPITB;  \
    571. 

  571.     (x) = (dev_all_ep_inten & dev_all_ep_int & out_ep_intb) >> 16; \
    572. 

  572. } while(0)
    573. 

  573. 

  574. /* read out endpoint-x interrupt flag */
    575. 

  575. #define USB_DOEP_INTR_READ(x, EpID) \
    576. 

  576. do { \
    577. 

  577.     uint32_t out_epintf = USB_DOEPxINTF(EpID); \
    578. 

  578.     (x) = out_epintf & USB_DOEPINTEN; \
    579. 

  579. } while(0) 
    580. 

  580. 

  581. /* read all in endpoint interrupt flag */
    582. 

  582. #define USB_DAIEP_INTR_READ(x) \
    583. 

  583. do { \
    584. 

  584.     uint32_t dev_all_ep_inten = USB_DAEPINTEN; \
    585. 

  585.     uint32_t dev_all_ep_int = USB_DAEPINT; \
    586. 

  586.     uint32_t in_ep_intb = DAEPINT_IEPITB;  \
    587. 

  587.     (x) = dev_all_ep_inten & dev_all_ep_int & in_ep_intb; \
    588. 

  588. } while(0)
    589. 

  589. 

  590. 

  591. /* read in endpoint-x interrupt flag */
    592. 

  592. #define USB_DIEP_INTR_READ(x, EpID) \
    593. 

  593. do { \
    594. 

  594.     uint32_t dev_ep_intf = USB_DIEPxINTF(EpID); \
    595. 

  595.     uint32_t dev_ep_fifoempty_intf = (((USB_DIEPFEINTEN >> (EpID)) & 0x1U) << 7U); \
    596. 

  596.     uint32_t dev_inep_inten = USB_DIEPINTEN; \
    597. 

  597.     (x) = dev_ep_intf & (dev_ep_fifoempty_intf | dev_inep_inten); \
    598. 

  598. } while(0)
    599. 

  599. 

  600. /* generate remote wakup signal */
    601. 

  601. #define USB_REMOTE_WAKEUP_SET()       (USB_DCTL |= DCTL_RWKUP)
    602. 

  602. 

  603. /* no remote wakup signal generate */
    604. 

  604. #define USB_REMOTE_WAKEUP_RESET()     (USB_DCTL &= ~DCTL_RWKUP)
    605. 

  605. 

  606. /* generate soft disconnect */
    607. 

  607. #define USB_SOFT_DISCONNECT_ENABLE()  (USB_DCTL |= DCTL_SD)
    608. 

  608. 

  609. /* no soft disconnect generate */
    610. 

  610. #define USB_SOFT_DISCONNECT_DISABLE() (USB_DCTL &= ~DCTL_SD)
    611. 

  611. 

  612. /* set device address */
    613. 

  613. #define USB_SET_DEVADDR(DevAddr)      (USB_DCFG |= (DevAddr) << 4U)
    614. 

  614. 

  615. /* check whether frame is even */
    616. 

  616. #define USB_EVEN_FRAME()              (!(USB_HFINFR & 0x01U))
    617. 

  617. 

  618. /* read port status */
    619. 

  619. #define USB_PORT_READ()               (USB_HPCS & (~HPCS_PE) & (~HPCS_PCD) & (~HPCS_PEDC))
    620. 

  620. 

  621. /* usb clock initialize */
    622. 

  622. #define USB_FSLSCLOCK_INIT(ClockFreq) (USB_HCTL &= ~HCTL_CLKSEL | (ClockFreq))
    623. 

  623. 

  624. /* get usb current speed */
    625. 

  625. #define USB_CURRENT_SPEED_GET()       ((USB_HPCS & HPCS_PS) >> 17)
    626. 

  626. 

  627. /* get usb current frame */
    628. 

  628. #define USB_CURRENT_FRAME_GET()       (USB_HFINFR & 0xFFFFU)
    629. 

  629. 

  630. #endif /* USB_REGS_H */
    631.