drv_spi.c 8.5 KB

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  1. /*
  2. * File : drv_spi.c
  3. * This file is part of RT-Thread RTOS
  4. * COPYRIGHT (C) 2017 RT-Thread Develop Team
  5. *
  6. * The license and distribution terms for this file may be
  7. * found in the file LICENSE in this distribution or at
  8. * http://www.rt-thread.org/license/LICENSE
  9. *
  10. * Change Logs:
  11. * Date Author Notes
  12. * 2017-06-05 tanek first implementation.
  13. * 2018-04-19 misonyo Porting for gd32f30x
  14. */
  15. #include "drv_spi.h"
  16. #include "gd32f30x.h"
  17. #include <rtthread.h>
  18. #if defined(RT_USING_SPI) && defined(RT_USING_PIN)
  19. #include <rtdevice.h>
  20. #if !defined(RT_USING_SPI0) && !defined(RT_USING_SPI1) && \
  21. !defined(RT_USING_SPI2)
  22. #error "Please define at least one SPIx"
  23. #endif
  24. /* #define DEBUG */
  25. #ifdef DEBUG
  26. #define DEBUG_PRINTF(...) rt_kprintf(__VA_ARGS__)
  27. #else
  28. #define DEBUG_PRINTF(...)
  29. #endif
  30. /* private rt-thread spi ops function */
  31. static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration);
  32. static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message);
  33. static struct rt_spi_ops gd32_spi_ops =
  34. {
  35. configure,
  36. xfer
  37. };
  38. static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration)
  39. {
  40. spi_parameter_struct spi_init_struct;
  41. rt_uint32_t spi_periph = (rt_uint32_t)device->bus->parent.user_data;
  42. RT_ASSERT(device != RT_NULL);
  43. RT_ASSERT(configuration != RT_NULL);
  44. if(configuration->data_width <= 8)
  45. {
  46. spi_init_struct.frame_size = SPI_FRAMESIZE_8BIT;
  47. }
  48. else if(configuration->data_width <= 16)
  49. {
  50. spi_init_struct.frame_size = SPI_FRAMESIZE_16BIT;
  51. }
  52. else
  53. {
  54. return RT_EIO;
  55. }
  56. {
  57. rcu_clock_freq_enum spi_src;
  58. rt_uint32_t spi_apb_clock;
  59. rt_uint32_t max_hz;
  60. max_hz = configuration->max_hz;
  61. DEBUG_PRINTF("sys freq: %d\n", rcu_clock_freq_get(CK_SYS));
  62. DEBUG_PRINTF("CK_APB2 freq: %d\n", rcu_clock_freq_get(CK_APB2));
  63. DEBUG_PRINTF("max freq: %d\n", max_hz);
  64. if (spi_periph == SPI1 || spi_periph == SPI2)
  65. {
  66. spi_src = CK_APB1;
  67. }
  68. else
  69. {
  70. spi_src = CK_APB2;
  71. }
  72. spi_apb_clock = rcu_clock_freq_get(spi_src);
  73. if(max_hz >= spi_apb_clock/2)
  74. {
  75. spi_init_struct.prescale = SPI_PSC_2;
  76. }
  77. else if (max_hz >= spi_apb_clock/4)
  78. {
  79. spi_init_struct.prescale = SPI_PSC_4;
  80. }
  81. else if (max_hz >= spi_apb_clock/8)
  82. {
  83. spi_init_struct.prescale = SPI_PSC_8;
  84. }
  85. else if (max_hz >= spi_apb_clock/16)
  86. {
  87. spi_init_struct.prescale = SPI_PSC_16;
  88. }
  89. else if (max_hz >= spi_apb_clock/32)
  90. {
  91. spi_init_struct.prescale = SPI_PSC_32;
  92. }
  93. else if (max_hz >= spi_apb_clock/64)
  94. {
  95. spi_init_struct.prescale = SPI_PSC_64;
  96. }
  97. else if (max_hz >= spi_apb_clock/128)
  98. {
  99. spi_init_struct.prescale = SPI_PSC_128;
  100. }
  101. else
  102. {
  103. /* min prescaler 256 */
  104. spi_init_struct.prescale = SPI_PSC_256;
  105. }
  106. } /* baudrate */
  107. switch(configuration->mode & RT_SPI_MODE_3)
  108. {
  109. case RT_SPI_MODE_0:
  110. spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE;
  111. break;
  112. case RT_SPI_MODE_1:
  113. spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_2EDGE;
  114. break;
  115. case RT_SPI_MODE_2:
  116. spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_1EDGE;
  117. break;
  118. case RT_SPI_MODE_3:
  119. spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE;
  120. break;
  121. }
  122. /* MSB or LSB */
  123. if(configuration->mode & RT_SPI_MSB)
  124. {
  125. spi_init_struct.endian = SPI_ENDIAN_MSB;
  126. }
  127. else
  128. {
  129. spi_init_struct.endian = SPI_ENDIAN_LSB;
  130. }
  131. spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX;
  132. spi_init_struct.device_mode = SPI_MASTER;
  133. spi_init_struct.nss = SPI_NSS_SOFT;
  134. spi_init(spi_periph, &spi_init_struct);
  135. spi_crc_off(spi_periph);
  136. spi_enable(spi_periph);
  137. return RT_EOK;
  138. };
  139. static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message)
  140. {
  141. rt_base_t gd32_cs_pin = (rt_base_t)device->parent.user_data;
  142. rt_uint32_t spi_periph = (rt_uint32_t)device->bus->parent.user_data;
  143. struct rt_spi_configuration * config = &device->config;
  144. RT_ASSERT(device != NULL);
  145. RT_ASSERT(message != NULL);
  146. /* take CS */
  147. if(message->cs_take)
  148. {
  149. rt_pin_write(gd32_cs_pin, PIN_LOW);
  150. DEBUG_PRINTF("spi take cs\n");
  151. }
  152. {
  153. if(config->data_width <= 8)
  154. {
  155. const rt_uint8_t * send_ptr = message->send_buf;
  156. rt_uint8_t * recv_ptr = message->recv_buf;
  157. rt_uint32_t size = message->length;
  158. DEBUG_PRINTF("spi poll transfer start: %d\n", size);
  159. while(size--)
  160. {
  161. rt_uint8_t data = 0xFF;
  162. if(send_ptr != RT_NULL)
  163. {
  164. data = *send_ptr++;
  165. }
  166. // Todo: replace register read/write by gd32f3 lib
  167. //Wait until the transmit buffer is empty
  168. while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE));
  169. // Send the byte
  170. spi_i2s_data_transmit(spi_periph, data);
  171. //Wait until a data is received
  172. while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE));
  173. // Get the received data
  174. data = spi_i2s_data_receive(spi_periph);
  175. if(recv_ptr != RT_NULL)
  176. {
  177. *recv_ptr++ = data;
  178. }
  179. }
  180. DEBUG_PRINTF("spi poll transfer finsh\n");
  181. }
  182. else if(config->data_width <= 16)
  183. {
  184. const rt_uint16_t * send_ptr = message->send_buf;
  185. rt_uint16_t * recv_ptr = message->recv_buf;
  186. rt_uint32_t size = message->length;
  187. while(size--)
  188. {
  189. rt_uint16_t data = 0xFF;
  190. if(send_ptr != RT_NULL)
  191. {
  192. data = *send_ptr++;
  193. }
  194. //Wait until the transmit buffer is empty
  195. while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE));
  196. // Send the byte
  197. spi_i2s_data_transmit(spi_periph, data);
  198. //Wait until a data is received
  199. while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE));
  200. // Get the received data
  201. data = spi_i2s_data_receive(spi_periph);
  202. if(recv_ptr != RT_NULL)
  203. {
  204. *recv_ptr++ = data;
  205. }
  206. }
  207. }
  208. }
  209. /* release CS */
  210. if(message->cs_release)
  211. {
  212. rt_pin_write(gd32_cs_pin, PIN_HIGH);
  213. DEBUG_PRINTF("spi release cs\n");
  214. }
  215. return message->length;
  216. };
  217. int gd32_hw_spi_init(void)
  218. {
  219. int result = 0;
  220. #ifdef RT_USING_SPI0
  221. static struct rt_spi_bus spi_bus0;
  222. spi_bus0.parent.user_data = (void *)SPI0;
  223. result = rt_spi_bus_register(&spi_bus0, "spi0", &gd32_spi_ops);
  224. rcu_periph_clock_enable(RCU_GPIOA);
  225. rcu_periph_clock_enable(RCU_SPI0);
  226. /* SPI0_SCK(PA5), SPI0_MISO(PA6) and SPI0_MOSI(PA7) GPIO pin configuration */
  227. gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_5 | GPIO_PIN_7);
  228. gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_6);
  229. #endif
  230. #ifdef RT_USING_SPI1
  231. static struct rt_spi_bus spi_bus1;
  232. spi_bus1.parent.user_data = (void *)SPI1;
  233. result = rt_spi_bus_register(&spi_bus1, "spi1", &gd32_spi_ops);
  234. rcu_periph_clock_enable(RCU_SPI1);
  235. rcu_periph_clock_enable(RCU_GPIOB);
  236. /* SPI1_SCK(PB13), SPI1_MISO(PB14) and SPI1_MOSI(PB15) GPIO pin configuration */
  237. gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_13 | GPIO_PIN_15);
  238. gpio_init(GPIOB, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_14);
  239. #endif
  240. #ifdef RT_USING_SPI2
  241. static struct rt_spi_bus spi_bus2;
  242. spi_bus2.parent.user_data = (void *)SPI2;
  243. result = rt_spi_bus_register(&spi_bus2, "spi2", &gd32_spi_ops);
  244. rcu_periph_clock_enable(RCU_SPI2);
  245. rcu_periph_clock_enable(RCU_GPIOB);
  246. /* SPI2_SCK(PB3), SPI2_MISO(PB4) and SPI2_MOSI(PB5) GPIO pin configuration */
  247. gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_3 | GPIO_PIN_5);
  248. gpio_init(GPIOB, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_4);
  249. #endif
  250. return result;
  251. }
  252. INIT_BOARD_EXPORT(gd32_hw_spi_init);
  253. #endif