hw_ints.h 10 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202
  1. //*****************************************************************************
  2. //
  3. // hw_ints.h - Macros that define the interrupt assignment on Stellaris.
  4. //
  5. // Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
  6. // Software License Agreement
  7. //
  8. // Texas Instruments (TI) is supplying this software for use solely and
  9. // exclusively on TI's microcontroller products. The software is owned by
  10. // TI and/or its suppliers, and is protected under applicable copyright
  11. // laws. You may not combine this software with "viral" open-source
  12. // software in order to form a larger program.
  13. //
  14. // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
  15. // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
  16. // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  17. // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
  18. // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
  19. // DAMAGES, FOR ANY REASON WHATSOEVER.
  20. //
  21. // This is part of revision 8264 of the Stellaris Firmware Development Package.
  22. //
  23. //*****************************************************************************
  24. #ifndef __HW_INTS_H__
  25. #define __HW_INTS_H__
  26. //*****************************************************************************
  27. //
  28. // The following are defines for the fault assignments.
  29. //
  30. //*****************************************************************************
  31. #define FAULT_NMI 2 // NMI fault
  32. #define FAULT_HARD 3 // Hard fault
  33. #define FAULT_MPU 4 // MPU fault
  34. #define FAULT_BUS 5 // Bus fault
  35. #define FAULT_USAGE 6 // Usage fault
  36. #define FAULT_SVCALL 11 // SVCall
  37. #define FAULT_DEBUG 12 // Debug monitor
  38. #define FAULT_PENDSV 14 // PendSV
  39. #define FAULT_SYSTICK 15 // System Tick
  40. //*****************************************************************************
  41. //
  42. // The following are defines for the interrupt assignments.
  43. //
  44. //*****************************************************************************
  45. #define INT_GPIOA 16 // GPIO Port A
  46. #define INT_GPIOB 17 // GPIO Port B
  47. #define INT_GPIOC 18 // GPIO Port C
  48. #define INT_GPIOD 19 // GPIO Port D
  49. #define INT_GPIOE 20 // GPIO Port E
  50. #define INT_UART0 21 // UART0 Rx and Tx
  51. #define INT_UART1 22 // UART1 Rx and Tx
  52. #define INT_SSI0 23 // SSI0 Rx and Tx
  53. #define INT_I2C0 24 // I2C0 Master and Slave
  54. #define INT_PWM0_FAULT 25 // PWM0 Fault
  55. #define INT_PWM0_0 26 // PWM0 Generator 0
  56. #define INT_PWM0_1 27 // PWM0 Generator 1
  57. #define INT_PWM0_2 28 // PWM0 Generator 2
  58. #define INT_QEI0 29 // Quadrature Encoder 0
  59. #define INT_ADC0SS0 30 // ADC0 Sequence 0
  60. #define INT_ADC0SS1 31 // ADC0 Sequence 1
  61. #define INT_ADC0SS2 32 // ADC0 Sequence 2
  62. #define INT_ADC0SS3 33 // ADC0 Sequence 3
  63. #define INT_WATCHDOG 34 // Watchdog timer
  64. #define INT_TIMER0A 35 // Timer 0 subtimer A
  65. #define INT_TIMER0B 36 // Timer 0 subtimer B
  66. #define INT_TIMER1A 37 // Timer 1 subtimer A
  67. #define INT_TIMER1B 38 // Timer 1 subtimer B
  68. #define INT_TIMER2A 39 // Timer 2 subtimer A
  69. #define INT_TIMER2B 40 // Timer 2 subtimer B
  70. #define INT_COMP0 41 // Analog Comparator 0
  71. #define INT_COMP1 42 // Analog Comparator 1
  72. #define INT_COMP2 43 // Analog Comparator 2
  73. #define INT_SYSCTL 44 // System Control (PLL, OSC, BO)
  74. #define INT_FLASH 45 // FLASH Control
  75. #define INT_GPIOF 46 // GPIO Port F
  76. #define INT_GPIOG 47 // GPIO Port G
  77. #define INT_GPIOH 48 // GPIO Port H
  78. #define INT_UART2 49 // UART2 Rx and Tx
  79. #define INT_SSI1 50 // SSI1 Rx and Tx
  80. #define INT_TIMER3A 51 // Timer 3 subtimer A
  81. #define INT_TIMER3B 52 // Timer 3 subtimer B
  82. #define INT_I2C1 53 // I2C1 Master and Slave
  83. #define INT_QEI1 54 // Quadrature Encoder 1
  84. #define INT_CAN0 55 // CAN0
  85. #define INT_CAN1 56 // CAN1
  86. #define INT_CAN2 57 // CAN2
  87. #define INT_ETH 58 // Ethernet
  88. #define INT_HIBERNATE 59 // Hibernation module
  89. #define INT_USB0 60 // USB 0 Controller
  90. #define INT_PWM0_3 61 // PWM0 Generator 3
  91. #define INT_UDMA 62 // uDMA controller
  92. #define INT_UDMAERR 63 // uDMA Error
  93. #define INT_ADC1SS0 64 // ADC1 Sequence 0
  94. #define INT_ADC1SS1 65 // ADC1 Sequence 1
  95. #define INT_ADC1SS2 66 // ADC1 Sequence 2
  96. #define INT_ADC1SS3 67 // ADC1 Sequence 3
  97. #define INT_I2S0 68 // I2S0
  98. #define INT_EPI0 69 // EPI0
  99. #define INT_GPIOJ 70 // GPIO Port J
  100. #define INT_GPIOK 71 // GPIO Port K
  101. #define INT_GPIOL 72 // GPIO Port L
  102. #define INT_SSI2 73 // SSI2
  103. #define INT_SSI3 74 // SSI3
  104. #define INT_UART3 75 // UART3
  105. #define INT_UART4 76 // UART4
  106. #define INT_UART5 77 // UART5
  107. #define INT_UART6 78 // UART6
  108. #define INT_UART7 79 // UART7
  109. #define INT_I2C2 84 // I2C2
  110. #define INT_I2C3 85 // I2C3
  111. #define INT_TIMER4A 86 // Timer 4A
  112. #define INT_TIMER4B 87 // Timer 4B
  113. #define INT_TIMER5A 108 // Timer 5A
  114. #define INT_TIMER5B 109 // Timer 5B
  115. #define INT_WTIMER0A 110 // Wide Timer 0A
  116. #define INT_WTIMER0B 111 // Wide Timer 0B
  117. #define INT_WTIMER1A 112 // Wide Timer 1A
  118. #define INT_WTIMER1B 113 // Wide Timer 1B
  119. #define INT_WTIMER2A 114 // Wide Timer 2A
  120. #define INT_WTIMER2B 115 // Wide Timer 2B
  121. #define INT_WTIMER3A 116 // Wide Timer 3A
  122. #define INT_WTIMER3B 117 // Wide Timer 3B
  123. #define INT_WTIMER4A 118 // Wide Timer 4A
  124. #define INT_WTIMER4B 119 // Wide Timer 4B
  125. #define INT_WTIMER5A 120 // Wide Timer 5A
  126. #define INT_WTIMER5B 121 // Wide Timer 5B
  127. #define INT_SYSEXC 122 // System Exception (imprecise)
  128. #define INT_PECI0 123 // PECI 0
  129. #define INT_LPC0 124 // LPC 0
  130. #define INT_I2C4 125 // I2C4
  131. #define INT_I2C5 126 // I2C5
  132. #define INT_GPIOM 127 // GPIO Port M
  133. #define INT_GPION 128 // GPIO Port N
  134. #define INT_FAN0 130 // FAN 0
  135. #define INT_GPIOP0 132 // GPIO Port P (Summary or P0)
  136. #define INT_GPIOP1 133 // GPIO Port P1
  137. #define INT_GPIOP2 134 // GPIO Port P2
  138. #define INT_GPIOP3 135 // GPIO Port P3
  139. #define INT_GPIOP4 136 // GPIO Port P4
  140. #define INT_GPIOP5 137 // GPIO Port P5
  141. #define INT_GPIOP6 138 // GPIO Port P6
  142. #define INT_GPIOP7 139 // GPIO Port P7
  143. #define INT_GPIOQ0 140 // GPIO Port Q (Summary or Q0)
  144. #define INT_GPIOQ1 141 // GPIO Port Q1
  145. #define INT_GPIOQ2 142 // GPIO Port Q2
  146. #define INT_GPIOQ3 143 // GPIO Port Q3
  147. #define INT_GPIOQ4 144 // GPIO Port Q4
  148. #define INT_GPIOQ5 145 // GPIO Port Q5
  149. #define INT_GPIOQ6 146 // GPIO Port Q6
  150. #define INT_GPIOQ7 147 // GPIO Port Q7
  151. #define INT_PWM1_0 150 // PWM1 Generator 0
  152. #define INT_PWM1_1 151 // PWM1 Generator 1
  153. #define INT_PWM1_2 152 // PWM1 Generator 2
  154. #define INT_PWM1_3 153 // PWM1 Generator 3
  155. #define INT_PWM1_FAULT 154 // PWM1 Fault
  156. //*****************************************************************************
  157. //
  158. // The following are defines for the total number of interrupts.
  159. //
  160. //*****************************************************************************
  161. #define NUM_INTERRUPTS 155
  162. //*****************************************************************************
  163. //
  164. // The following are defines for the total number of priority levels.
  165. //
  166. //*****************************************************************************
  167. #define NUM_PRIORITY 8
  168. #define NUM_PRIORITY_BITS 3
  169. //*****************************************************************************
  170. //
  171. // The following definitions are deprecated.
  172. //
  173. //*****************************************************************************
  174. #ifndef DEPRECATED
  175. //*****************************************************************************
  176. //
  177. // The following are deprecated defines for the interrupt assignments.
  178. //
  179. //*****************************************************************************
  180. #define INT_SSI 23 // SSI Rx and Tx
  181. #define INT_I2C 24 // I2C Master and Slave
  182. #define INT_PWM_FAULT 25 // PWM Fault
  183. #define INT_PWM0 26 // PWM Generator 0
  184. #define INT_PWM1 27 // PWM Generator 1
  185. #define INT_PWM2 28 // PWM Generator 2
  186. #define INT_QEI 29 // Quadrature Encoder
  187. #define INT_ADC0 30 // ADC Sequence 0
  188. #define INT_ADC1 31 // ADC Sequence 1
  189. #define INT_ADC2 32 // ADC Sequence 2
  190. #define INT_ADC3 33 // ADC Sequence 3
  191. #define INT_PWM3 61 // PWM Generator 3
  192. #endif
  193. #endif // __HW_INTS_H__