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stm32f1xx_hal_tim.h 80 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f1xx_hal_tim.h
  4. * @author MCD Application Team
  5. * @version V1.1.1
  6. * @date 12-May-2017
  7. * @brief Header file of TIM HAL module.
  8. ******************************************************************************
  9. * @attention
  10. *
  11. * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  12. *
  13. * Redistribution and use in source and binary forms, with or without modification,
  14. * are permitted provided that the following conditions are met:
  15. * 1. Redistributions of source code must retain the above copyright notice,
  16. * this list of conditions and the following disclaimer.
  17. * 2. Redistributions in binary form must reproduce the above copyright notice,
  18. * this list of conditions and the following disclaimer in the documentation
  19. * and/or other materials provided with the distribution.
  20. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  21. * may be used to endorse or promote products derived from this software
  22. * without specific prior written permission.
  23. *
  24. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34. *
  35. ******************************************************************************
  36. */
  37. /* Define to prevent recursive inclusion -------------------------------------*/
  38. #ifndef __STM32F1xx_HAL_TIM_H
  39. #define __STM32F1xx_HAL_TIM_H
  40. #ifdef __cplusplus
  41. extern "C" {
  42. #endif
  43. /* Includes ------------------------------------------------------------------*/
  44. #include "stm32f1xx_hal_def.h"
  45. /** @addtogroup STM32F1xx_HAL_Driver
  46. * @{
  47. */
  48. /** @addtogroup TIM
  49. * @{
  50. */
  51. /* Exported types ------------------------------------------------------------*/
  52. /** @defgroup TIM_Exported_Types TIM Exported Types
  53. * @{
  54. */
  55. /**
  56. * @brief TIM Time base Configuration Structure definition
  57. */
  58. typedef struct
  59. {
  60. uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
  61. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
  62. uint32_t CounterMode; /*!< Specifies the counter mode.
  63. This parameter can be a value of @ref TIM_Counter_Mode */
  64. uint32_t Period; /*!< Specifies the period value to be loaded into the active
  65. Auto-Reload Register at the next update event.
  66. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
  67. uint32_t ClockDivision; /*!< Specifies the clock division.
  68. This parameter can be a value of @ref TIM_ClockDivision */
  69. uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
  70. reaches zero, an update event is generated and counting restarts
  71. from the RCR value (N).
  72. This means in PWM mode that (N+1) corresponds to:
  73. - the number of PWM periods in edge-aligned mode
  74. - the number of half PWM period in center-aligned mode
  75. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
  76. @note This parameter is valid only for TIM1 and TIM8. */
  77. uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
  78. This parameter can be a value of @ref TIM_AutoReloadPreload */
  79. } TIM_Base_InitTypeDef;
  80. /**
  81. * @brief TIM Output Compare Configuration Structure definition
  82. */
  83. typedef struct
  84. {
  85. uint32_t OCMode; /*!< Specifies the TIM mode.
  86. This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
  87. uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
  88. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
  89. uint32_t OCPolarity; /*!< Specifies the output polarity.
  90. This parameter can be a value of @ref TIM_Output_Compare_Polarity */
  91. uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
  92. This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
  93. @note This parameter is valid only for TIM1 and TIM8. */
  94. uint32_t OCFastMode; /*!< Specifies the Fast mode state.
  95. This parameter can be a value of @ref TIM_Output_Fast_State
  96. @note This parameter is valid only in PWM1 and PWM2 mode. */
  97. uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
  98. This parameter can be a value of @ref TIM_Output_Compare_Idle_State
  99. @note This parameter is valid only for TIM1 and TIM8. */
  100. uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
  101. This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
  102. @note This parameter is valid only for TIM1 and TIM8. */
  103. } TIM_OC_InitTypeDef;
  104. /**
  105. * @brief TIM One Pulse Mode Configuration Structure definition
  106. */
  107. typedef struct
  108. {
  109. uint32_t OCMode; /*!< Specifies the TIM mode.
  110. This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
  111. uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
  112. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
  113. uint32_t OCPolarity; /*!< Specifies the output polarity.
  114. This parameter can be a value of @ref TIM_Output_Compare_Polarity */
  115. uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
  116. This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
  117. @note This parameter is valid only for TIM1 and TIM8. */
  118. uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
  119. This parameter can be a value of @ref TIM_Output_Compare_Idle_State
  120. @note This parameter is valid only for TIM1 and TIM8. */
  121. uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
  122. This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
  123. @note This parameter is valid only for TIM1 and TIM8. */
  124. uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
  125. This parameter can be a value of @ref TIM_Input_Capture_Polarity */
  126. uint32_t ICSelection; /*!< Specifies the input.
  127. This parameter can be a value of @ref TIM_Input_Capture_Selection */
  128. uint32_t ICFilter; /*!< Specifies the input capture filter.
  129. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
  130. } TIM_OnePulse_InitTypeDef;
  131. /**
  132. * @brief TIM Input Capture Configuration Structure definition
  133. */
  134. typedef struct
  135. {
  136. uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
  137. This parameter can be a value of @ref TIM_Input_Capture_Polarity */
  138. uint32_t ICSelection; /*!< Specifies the input.
  139. This parameter can be a value of @ref TIM_Input_Capture_Selection */
  140. uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
  141. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
  142. uint32_t ICFilter; /*!< Specifies the input capture filter.
  143. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
  144. } TIM_IC_InitTypeDef;
  145. /**
  146. * @brief TIM Encoder Configuration Structure definition
  147. */
  148. typedef struct
  149. {
  150. uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
  151. This parameter can be a value of @ref TIM_Encoder_Mode */
  152. uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
  153. This parameter can be a value of @ref TIM_Input_Capture_Polarity */
  154. uint32_t IC1Selection; /*!< Specifies the input.
  155. This parameter can be a value of @ref TIM_Input_Capture_Selection */
  156. uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
  157. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
  158. uint32_t IC1Filter; /*!< Specifies the input capture filter.
  159. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
  160. uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
  161. This parameter can be a value of @ref TIM_Input_Capture_Polarity */
  162. uint32_t IC2Selection; /*!< Specifies the input.
  163. This parameter can be a value of @ref TIM_Input_Capture_Selection */
  164. uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
  165. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
  166. uint32_t IC2Filter; /*!< Specifies the input capture filter.
  167. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
  168. } TIM_Encoder_InitTypeDef;
  169. /**
  170. * @brief TIM Clock Configuration Handle Structure definition
  171. */
  172. typedef struct
  173. {
  174. uint32_t ClockSource; /*!< TIM clock sources
  175. This parameter can be a value of @ref TIM_Clock_Source */
  176. uint32_t ClockPolarity; /*!< TIM clock polarity
  177. This parameter can be a value of @ref TIM_Clock_Polarity */
  178. uint32_t ClockPrescaler; /*!< TIM clock prescaler
  179. This parameter can be a value of @ref TIM_Clock_Prescaler */
  180. uint32_t ClockFilter; /*!< TIM clock filter
  181. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
  182. }TIM_ClockConfigTypeDef;
  183. /**
  184. * @brief TIM Clear Input Configuration Handle Structure definition
  185. */
  186. typedef struct
  187. {
  188. uint32_t ClearInputState; /*!< TIM clear Input state
  189. This parameter can be ENABLE or DISABLE */
  190. uint32_t ClearInputSource; /*!< TIM clear Input sources
  191. This parameter can be a value of @ref TIM_ClearInput_Source */
  192. uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
  193. This parameter can be a value of @ref TIM_ClearInput_Polarity */
  194. uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
  195. This parameter can be a value of @ref TIM_ClearInput_Prescaler */
  196. uint32_t ClearInputFilter; /*!< TIM Clear Input filter
  197. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
  198. }TIM_ClearInputConfigTypeDef;
  199. /**
  200. * @brief TIM Slave configuration Structure definition
  201. */
  202. typedef struct {
  203. uint32_t SlaveMode; /*!< Slave mode selection
  204. This parameter can be a value of @ref TIM_Slave_Mode */
  205. uint32_t InputTrigger; /*!< Input Trigger source
  206. This parameter can be a value of @ref TIM_Trigger_Selection */
  207. uint32_t TriggerPolarity; /*!< Input Trigger polarity
  208. This parameter can be a value of @ref TIM_Trigger_Polarity */
  209. uint32_t TriggerPrescaler; /*!< Input trigger prescaler
  210. This parameter can be a value of @ref TIM_Trigger_Prescaler */
  211. uint32_t TriggerFilter; /*!< Input trigger filter
  212. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
  213. }TIM_SlaveConfigTypeDef;
  214. /**
  215. * @brief HAL State structures definition
  216. */
  217. typedef enum
  218. {
  219. HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
  220. HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
  221. HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
  222. HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
  223. HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
  224. }HAL_TIM_StateTypeDef;
  225. /**
  226. * @brief HAL Active channel structures definition
  227. */
  228. typedef enum
  229. {
  230. HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
  231. HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
  232. HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
  233. HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
  234. HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
  235. }HAL_TIM_ActiveChannel;
  236. /**
  237. * @brief TIM Time Base Handle Structure definition
  238. */
  239. typedef struct
  240. {
  241. TIM_TypeDef *Instance; /*!< Register base address */
  242. TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
  243. HAL_TIM_ActiveChannel Channel; /*!< Active channel */
  244. DMA_HandleTypeDef *hdma[7U]; /*!< DMA Handlers array
  245. This array is accessed by a @ref TIM_DMA_Handle_index */
  246. HAL_LockTypeDef Lock; /*!< Locking object */
  247. __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
  248. }TIM_HandleTypeDef;
  249. /**
  250. * @}
  251. */
  252. /* Exported constants --------------------------------------------------------*/
  253. /** @defgroup TIM_Exported_Constants TIM Exported Constants
  254. * @{
  255. */
  256. /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
  257. * @{
  258. */
  259. #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */
  260. #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
  261. #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
  262. /**
  263. * @}
  264. */
  265. /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
  266. * @{
  267. */
  268. #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
  269. #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */
  270. /**
  271. * @}
  272. */
  273. /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
  274. * @{
  275. */
  276. #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */
  277. #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
  278. #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
  279. #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
  280. /**
  281. * @}
  282. */
  283. /** @defgroup TIM_Counter_Mode TIM Counter Mode
  284. * @{
  285. */
  286. #define TIM_COUNTERMODE_UP 0x00000000U
  287. #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
  288. #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
  289. #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
  290. #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
  291. /**
  292. * @}
  293. */
  294. /** @defgroup TIM_ClockDivision TIM ClockDivision
  295. * @{
  296. */
  297. #define TIM_CLOCKDIVISION_DIV1 0x00000000U
  298. #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
  299. #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
  300. /**
  301. * @}
  302. */
  303. /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
  304. * @{
  305. */
  306. #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x0000U /*!< TIMx_ARR register is not buffered */
  307. #define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /*!< TIMx_ARR register is buffered */
  308. /**
  309. * @}
  310. */
  311. /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
  312. * @{
  313. */
  314. #define TIM_OCMODE_TIMING 0x00000000U
  315. #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
  316. #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
  317. #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
  318. #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
  319. #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
  320. #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
  321. #define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
  322. /**
  323. * @}
  324. */
  325. /** @defgroup TIM_Output_Compare_State TIM Output Compare State
  326. * @{
  327. */
  328. #define TIM_OUTPUTSTATE_DISABLE 0x00000000U
  329. #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
  330. /**
  331. * @}
  332. */
  333. /** @defgroup TIM_Output_Fast_State TIM Output Fast State
  334. * @{
  335. */
  336. #define TIM_OCFAST_DISABLE 0x00000000U
  337. #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
  338. /**
  339. * @}
  340. */
  341. /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
  342. * @{
  343. */
  344. #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U
  345. #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
  346. /**
  347. * @}
  348. */
  349. /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
  350. * @{
  351. */
  352. #define TIM_OCPOLARITY_HIGH 0x00000000U
  353. #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
  354. /**
  355. * @}
  356. */
  357. /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
  358. * @{
  359. */
  360. #define TIM_OCNPOLARITY_HIGH 0x00000000U
  361. #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
  362. /**
  363. * @}
  364. */
  365. /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
  366. * @{
  367. */
  368. #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
  369. #define TIM_OCIDLESTATE_RESET 0x00000000U
  370. /**
  371. * @}
  372. */
  373. /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
  374. * @{
  375. */
  376. #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
  377. #define TIM_OCNIDLESTATE_RESET 0x00000000U
  378. /**
  379. * @}
  380. */
  381. /** @defgroup TIM_Channel TIM Channel
  382. * @{
  383. */
  384. #define TIM_CHANNEL_1 0x00000000U
  385. #define TIM_CHANNEL_2 0x00000004U
  386. #define TIM_CHANNEL_3 0x00000008U
  387. #define TIM_CHANNEL_4 0x0000000CU
  388. #define TIM_CHANNEL_ALL 0x00000018U
  389. /**
  390. * @}
  391. */
  392. /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
  393. * @{
  394. */
  395. #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
  396. #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
  397. /**
  398. * @}
  399. */
  400. /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
  401. * @{
  402. */
  403. #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
  404. connected to IC1, IC2, IC3 or IC4, respectively */
  405. #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
  406. connected to IC2, IC1, IC4 or IC3, respectively */
  407. #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
  408. /**
  409. * @}
  410. */
  411. /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
  412. * @{
  413. */
  414. #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */
  415. #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
  416. #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
  417. #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
  418. /**
  419. * @}
  420. */
  421. /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
  422. * @{
  423. */
  424. #define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
  425. #define TIM_OPMODE_REPETITIVE 0x00000000U
  426. /**
  427. * @}
  428. */
  429. /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
  430. * @{
  431. */
  432. #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
  433. #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
  434. #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
  435. /**
  436. * @}
  437. */
  438. /** @defgroup TIM_Interrupt_definition TIM Interrupt Definition
  439. * @{
  440. */
  441. #define TIM_IT_UPDATE (TIM_DIER_UIE)
  442. #define TIM_IT_CC1 (TIM_DIER_CC1IE)
  443. #define TIM_IT_CC2 (TIM_DIER_CC2IE)
  444. #define TIM_IT_CC3 (TIM_DIER_CC3IE)
  445. #define TIM_IT_CC4 (TIM_DIER_CC4IE)
  446. #define TIM_IT_COM (TIM_DIER_COMIE)
  447. #define TIM_IT_TRIGGER (TIM_DIER_TIE)
  448. #define TIM_IT_BREAK (TIM_DIER_BIE)
  449. /**
  450. * @}
  451. */
  452. /** @defgroup TIM_Commutation_Source TIM Commutation Source
  453. * @{
  454. */
  455. #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
  456. #define TIM_COMMUTATION_SOFTWARE 0x00000000U
  457. /**
  458. * @}
  459. */
  460. /** @defgroup TIM_DMA_sources TIM DMA Sources
  461. * @{
  462. */
  463. #define TIM_DMA_UPDATE (TIM_DIER_UDE)
  464. #define TIM_DMA_CC1 (TIM_DIER_CC1DE)
  465. #define TIM_DMA_CC2 (TIM_DIER_CC2DE)
  466. #define TIM_DMA_CC3 (TIM_DIER_CC3DE)
  467. #define TIM_DMA_CC4 (TIM_DIER_CC4DE)
  468. #define TIM_DMA_COM (TIM_DIER_COMDE)
  469. #define TIM_DMA_TRIGGER (TIM_DIER_TDE)
  470. /**
  471. * @}
  472. */
  473. /** @defgroup TIM_Event_Source TIM Event Source
  474. * @{
  475. */
  476. #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
  477. #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
  478. #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
  479. #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
  480. #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
  481. #define TIM_EVENTSOURCE_COM TIM_EGR_COMG
  482. #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
  483. #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
  484. /**
  485. * @}
  486. */
  487. /** @defgroup TIM_Flag_definition TIM Flag Definition
  488. * @{
  489. */
  490. #define TIM_FLAG_UPDATE (TIM_SR_UIF)
  491. #define TIM_FLAG_CC1 (TIM_SR_CC1IF)
  492. #define TIM_FLAG_CC2 (TIM_SR_CC2IF)
  493. #define TIM_FLAG_CC3 (TIM_SR_CC3IF)
  494. #define TIM_FLAG_CC4 (TIM_SR_CC4IF)
  495. #define TIM_FLAG_COM (TIM_SR_COMIF)
  496. #define TIM_FLAG_TRIGGER (TIM_SR_TIF)
  497. #define TIM_FLAG_BREAK (TIM_SR_BIF)
  498. #define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
  499. #define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
  500. #define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
  501. #define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
  502. /**
  503. * @}
  504. */
  505. /** @defgroup TIM_Clock_Source TIM Clock Source
  506. * @{
  507. */
  508. #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
  509. #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
  510. #define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
  511. #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
  512. #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
  513. #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
  514. #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
  515. #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
  516. #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
  517. #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
  518. /**
  519. * @}
  520. */
  521. /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
  522. * @{
  523. */
  524. #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
  525. #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
  526. #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
  527. #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
  528. #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
  529. /**
  530. * @}
  531. */
  532. /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
  533. * @{
  534. */
  535. #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
  536. #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
  537. #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
  538. #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
  539. /**
  540. * @}
  541. */
  542. /** @defgroup TIM_ClearInput_Source TIM ClearInput Source
  543. * @{
  544. */
  545. #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U
  546. #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U
  547. /**
  548. * @}
  549. */
  550. /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
  551. * @{
  552. */
  553. #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
  554. #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
  555. /**
  556. * @}
  557. */
  558. /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
  559. * @{
  560. */
  561. #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
  562. #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
  563. #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
  564. #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
  565. /**
  566. * @}
  567. */
  568. /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state
  569. * @{
  570. */
  571. #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
  572. #define TIM_OSSR_DISABLE 0x00000000U
  573. /**
  574. * @}
  575. */
  576. /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state
  577. * @{
  578. */
  579. #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
  580. #define TIM_OSSI_DISABLE 0x00000000U
  581. /**
  582. * @}
  583. */
  584. /** @defgroup TIM_Lock_level TIM Lock level
  585. * @{
  586. */
  587. #define TIM_LOCKLEVEL_OFF 0x00000000U
  588. #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
  589. #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
  590. #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
  591. /**
  592. * @}
  593. */
  594. /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable Disable
  595. * @{
  596. */
  597. #define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
  598. #define TIM_BREAK_DISABLE 0x00000000U
  599. /**
  600. * @}
  601. */
  602. /** @defgroup TIM_Break_Polarity TIM Break Input Polarity
  603. * @{
  604. */
  605. #define TIM_BREAKPOLARITY_LOW 0x00000000U
  606. #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
  607. /**
  608. * @}
  609. */
  610. /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
  611. * @{
  612. */
  613. #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
  614. #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
  615. /**
  616. * @}
  617. */
  618. /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
  619. * @{
  620. */
  621. #define TIM_TRGO_RESET 0x00000000U
  622. #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
  623. #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
  624. #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
  625. #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
  626. #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
  627. #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
  628. #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
  629. /**
  630. * @}
  631. */
  632. /** @defgroup TIM_Slave_Mode TIM Slave Mode
  633. * @{
  634. */
  635. #define TIM_SLAVEMODE_DISABLE 0x00000000U
  636. #define TIM_SLAVEMODE_RESET 0x00000004U
  637. #define TIM_SLAVEMODE_GATED 0x00000005U
  638. #define TIM_SLAVEMODE_TRIGGER 0x00000006U
  639. #define TIM_SLAVEMODE_EXTERNAL1 0x00000007U
  640. /**
  641. * @}
  642. */
  643. /** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
  644. * @{
  645. */
  646. #define TIM_MASTERSLAVEMODE_ENABLE 0x00000080U
  647. #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U
  648. /**
  649. * @}
  650. */
  651. /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
  652. * @{
  653. */
  654. #define TIM_TS_ITR0 0x00000000U
  655. #define TIM_TS_ITR1 0x00000010U
  656. #define TIM_TS_ITR2 0x00000020U
  657. #define TIM_TS_ITR3 0x00000030U
  658. #define TIM_TS_TI1F_ED 0x00000040U
  659. #define TIM_TS_TI1FP1 0x00000050U
  660. #define TIM_TS_TI2FP2 0x00000060U
  661. #define TIM_TS_ETRF 0x00000070U
  662. #define TIM_TS_NONE 0x0000FFFFU
  663. /**
  664. * @}
  665. */
  666. /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
  667. * @{
  668. */
  669. #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
  670. #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
  671. #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
  672. #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
  673. #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
  674. /**
  675. * @}
  676. */
  677. /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
  678. * @{
  679. */
  680. #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
  681. #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
  682. #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
  683. #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
  684. /**
  685. * @}
  686. */
  687. /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
  688. * @{
  689. */
  690. #define TIM_TI1SELECTION_CH1 0x00000000U
  691. #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
  692. /**
  693. * @}
  694. */
  695. /** @defgroup TIM_DMA_Base_address TIM DMA Base Address
  696. * @{
  697. */
  698. #define TIM_DMABASE_CR1 0x00000000U
  699. #define TIM_DMABASE_CR2 0x00000001U
  700. #define TIM_DMABASE_SMCR 0x00000002U
  701. #define TIM_DMABASE_DIER 0x00000003U
  702. #define TIM_DMABASE_SR 0x00000004U
  703. #define TIM_DMABASE_EGR 0x00000005U
  704. #define TIM_DMABASE_CCMR1 0x00000006U
  705. #define TIM_DMABASE_CCMR2 0x00000007U
  706. #define TIM_DMABASE_CCER 0x00000008U
  707. #define TIM_DMABASE_CNT 0x00000009U
  708. #define TIM_DMABASE_PSC 0x0000000AU
  709. #define TIM_DMABASE_ARR 0x0000000BU
  710. #define TIM_DMABASE_RCR 0x0000000CU
  711. #define TIM_DMABASE_CCR1 0x0000000DU
  712. #define TIM_DMABASE_CCR2 0x0000000EU
  713. #define TIM_DMABASE_CCR3 0x0000000FU
  714. #define TIM_DMABASE_CCR4 0x00000010U
  715. #define TIM_DMABASE_BDTR 0x00000011U
  716. #define TIM_DMABASE_DCR 0x00000012U
  717. /**
  718. * @}
  719. */
  720. /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
  721. * @{
  722. */
  723. #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U
  724. #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U
  725. #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U
  726. #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U
  727. #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U
  728. #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U
  729. #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U
  730. #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U
  731. #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U
  732. #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U
  733. #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U
  734. #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U
  735. #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U
  736. #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U
  737. #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U
  738. #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U
  739. #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U
  740. #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U
  741. /**
  742. * @}
  743. */
  744. /** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index
  745. * @{
  746. */
  747. #define TIM_DMA_ID_UPDATE ((uint16_t)0x0) /*!< Index of the DMA handle used for Update DMA requests */
  748. #define TIM_DMA_ID_CC1 ((uint16_t)0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
  749. #define TIM_DMA_ID_CC2 ((uint16_t)0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
  750. #define TIM_DMA_ID_CC3 ((uint16_t)0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
  751. #define TIM_DMA_ID_CC4 ((uint16_t)0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
  752. #define TIM_DMA_ID_COMMUTATION ((uint16_t)0x5) /*!< Index of the DMA handle used for Commutation DMA requests */
  753. #define TIM_DMA_ID_TRIGGER ((uint16_t)0x6) /*!< Index of the DMA handle used for Trigger DMA requests */
  754. /**
  755. * @}
  756. */
  757. /** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State
  758. * @{
  759. */
  760. #define TIM_CCx_ENABLE 0x00000001U
  761. #define TIM_CCx_DISABLE 0x00000000U
  762. #define TIM_CCxN_ENABLE 0x00000004U
  763. #define TIM_CCxN_DISABLE 0x00000000U
  764. /**
  765. * @}
  766. */
  767. /**
  768. * @}
  769. */
  770. /* Private Constants -----------------------------------------------------------*/
  771. /** @defgroup TIM_Private_Constants TIM Private Constants
  772. * @{
  773. */
  774. /* The counter of a timer instance is disabled only if all the CCx and CCxN
  775. channels have been disabled */
  776. #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
  777. #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
  778. /**
  779. * @}
  780. */
  781. /* Private Macros -----------------------------------------------------------*/
  782. /** @defgroup TIM_Private_Macros TIM Private Macros
  783. * @{
  784. */
  785. #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
  786. ((MODE) == TIM_COUNTERMODE_DOWN) || \
  787. ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
  788. ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
  789. ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
  790. #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
  791. ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
  792. ((DIV) == TIM_CLOCKDIVISION_DIV4))
  793. #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
  794. ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
  795. #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
  796. ((MODE) == TIM_OCMODE_PWM2))
  797. #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
  798. ((MODE) == TIM_OCMODE_ACTIVE) || \
  799. ((MODE) == TIM_OCMODE_INACTIVE) || \
  800. ((MODE) == TIM_OCMODE_TOGGLE) || \
  801. ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
  802. ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
  803. #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
  804. ((STATE) == TIM_OCFAST_ENABLE))
  805. #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
  806. ((POLARITY) == TIM_OCPOLARITY_LOW))
  807. #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
  808. ((POLARITY) == TIM_OCNPOLARITY_LOW))
  809. #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
  810. ((STATE) == TIM_OCIDLESTATE_RESET))
  811. #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
  812. ((STATE) == TIM_OCNIDLESTATE_RESET))
  813. #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
  814. ((CHANNEL) == TIM_CHANNEL_2) || \
  815. ((CHANNEL) == TIM_CHANNEL_3) || \
  816. ((CHANNEL) == TIM_CHANNEL_4) || \
  817. ((CHANNEL) == TIM_CHANNEL_ALL))
  818. #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
  819. ((CHANNEL) == TIM_CHANNEL_2))
  820. #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
  821. ((CHANNEL) == TIM_CHANNEL_2) || \
  822. ((CHANNEL) == TIM_CHANNEL_3))
  823. #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
  824. ((POLARITY) == TIM_ICPOLARITY_FALLING))
  825. #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
  826. ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
  827. ((SELECTION) == TIM_ICSELECTION_TRC))
  828. #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
  829. ((PRESCALER) == TIM_ICPSC_DIV2) || \
  830. ((PRESCALER) == TIM_ICPSC_DIV4) || \
  831. ((PRESCALER) == TIM_ICPSC_DIV8))
  832. #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
  833. ((MODE) == TIM_OPMODE_REPETITIVE))
  834. #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
  835. ((MODE) == TIM_ENCODERMODE_TI2) || \
  836. ((MODE) == TIM_ENCODERMODE_TI12))
  837. #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
  838. #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
  839. #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
  840. ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
  841. ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
  842. ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
  843. ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
  844. ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
  845. ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
  846. ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
  847. ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
  848. ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
  849. #define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
  850. ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
  851. ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
  852. ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
  853. ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
  854. #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
  855. ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
  856. ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
  857. ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
  858. #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
  859. #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) || \
  860. ((SOURCE) == TIM_CLEARINPUTSOURCE_NONE))
  861. #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
  862. ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
  863. #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
  864. ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
  865. ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
  866. ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
  867. #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
  868. #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
  869. ((STATE) == TIM_OSSR_DISABLE))
  870. #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
  871. ((STATE) == TIM_OSSI_DISABLE))
  872. #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
  873. ((LEVEL) == TIM_LOCKLEVEL_1) || \
  874. ((LEVEL) == TIM_LOCKLEVEL_2) || \
  875. ((LEVEL) == TIM_LOCKLEVEL_3))
  876. #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
  877. ((STATE) == TIM_BREAK_DISABLE))
  878. #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
  879. ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
  880. #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
  881. ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
  882. #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
  883. ((SOURCE) == TIM_TRGO_ENABLE) || \
  884. ((SOURCE) == TIM_TRGO_UPDATE) || \
  885. ((SOURCE) == TIM_TRGO_OC1) || \
  886. ((SOURCE) == TIM_TRGO_OC1REF) || \
  887. ((SOURCE) == TIM_TRGO_OC2REF) || \
  888. ((SOURCE) == TIM_TRGO_OC3REF) || \
  889. ((SOURCE) == TIM_TRGO_OC4REF))
  890. #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
  891. ((MODE) == TIM_SLAVEMODE_GATED) || \
  892. ((MODE) == TIM_SLAVEMODE_RESET) || \
  893. ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
  894. ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
  895. #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
  896. ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
  897. #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
  898. ((SELECTION) == TIM_TS_ITR1) || \
  899. ((SELECTION) == TIM_TS_ITR2) || \
  900. ((SELECTION) == TIM_TS_ITR3) || \
  901. ((SELECTION) == TIM_TS_TI1F_ED) || \
  902. ((SELECTION) == TIM_TS_TI1FP1) || \
  903. ((SELECTION) == TIM_TS_TI2FP2) || \
  904. ((SELECTION) == TIM_TS_ETRF))
  905. #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
  906. ((SELECTION) == TIM_TS_ITR1) || \
  907. ((SELECTION) == TIM_TS_ITR2) || \
  908. ((SELECTION) == TIM_TS_ITR3) || \
  909. ((SELECTION) == TIM_TS_NONE))
  910. #define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
  911. ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
  912. ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
  913. ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
  914. ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
  915. #define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
  916. ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
  917. ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
  918. ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
  919. #define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
  920. #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
  921. ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
  922. #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
  923. ((BASE) == TIM_DMABASE_CR2) || \
  924. ((BASE) == TIM_DMABASE_SMCR) || \
  925. ((BASE) == TIM_DMABASE_DIER) || \
  926. ((BASE) == TIM_DMABASE_SR) || \
  927. ((BASE) == TIM_DMABASE_EGR) || \
  928. ((BASE) == TIM_DMABASE_CCMR1) || \
  929. ((BASE) == TIM_DMABASE_CCMR2) || \
  930. ((BASE) == TIM_DMABASE_CCER) || \
  931. ((BASE) == TIM_DMABASE_CNT) || \
  932. ((BASE) == TIM_DMABASE_PSC) || \
  933. ((BASE) == TIM_DMABASE_ARR) || \
  934. ((BASE) == TIM_DMABASE_RCR) || \
  935. ((BASE) == TIM_DMABASE_CCR1) || \
  936. ((BASE) == TIM_DMABASE_CCR2) || \
  937. ((BASE) == TIM_DMABASE_CCR3) || \
  938. ((BASE) == TIM_DMABASE_CCR4) || \
  939. ((BASE) == TIM_DMABASE_BDTR) || \
  940. ((BASE) == TIM_DMABASE_DCR))
  941. #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \
  942. ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
  943. ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
  944. ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
  945. ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
  946. ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
  947. ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
  948. ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
  949. ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
  950. ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
  951. ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
  952. ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
  953. ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
  954. ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
  955. ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
  956. ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
  957. ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
  958. ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
  959. #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
  960. /** @brief Set TIM IC prescaler
  961. * @param __HANDLE__: TIM handle
  962. * @param __CHANNEL__: specifies TIM Channel
  963. * @param __ICPSC__: specifies the prescaler value.
  964. * @retval None
  965. */
  966. #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
  967. (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
  968. ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
  969. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
  970. ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
  971. /** @brief Reset TIM IC prescaler
  972. * @param __HANDLE__: TIM handle
  973. * @param __CHANNEL__: specifies TIM Channel
  974. * @retval None
  975. */
  976. #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
  977. (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
  978. ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
  979. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
  980. ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
  981. /** @brief Set TIM IC polarity
  982. * @param __HANDLE__: TIM handle
  983. * @param __CHANNEL__: specifies TIM Channel
  984. * @param __POLARITY__: specifies TIM Channel Polarity
  985. * @retval None
  986. */
  987. #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
  988. (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
  989. ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
  990. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
  991. ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U) & TIM_CCER_CC4P)))
  992. /** @brief Reset TIM IC polarity
  993. * @param __HANDLE__: TIM handle
  994. * @param __CHANNEL__: specifies TIM Channel
  995. * @retval None
  996. */
  997. #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
  998. (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
  999. ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
  1000. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
  1001. ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
  1002. /**
  1003. * @}
  1004. */
  1005. /* Private Functions --------------------------------------------------------*/
  1006. /** @addtogroup TIM_Private_Functions
  1007. * @{
  1008. */
  1009. void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
  1010. void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
  1011. void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
  1012. void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
  1013. void TIM_DMAError(DMA_HandleTypeDef *hdma);
  1014. void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
  1015. void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
  1016. /**
  1017. * @}
  1018. */
  1019. /* Exported macros -----------------------------------------------------------*/
  1020. /** @defgroup TIM_Exported_Macros TIM Exported Macros
  1021. * @{
  1022. */
  1023. /** @brief Reset TIM handle state
  1024. * @param __HANDLE__: TIM handle.
  1025. * @retval None
  1026. */
  1027. #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
  1028. /**
  1029. * @brief Enable the TIM peripheral.
  1030. * @param __HANDLE__: TIM handle
  1031. * @retval None
  1032. */
  1033. #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
  1034. /**
  1035. * @brief Enable the TIM main Output.
  1036. * @param __HANDLE__: TIM handle
  1037. * @retval None
  1038. */
  1039. #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
  1040. /**
  1041. * @brief Disable the TIM peripheral.
  1042. * @param __HANDLE__: TIM handle
  1043. * @retval None
  1044. */
  1045. #define __HAL_TIM_DISABLE(__HANDLE__) \
  1046. do { \
  1047. if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
  1048. { \
  1049. if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
  1050. { \
  1051. (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
  1052. } \
  1053. } \
  1054. } while(0U)
  1055. /* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
  1056. channels have been disabled */
  1057. /**
  1058. * @brief Disable the TIM main Output.
  1059. * @param __HANDLE__: TIM handle
  1060. * @retval None
  1061. * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
  1062. */
  1063. #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
  1064. do { \
  1065. if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
  1066. { \
  1067. if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
  1068. { \
  1069. (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
  1070. } \
  1071. } \
  1072. } while(0U)
  1073. /**
  1074. * @brief Disable the TIM main Output.
  1075. * @param __HANDLE__: TIM handle
  1076. * @retval None
  1077. * @note The Main Output Enable of a timer instance is disabled unconditionally
  1078. */
  1079. #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
  1080. /**
  1081. * @brief Enables the specified TIM interrupt.
  1082. * @param __HANDLE__: specifies the TIM Handle.
  1083. * @param __INTERRUPT__: specifies the TIM interrupt source to enable.
  1084. * This parameter can be one of the following values:
  1085. * @arg TIM_IT_UPDATE: Update interrupt
  1086. * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
  1087. * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
  1088. * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
  1089. * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
  1090. * @arg TIM_IT_COM: Commutation interrupt
  1091. * @arg TIM_IT_TRIGGER: Trigger interrupt
  1092. * @arg TIM_IT_BREAK: Break interrupt
  1093. * @retval None
  1094. */
  1095. #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
  1096. /**
  1097. * @brief Disables the specified TIM interrupt.
  1098. * @param __HANDLE__: specifies the TIM Handle.
  1099. * @param __INTERRUPT__: specifies the TIM interrupt source to disable.
  1100. * This parameter can be one of the following values:
  1101. * @arg TIM_IT_UPDATE: Update interrupt
  1102. * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
  1103. * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
  1104. * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
  1105. * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
  1106. * @arg TIM_IT_COM: Commutation interrupt
  1107. * @arg TIM_IT_TRIGGER: Trigger interrupt
  1108. * @arg TIM_IT_BREAK: Break interrupt
  1109. * @retval None
  1110. */
  1111. #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
  1112. /**
  1113. * @brief Enables the specified DMA request.
  1114. * @param __HANDLE__: specifies the TIM Handle.
  1115. * @param __DMA__: specifies the TIM DMA request to enable.
  1116. * This parameter can be one of the following values:
  1117. * @arg TIM_DMA_UPDATE: Update DMA request
  1118. * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
  1119. * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
  1120. * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
  1121. * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
  1122. * @arg TIM_DMA_COM: Commutation DMA request
  1123. * @arg TIM_DMA_TRIGGER: Trigger DMA request
  1124. * @retval None
  1125. */
  1126. #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
  1127. /**
  1128. * @brief Disables the specified DMA request.
  1129. * @param __HANDLE__: specifies the TIM Handle.
  1130. * @param __DMA__: specifies the TIM DMA request to disable.
  1131. * This parameter can be one of the following values:
  1132. * @arg TIM_DMA_UPDATE: Update DMA request
  1133. * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
  1134. * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
  1135. * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
  1136. * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
  1137. * @arg TIM_DMA_COM: Commutation DMA request
  1138. * @arg TIM_DMA_TRIGGER: Trigger DMA request
  1139. * @retval None
  1140. */
  1141. #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
  1142. /**
  1143. * @brief Checks whether the specified TIM interrupt flag is set or not.
  1144. * @param __HANDLE__: specifies the TIM Handle.
  1145. * @param __FLAG__: specifies the TIM interrupt flag to check.
  1146. * This parameter can be one of the following values:
  1147. * @arg TIM_FLAG_UPDATE: Update interrupt flag
  1148. * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
  1149. * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
  1150. * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
  1151. * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
  1152. * @arg TIM_FLAG_COM: Commutation interrupt flag
  1153. * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
  1154. * @arg TIM_FLAG_BREAK: Break interrupt flag
  1155. * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
  1156. * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
  1157. * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
  1158. * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
  1159. * @retval The new state of __FLAG__ (TRUE or FALSE).
  1160. */
  1161. #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
  1162. /**
  1163. * @brief Clears the specified TIM interrupt flag.
  1164. * @param __HANDLE__: specifies the TIM Handle.
  1165. * @param __FLAG__: specifies the TIM interrupt flag to clear.
  1166. * This parameter can be one of the following values:
  1167. * @arg TIM_FLAG_UPDATE: Update interrupt flag
  1168. * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
  1169. * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
  1170. * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
  1171. * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
  1172. * @arg TIM_FLAG_COM: Commutation interrupt flag
  1173. * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
  1174. * @arg TIM_FLAG_BREAK: Break interrupt flag
  1175. * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
  1176. * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
  1177. * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
  1178. * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
  1179. * @retval The new state of __FLAG__ (TRUE or FALSE).
  1180. */
  1181. #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
  1182. /**
  1183. * @brief Checks whether the specified TIM interrupt has occurred or not.
  1184. * @param __HANDLE__: TIM handle
  1185. * @param __INTERRUPT__: specifies the TIM interrupt source to check.
  1186. * @retval The state of TIM_IT (SET or RESET).
  1187. */
  1188. #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
  1189. /**
  1190. * @brief Clear the TIM interrupt pending bits
  1191. * @param __HANDLE__: TIM handle
  1192. * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
  1193. * @retval None
  1194. */
  1195. #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
  1196. /**
  1197. * @brief Indicates whether or not the TIM Counter is used as downcounter
  1198. * @param __HANDLE__: TIM handle.
  1199. * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
  1200. * @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder
  1201. mode.
  1202. */
  1203. #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))
  1204. /**
  1205. * @brief Sets the TIM active prescaler register value on update event.
  1206. * @param __HANDLE__: TIM handle.
  1207. * @param __PRESC__: specifies the active prescaler register new value.
  1208. * @retval None
  1209. */
  1210. #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
  1211. /**
  1212. * @brief Sets the TIM Capture Compare Register value on runtime without
  1213. * calling another time ConfigChannel function.
  1214. * @param __HANDLE__: TIM handle.
  1215. * @param __CHANNEL__ : TIM Channels to be configured.
  1216. * This parameter can be one of the following values:
  1217. * @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1218. * @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1219. * @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1220. * @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1221. * @param __COMPARE__: specifies the Capture Compare register new value.
  1222. * @retval None
  1223. */
  1224. #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
  1225. (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
  1226. /**
  1227. * @brief Gets the TIM Capture Compare Register value on runtime
  1228. * @param __HANDLE__: TIM handle.
  1229. * @param __CHANNEL__ : TIM Channel associated with the capture compare register
  1230. * This parameter can be one of the following values:
  1231. * @arg TIM_CHANNEL_1: get capture/compare 1 register value
  1232. * @arg TIM_CHANNEL_2: get capture/compare 2 register value
  1233. * @arg TIM_CHANNEL_3: get capture/compare 3 register value
  1234. * @arg TIM_CHANNEL_4: get capture/compare 4 register value
  1235. * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
  1236. */
  1237. #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
  1238. (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
  1239. /**
  1240. * @brief Sets the TIM Counter Register value on runtime.
  1241. * @param __HANDLE__: TIM handle.
  1242. * @param __COUNTER__: specifies the Counter register new value.
  1243. * @retval None
  1244. */
  1245. #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
  1246. /**
  1247. * @brief Gets the TIM Counter Register value on runtime.
  1248. * @param __HANDLE__: TIM handle.
  1249. * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
  1250. */
  1251. #define __HAL_TIM_GET_COUNTER(__HANDLE__) \
  1252. ((__HANDLE__)->Instance->CNT)
  1253. /**
  1254. * @brief Sets the TIM Autoreload Register value on runtime without calling
  1255. * another time any Init function.
  1256. * @param __HANDLE__: TIM handle.
  1257. * @param __AUTORELOAD__: specifies the Counter register new value.
  1258. * @retval None
  1259. */
  1260. #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
  1261. do{ \
  1262. (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
  1263. (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
  1264. } while(0U)
  1265. /**
  1266. * @brief Gets the TIM Autoreload Register value on runtime
  1267. * @param __HANDLE__: TIM handle.
  1268. * @retval @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
  1269. */
  1270. #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
  1271. ((__HANDLE__)->Instance->ARR)
  1272. /**
  1273. * @brief Sets the TIM Clock Division value on runtime without calling
  1274. * another time any Init function.
  1275. * @param __HANDLE__: TIM handle.
  1276. * @param __CKD__: specifies the clock division value.
  1277. * This parameter can be one of the following value:
  1278. * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
  1279. * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
  1280. * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
  1281. * @retval None
  1282. */
  1283. #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
  1284. do{ \
  1285. (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
  1286. (__HANDLE__)->Instance->CR1 |= (__CKD__); \
  1287. (__HANDLE__)->Init.ClockDivision = (__CKD__); \
  1288. } while(0U)
  1289. /**
  1290. * @brief Gets the TIM Clock Division value on runtime
  1291. * @param __HANDLE__: TIM handle.
  1292. * @retval The clock division can be one of the following values:
  1293. * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
  1294. * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
  1295. * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
  1296. */
  1297. #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
  1298. ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
  1299. /**
  1300. * @brief Sets the TIM Input Capture prescaler on runtime without calling
  1301. * another time HAL_TIM_IC_ConfigChannel() function.
  1302. * @param __HANDLE__: TIM handle.
  1303. * @param __CHANNEL__ : TIM Channels to be configured.
  1304. * This parameter can be one of the following values:
  1305. * @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1306. * @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1307. * @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1308. * @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1309. * @param __ICPSC__: specifies the Input Capture4 prescaler new value.
  1310. * This parameter can be one of the following values:
  1311. * @arg TIM_ICPSC_DIV1: no prescaler
  1312. * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
  1313. * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
  1314. * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
  1315. * @retval None
  1316. */
  1317. #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
  1318. do{ \
  1319. TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
  1320. TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
  1321. } while(0U)
  1322. /**
  1323. * @brief Gets the TIM Input Capture prescaler on runtime
  1324. * @param __HANDLE__: TIM handle.
  1325. * @param __CHANNEL__: TIM Channels to be configured.
  1326. * This parameter can be one of the following values:
  1327. * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
  1328. * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
  1329. * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
  1330. * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
  1331. * @retval The input capture prescaler can be one of the following values:
  1332. * @arg TIM_ICPSC_DIV1: no prescaler
  1333. * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
  1334. * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
  1335. * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
  1336. */
  1337. #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
  1338. (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
  1339. ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
  1340. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
  1341. (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
  1342. /**
  1343. * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
  1344. * @param __HANDLE__: TIM handle.
  1345. * @note When the USR bit of the TIMx_CR1 register is set, only counter
  1346. * overflow/underflow generates an update interrupt or DMA request (if
  1347. * enabled)
  1348. * @retval None
  1349. */
  1350. #define __HAL_TIM_URS_ENABLE(__HANDLE__) \
  1351. ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
  1352. /**
  1353. * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
  1354. * @param __HANDLE__: TIM handle.
  1355. * @note When the USR bit of the TIMx_CR1 register is reset, any of the
  1356. * following events generate an update interrupt or DMA request (if
  1357. * enabled):
  1358. * (+) Counter overflow/underflow
  1359. * (+) Setting the UG bit
  1360. * (+) Update generation through the slave mode controller
  1361. * @retval None
  1362. */
  1363. #define __HAL_TIM_URS_DISABLE(__HANDLE__) \
  1364. ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
  1365. /**
  1366. * @brief Sets the TIM Capture x input polarity on runtime.
  1367. * @param __HANDLE__: TIM handle.
  1368. * @param __CHANNEL__: TIM Channels to be configured.
  1369. * This parameter can be one of the following values:
  1370. * @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1371. * @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1372. * @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1373. * @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1374. * @param __POLARITY__: Polarity for TIx source
  1375. * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
  1376. * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
  1377. * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
  1378. * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
  1379. * @retval None
  1380. */
  1381. #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
  1382. do{ \
  1383. TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
  1384. TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
  1385. }while(0U)
  1386. /**
  1387. * @}
  1388. */
  1389. /* Include TIM HAL Extension module */
  1390. #include "stm32f1xx_hal_tim_ex.h"
  1391. /* Exported functions --------------------------------------------------------*/
  1392. /** @addtogroup TIM_Exported_Functions
  1393. * @{
  1394. */
  1395. /** @addtogroup TIM_Exported_Functions_Group1
  1396. * @{
  1397. */
  1398. /* Time Base functions ********************************************************/
  1399. HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
  1400. HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
  1401. void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
  1402. void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
  1403. /* Blocking mode: Polling */
  1404. HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
  1405. HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
  1406. /* Non-Blocking mode: Interrupt */
  1407. HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
  1408. HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
  1409. /* Non-Blocking mode: DMA */
  1410. HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
  1411. HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
  1412. /**
  1413. * @}
  1414. */
  1415. /** @addtogroup TIM_Exported_Functions_Group2
  1416. * @{
  1417. */
  1418. /* Timer Output Compare functions **********************************************/
  1419. HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
  1420. HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
  1421. void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
  1422. void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
  1423. /* Blocking mode: Polling */
  1424. HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
  1425. HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
  1426. /* Non-Blocking mode: Interrupt */
  1427. HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
  1428. HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
  1429. /* Non-Blocking mode: DMA */
  1430. HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
  1431. HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
  1432. /**
  1433. * @}
  1434. */
  1435. /** @addtogroup TIM_Exported_Functions_Group3
  1436. * @{
  1437. */
  1438. /* Timer PWM functions *********************************************************/
  1439. HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
  1440. HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
  1441. void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
  1442. void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
  1443. /* Blocking mode: Polling */
  1444. HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
  1445. HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
  1446. /* Non-Blocking mode: Interrupt */
  1447. HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
  1448. HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
  1449. /* Non-Blocking mode: DMA */
  1450. HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
  1451. HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
  1452. /**
  1453. * @}
  1454. */
  1455. /** @addtogroup TIM_Exported_Functions_Group4
  1456. * @{
  1457. */
  1458. /* Timer Input Capture functions ***********************************************/
  1459. HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
  1460. HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
  1461. void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
  1462. void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
  1463. /* Blocking mode: Polling */
  1464. HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
  1465. HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
  1466. /* Non-Blocking mode: Interrupt */
  1467. HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
  1468. HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
  1469. /* Non-Blocking mode: DMA */
  1470. HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
  1471. HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
  1472. /**
  1473. * @}
  1474. */
  1475. /** @addtogroup TIM_Exported_Functions_Group5
  1476. * @{
  1477. */
  1478. /* Timer One Pulse functions ***************************************************/
  1479. HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
  1480. HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
  1481. void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
  1482. void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
  1483. /* Blocking mode: Polling */
  1484. HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
  1485. HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
  1486. /* Non-Blocking mode: Interrupt */
  1487. HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
  1488. HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
  1489. /**
  1490. * @}
  1491. */
  1492. /** @addtogroup TIM_Exported_Functions_Group6
  1493. * @{
  1494. */
  1495. /* Timer Encoder functions *****************************************************/
  1496. HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
  1497. HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
  1498. void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
  1499. void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
  1500. /* Blocking mode: Polling */
  1501. HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
  1502. HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
  1503. /* Non-Blocking mode: Interrupt */
  1504. HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
  1505. HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
  1506. /* Non-Blocking mode: DMA */
  1507. HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
  1508. HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
  1509. /**
  1510. * @}
  1511. */
  1512. /** @addtogroup TIM_Exported_Functions_Group7
  1513. * @{
  1514. */
  1515. /* Interrupt Handler functions **********************************************/
  1516. void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
  1517. /**
  1518. * @}
  1519. */
  1520. /** @addtogroup TIM_Exported_Functions_Group8
  1521. * @{
  1522. */
  1523. /* Control functions *********************************************************/
  1524. HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
  1525. HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
  1526. HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
  1527. HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
  1528. HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
  1529. HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
  1530. HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
  1531. HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
  1532. HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
  1533. HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
  1534. uint32_t *BurstBuffer, uint32_t BurstLength);
  1535. HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
  1536. HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
  1537. uint32_t *BurstBuffer, uint32_t BurstLength);
  1538. HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
  1539. HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
  1540. uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
  1541. /**
  1542. * @}
  1543. */
  1544. /** @addtogroup TIM_Exported_Functions_Group9
  1545. * @{
  1546. */
  1547. /* Callback in non blocking modes (Interrupt and DMA) *************************/
  1548. void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
  1549. void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
  1550. void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
  1551. void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
  1552. void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
  1553. void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
  1554. /**
  1555. * @}
  1556. */
  1557. /** @addtogroup TIM_Exported_Functions_Group10
  1558. * @{
  1559. */
  1560. /* Peripheral State functions **************************************************/
  1561. HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
  1562. HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
  1563. HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
  1564. HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
  1565. HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
  1566. HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
  1567. /**
  1568. * @}
  1569. */
  1570. /**
  1571. * @}
  1572. */
  1573. /**
  1574. * @}
  1575. */
  1576. /**
  1577. * @}
  1578. */
  1579. #ifdef __cplusplus
  1580. }
  1581. #endif
  1582. #endif /* __STM32F1xx_HAL_TIM_H */
  1583. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/