stm32f1xx_hal_nand.c 61 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f1xx_hal_nand.c
  4. * @author MCD Application Team
  5. * @version V1.1.1
  6. * @date 12-May-2017
  7. * @brief NAND HAL module driver.
  8. * This file provides a generic firmware to drive NAND memories mounted
  9. * as external device.
  10. *
  11. @verbatim
  12. ==============================================================================
  13. ##### How to use this driver #####
  14. ==============================================================================
  15. [..]
  16. This driver is a generic layered driver which contains a set of APIs used to
  17. control NAND flash memories. It uses the FSMC layer functions to interface
  18. with NAND devices. This driver is used as follows:
  19. (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
  20. with control and timing parameters for both common and attribute spaces.
  21. (+) Read NAND flash memory maker and device IDs using the function
  22. HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
  23. structure declared by the function caller.
  24. (+) Access NAND flash memory by read/write operations using the functions
  25. HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(),
  26. HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(),
  27. HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(),
  28. HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b()
  29. to read/write page(s)/spare area(s). These functions use specific device
  30. information (Block, page size..) predefined by the user in the NAND_DeviceConfigTypeDef
  31. structure. The read/write address information is contained by the Nand_Address_Typedef
  32. structure passed as parameter.
  33. (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
  34. (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
  35. The erase block address information is contained in the Nand_Address_Typedef
  36. structure passed as parameter.
  37. (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
  38. (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
  39. HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
  40. feature or the function HAL_NAND_GetECC() to get the ECC correction code.
  41. (+) You can monitor the NAND device HAL state by calling the function
  42. HAL_NAND_GetState()
  43. [..]
  44. (@) This driver is a set of generic APIs which handle standard NAND flash operations.
  45. If a NAND flash device contains different operations and/or implementations,
  46. it should be implemented separately.
  47. @endverbatim
  48. ******************************************************************************
  49. * @attention
  50. *
  51. * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  52. *
  53. * Redistribution and use in source and binary forms, with or without modification,
  54. * are permitted provided that the following conditions are met:
  55. * 1. Redistributions of source code must retain the above copyright notice,
  56. * this list of conditions and the following disclaimer.
  57. * 2. Redistributions in binary form must reproduce the above copyright notice,
  58. * this list of conditions and the following disclaimer in the documentation
  59. * and/or other materials provided with the distribution.
  60. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  61. * may be used to endorse or promote products derived from this software
  62. * without specific prior written permission.
  63. *
  64. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  65. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  66. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  67. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  68. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  69. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  70. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  71. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  72. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  73. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  74. *
  75. ******************************************************************************
  76. */
  77. /* Includes ------------------------------------------------------------------*/
  78. #include "stm32f1xx_hal.h"
  79. /** @addtogroup STM32F1xx_HAL_Driver
  80. * @{
  81. */
  82. #ifdef HAL_NAND_MODULE_ENABLED
  83. #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
  84. /** @defgroup NAND NAND
  85. * @brief NAND HAL module driver
  86. * @{
  87. */
  88. /* Private typedef -----------------------------------------------------------*/
  89. /* Private define ------------------------------------------------------------*/
  90. /** @defgroup NAND_Private_Constants NAND Private Constants
  91. * @{
  92. */
  93. /**
  94. * @}
  95. */
  96. /* Private macro -------------------------------------------------------------*/
  97. /** @defgroup NAND_Private_Macros NAND Private Macros
  98. * @{
  99. */
  100. /**
  101. * @}
  102. */
  103. /* Private variables ---------------------------------------------------------*/
  104. /* Private function prototypes -----------------------------------------------*/
  105. /* Exported functions --------------------------------------------------------*/
  106. /** @defgroup NAND_Exported_Functions NAND Exported Functions
  107. * @{
  108. */
  109. /** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
  110. * @brief Initialization and Configuration functions
  111. *
  112. @verbatim
  113. ==============================================================================
  114. ##### NAND Initialization and de-initialization functions #####
  115. ==============================================================================
  116. [..]
  117. This section provides functions allowing to initialize/de-initialize
  118. the NAND memory
  119. @endverbatim
  120. * @{
  121. */
  122. /**
  123. * @brief Perform NAND memory Initialization sequence
  124. * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
  125. * the configuration information for NAND module.
  126. * @param ComSpace_Timing: pointer to Common space timing structure
  127. * @param AttSpace_Timing: pointer to Attribute space timing structure
  128. * @retval HAL status
  129. */
  130. HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
  131. {
  132. /* Check the NAND handle state */
  133. if(hnand == NULL)
  134. {
  135. return HAL_ERROR;
  136. }
  137. if(hnand->State == HAL_NAND_STATE_RESET)
  138. {
  139. /* Allocate lock resource and initialize it */
  140. hnand->Lock = HAL_UNLOCKED;
  141. /* Initialize the low level hardware (MSP) */
  142. HAL_NAND_MspInit(hnand);
  143. }
  144. /* Initialize NAND control Interface */
  145. FSMC_NAND_Init(hnand->Instance, &(hnand->Init));
  146. /* Initialize NAND common space timing Interface */
  147. FSMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
  148. /* Initialize NAND attribute space timing Interface */
  149. FSMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
  150. /* Enable the NAND device */
  151. __FSMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
  152. /* Update the NAND controller state */
  153. hnand->State = HAL_NAND_STATE_READY;
  154. return HAL_OK;
  155. }
  156. /**
  157. * @brief Perform NAND memory De-Initialization sequence
  158. * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
  159. * the configuration information for NAND module.
  160. * @retval HAL status
  161. */
  162. HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
  163. {
  164. /* Initialize the low level hardware (MSP) */
  165. HAL_NAND_MspDeInit(hnand);
  166. /* Configure the NAND registers with their reset values */
  167. FSMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
  168. /* Reset the NAND controller state */
  169. hnand->State = HAL_NAND_STATE_RESET;
  170. /* Release Lock */
  171. __HAL_UNLOCK(hnand);
  172. return HAL_OK;
  173. }
  174. /**
  175. * @brief NAND MSP Init
  176. * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
  177. * the configuration information for NAND module.
  178. * @retval None
  179. */
  180. __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
  181. {
  182. /* Prevent unused argument(s) compilation warning */
  183. UNUSED(hnand);
  184. /* NOTE : This function Should not be modified, when the callback is needed,
  185. the HAL_NAND_MspInit could be implemented in the user file
  186. */
  187. }
  188. /**
  189. * @brief NAND MSP DeInit
  190. * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
  191. * the configuration information for NAND module.
  192. * @retval None
  193. */
  194. __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
  195. {
  196. /* Prevent unused argument(s) compilation warning */
  197. UNUSED(hnand);
  198. /* NOTE : This function Should not be modified, when the callback is needed,
  199. the HAL_NAND_MspDeInit could be implemented in the user file
  200. */
  201. }
  202. /**
  203. * @brief This function handles NAND device interrupt request.
  204. * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
  205. * the configuration information for NAND module.
  206. * @retval HAL status
  207. */
  208. void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
  209. {
  210. /* Check NAND interrupt Rising edge flag */
  211. if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE))
  212. {
  213. /* NAND interrupt callback*/
  214. HAL_NAND_ITCallback(hnand);
  215. /* Clear NAND interrupt Rising edge pending bit */
  216. __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE);
  217. }
  218. /* Check NAND interrupt Level flag */
  219. if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL))
  220. {
  221. /* NAND interrupt callback*/
  222. HAL_NAND_ITCallback(hnand);
  223. /* Clear NAND interrupt Level pending bit */
  224. __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL);
  225. }
  226. /* Check NAND interrupt Falling edge flag */
  227. if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE))
  228. {
  229. /* NAND interrupt callback*/
  230. HAL_NAND_ITCallback(hnand);
  231. /* Clear NAND interrupt Falling edge pending bit */
  232. __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE);
  233. }
  234. /* Check NAND interrupt FIFO empty flag */
  235. if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT))
  236. {
  237. /* NAND interrupt callback*/
  238. HAL_NAND_ITCallback(hnand);
  239. /* Clear NAND interrupt FIFO empty pending bit */
  240. __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT);
  241. }
  242. }
  243. /**
  244. * @brief NAND interrupt feature callback
  245. * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
  246. * the configuration information for NAND module.
  247. * @retval None
  248. */
  249. __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
  250. {
  251. /* Prevent unused argument(s) compilation warning */
  252. UNUSED(hnand);
  253. /* NOTE : This function Should not be modified, when the callback is needed,
  254. the HAL_NAND_ITCallback could be implemented in the user file
  255. */
  256. }
  257. /**
  258. * @}
  259. */
  260. /** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
  261. * @brief Input Output and memory control functions
  262. *
  263. @verbatim
  264. ==============================================================================
  265. ##### NAND Input and Output functions #####
  266. ==============================================================================
  267. [..]
  268. This section provides functions allowing to use and control the NAND
  269. memory
  270. @endverbatim
  271. * @{
  272. */
  273. /**
  274. * @brief Read the NAND memory electronic signature
  275. * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
  276. * the configuration information for NAND module.
  277. * @param pNAND_ID: NAND ID structure
  278. * @retval HAL status
  279. */
  280. HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
  281. {
  282. __IO uint32_t data = 0U;
  283. __IO uint32_t data1 = 0U;
  284. uint32_t deviceaddress = 0U;
  285. /* Process Locked */
  286. __HAL_LOCK(hnand);
  287. /* Check the NAND controller state */
  288. if(hnand->State == HAL_NAND_STATE_BUSY)
  289. {
  290. return HAL_BUSY;
  291. }
  292. /* Identify the device address */
  293. if(hnand->Init.NandBank == FSMC_NAND_BANK2)
  294. {
  295. deviceaddress = NAND_DEVICE1;
  296. }
  297. else
  298. {
  299. deviceaddress = NAND_DEVICE2;
  300. }
  301. /* Update the NAND controller state */
  302. hnand->State = HAL_NAND_STATE_BUSY;
  303. /* Send Read ID command sequence */
  304. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID;
  305. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
  306. /* Read the electronic signature from NAND flash */
  307. if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8)
  308. {
  309. data = *(__IO uint32_t *)deviceaddress;
  310. /* Return the data read */
  311. pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
  312. pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);
  313. pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);
  314. pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);
  315. }
  316. else
  317. {
  318. data = *(__IO uint32_t *)deviceaddress;
  319. data1 = *((__IO uint32_t *)deviceaddress + 4U);
  320. /* Return the data read */
  321. pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
  322. pNAND_ID->Device_Id = ADDR_3RD_CYCLE(data);
  323. pNAND_ID->Third_Id = ADDR_1ST_CYCLE(data1);
  324. pNAND_ID->Fourth_Id = ADDR_3RD_CYCLE(data1);
  325. }
  326. /* Update the NAND controller state */
  327. hnand->State = HAL_NAND_STATE_READY;
  328. /* Process unlocked */
  329. __HAL_UNLOCK(hnand);
  330. return HAL_OK;
  331. }
  332. /**
  333. * @brief NAND memory reset
  334. * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
  335. * the configuration information for NAND module.
  336. * @retval HAL status
  337. */
  338. HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
  339. {
  340. uint32_t deviceaddress = 0U;
  341. /* Process Locked */
  342. __HAL_LOCK(hnand);
  343. /* Check the NAND controller state */
  344. if(hnand->State == HAL_NAND_STATE_BUSY)
  345. {
  346. return HAL_BUSY;
  347. }
  348. /* Identify the device address */
  349. if(hnand->Init.NandBank == FSMC_NAND_BANK2)
  350. {
  351. deviceaddress = NAND_DEVICE1;
  352. }
  353. else
  354. {
  355. deviceaddress = NAND_DEVICE2;
  356. }
  357. /* Update the NAND controller state */
  358. hnand->State = HAL_NAND_STATE_BUSY;
  359. /* Send NAND reset command */
  360. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
  361. /* Update the NAND controller state */
  362. hnand->State = HAL_NAND_STATE_READY;
  363. /* Process unlocked */
  364. __HAL_UNLOCK(hnand);
  365. return HAL_OK;
  366. }
  367. /**
  368. * @brief Configure the device: Enter the physical parameters of the device
  369. * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
  370. * the configuration information for NAND module.
  371. * @param pDeviceConfig : pointer to NAND_DeviceConfigTypeDef structure
  372. * @retval HAL status
  373. */
  374. HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
  375. {
  376. hnand->Config.PageSize = pDeviceConfig->PageSize;
  377. hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize;
  378. hnand->Config.BlockSize = pDeviceConfig->BlockSize;
  379. hnand->Config.BlockNbr = pDeviceConfig->BlockNbr;
  380. hnand->Config.PlaneSize = pDeviceConfig->PlaneSize;
  381. hnand->Config.PlaneNbr = pDeviceConfig->PlaneNbr;
  382. hnand->Config.ExtraCommandEnable = pDeviceConfig->ExtraCommandEnable;
  383. return HAL_OK;
  384. }
  385. /**
  386. * @brief Read Page(s) from NAND memory block (8-bits addressing)
  387. * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
  388. * the configuration information for NAND module.
  389. * @param pAddress : pointer to NAND address structure
  390. * @param pBuffer : pointer to destination read buffer
  391. * @param NumPageToRead : number of pages to read from block
  392. * @retval HAL status
  393. */
  394. HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
  395. {
  396. __IO uint32_t index = 0U;
  397. uint32_t tickstart = 0U;
  398. uint32_t deviceaddress = 0U, size = 0U, numPagesRead = 0U, nandaddress = 0U;
  399. /* Process Locked */
  400. __HAL_LOCK(hnand);
  401. /* Check the NAND controller state */
  402. if(hnand->State == HAL_NAND_STATE_BUSY)
  403. {
  404. return HAL_BUSY;
  405. }
  406. /* Identify the device address */
  407. if(hnand->Init.NandBank == FSMC_NAND_BANK2)
  408. {
  409. deviceaddress = NAND_DEVICE1;
  410. }
  411. else
  412. {
  413. deviceaddress = NAND_DEVICE2;
  414. }
  415. /* Update the NAND controller state */
  416. hnand->State = HAL_NAND_STATE_BUSY;
  417. /* NAND raw address calculation */
  418. nandaddress = ARRAY_ADDRESS(pAddress, hnand);
  419. /* Page(s) read loop */
  420. while((NumPageToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
  421. {
  422. /* update the buffer size */
  423. size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead);
  424. /* Send read page command sequence */
  425. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
  426. /* Cards with page size <= 512 bytes */
  427. if((hnand->Config.PageSize) <= 512U)
  428. {
  429. if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
  430. {
  431. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
  432. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  433. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  434. }
  435. else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
  436. {
  437. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
  438. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  439. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  440. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
  441. }
  442. }
  443. else /* (hnand->Config.PageSize) > 512 */
  444. {
  445. if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
  446. {
  447. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
  448. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
  449. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  450. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  451. }
  452. else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
  453. {
  454. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
  455. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
  456. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  457. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  458. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
  459. }
  460. }
  461. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
  462. /* Check if an extra command is needed for reading pages */
  463. if(hnand->Config.ExtraCommandEnable == ENABLE)
  464. {
  465. /* Get tick */
  466. tickstart = HAL_GetTick();
  467. /* Read status until NAND is ready */
  468. while(HAL_NAND_Read_Status(hnand) != NAND_READY)
  469. {
  470. if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
  471. {
  472. return HAL_TIMEOUT;
  473. }
  474. }
  475. /* Go back to read mode */
  476. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
  477. }
  478. /* Get Data into Buffer */
  479. for(; index < size; index++)
  480. {
  481. *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
  482. }
  483. /* Increment read pages number */
  484. numPagesRead++;
  485. /* Decrement pages to read */
  486. NumPageToRead--;
  487. /* Increment the NAND address */
  488. nandaddress = (uint32_t)(nandaddress + 1U);
  489. }
  490. /* Update the NAND controller state */
  491. hnand->State = HAL_NAND_STATE_READY;
  492. /* Process unlocked */
  493. __HAL_UNLOCK(hnand);
  494. return HAL_OK;
  495. }
  496. /**
  497. * @brief Read Page(s) from NAND memory block (16-bits addressing)
  498. * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
  499. * the configuration information for NAND module.
  500. * @param pAddress : pointer to NAND address structure
  501. * @param pBuffer : pointer to destination read buffer. pBuffer should be 16bits aligned
  502. * @param NumPageToRead : number of pages to read from block
  503. * @retval HAL status
  504. */
  505. HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)
  506. {
  507. __IO uint32_t index = 0U;
  508. uint32_t tickstart = 0U;
  509. uint32_t deviceaddress = 0U, size = 0U, numPagesRead = 0U, nandaddress = 0U;
  510. /* Process Locked */
  511. __HAL_LOCK(hnand);
  512. /* Check the NAND controller state */
  513. if(hnand->State == HAL_NAND_STATE_BUSY)
  514. {
  515. return HAL_BUSY;
  516. }
  517. /* Identify the device address */
  518. if(hnand->Init.NandBank == FSMC_NAND_BANK2)
  519. {
  520. deviceaddress = NAND_DEVICE1;
  521. }
  522. else
  523. {
  524. deviceaddress = NAND_DEVICE2;
  525. }
  526. /* Update the NAND controller state */
  527. hnand->State = HAL_NAND_STATE_BUSY;
  528. /* NAND raw address calculation */
  529. nandaddress = ARRAY_ADDRESS(pAddress, hnand);
  530. /* Page(s) read loop */
  531. while((NumPageToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
  532. {
  533. /* update the buffer size */
  534. size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead);
  535. /* Send read page command sequence */
  536. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
  537. /* Cards with page size <= 512 bytes */
  538. if((hnand->Config.PageSize) <= 512U)
  539. {
  540. if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
  541. {
  542. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
  543. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  544. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  545. }
  546. else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
  547. {
  548. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
  549. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  550. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  551. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
  552. }
  553. }
  554. else /* (hnand->Config.PageSize) > 512 */
  555. {
  556. if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
  557. {
  558. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
  559. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
  560. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  561. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  562. }
  563. else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
  564. {
  565. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
  566. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
  567. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  568. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  569. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
  570. }
  571. }
  572. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
  573. if(hnand->Config.ExtraCommandEnable == ENABLE)
  574. {
  575. /* Get tick */
  576. tickstart = HAL_GetTick();
  577. /* Read status until NAND is ready */
  578. while(HAL_NAND_Read_Status(hnand) != NAND_READY)
  579. {
  580. if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
  581. {
  582. return HAL_TIMEOUT;
  583. }
  584. }
  585. /* Go back to read mode */
  586. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
  587. }
  588. /* Get Data into Buffer */
  589. for(; index < size; index++)
  590. {
  591. *(uint16_t *)pBuffer++ = *(uint16_t *)deviceaddress;
  592. }
  593. /* Increment read pages number */
  594. numPagesRead++;
  595. /* Decrement pages to read */
  596. NumPageToRead--;
  597. /* Increment the NAND address */
  598. nandaddress = (uint32_t)(nandaddress + 1U);
  599. }
  600. /* Update the NAND controller state */
  601. hnand->State = HAL_NAND_STATE_READY;
  602. /* Process unlocked */
  603. __HAL_UNLOCK(hnand);
  604. return HAL_OK;
  605. }
  606. /**
  607. * @brief Write Page(s) to NAND memory block (8-bits addressing)
  608. * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
  609. * the configuration information for NAND module.
  610. * @param pAddress : pointer to NAND address structure
  611. * @param pBuffer : pointer to source buffer to write
  612. * @param NumPageToWrite : number of pages to write to block
  613. * @retval HAL status
  614. */
  615. HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
  616. {
  617. __IO uint32_t index = 0U;
  618. uint32_t tickstart = 0U;
  619. uint32_t deviceaddress = 0U, size = 0U, numPagesWritten = 0U, nandaddress = 0U;
  620. /* Process Locked */
  621. __HAL_LOCK(hnand);
  622. /* Check the NAND controller state */
  623. if(hnand->State == HAL_NAND_STATE_BUSY)
  624. {
  625. return HAL_BUSY;
  626. }
  627. /* Identify the device address */
  628. if(hnand->Init.NandBank == FSMC_NAND_BANK2)
  629. {
  630. deviceaddress = NAND_DEVICE1;
  631. }
  632. else
  633. {
  634. deviceaddress = NAND_DEVICE2;
  635. }
  636. /* Update the NAND controller state */
  637. hnand->State = HAL_NAND_STATE_BUSY;
  638. /* NAND raw address calculation */
  639. nandaddress = ARRAY_ADDRESS(pAddress, hnand);
  640. /* Page(s) write loop */
  641. while((NumPageToWrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
  642. {
  643. /* update the buffer size */
  644. size = hnand->Config.PageSize + ((hnand->Config.PageSize) * numPagesWritten);
  645. /* Send write page command sequence */
  646. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
  647. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
  648. /* Cards with page size <= 512 bytes */
  649. if((hnand->Config.PageSize) <= 512U)
  650. {
  651. if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
  652. {
  653. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
  654. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  655. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  656. }
  657. else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
  658. {
  659. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
  660. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  661. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  662. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
  663. }
  664. }
  665. else /* (hnand->Config.PageSize) > 512 */
  666. {
  667. if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
  668. {
  669. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
  670. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
  671. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  672. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  673. }
  674. else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
  675. {
  676. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
  677. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
  678. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  679. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  680. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
  681. }
  682. }
  683. /* Write data to memory */
  684. for(; index < size; index++)
  685. {
  686. *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
  687. }
  688. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
  689. /* Read status until NAND is ready */
  690. while(HAL_NAND_Read_Status(hnand) != NAND_READY)
  691. {
  692. /* Get tick */
  693. tickstart = HAL_GetTick();
  694. if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
  695. {
  696. return HAL_TIMEOUT;
  697. }
  698. }
  699. /* Increment written pages number */
  700. numPagesWritten++;
  701. /* Decrement pages to write */
  702. NumPageToWrite--;
  703. /* Increment the NAND address */
  704. nandaddress = (uint32_t)(nandaddress + 1U);
  705. }
  706. /* Update the NAND controller state */
  707. hnand->State = HAL_NAND_STATE_READY;
  708. /* Process unlocked */
  709. __HAL_UNLOCK(hnand);
  710. return HAL_OK;
  711. }
  712. /**
  713. * @brief Write Page(s) to NAND memory block (16-bits addressing)
  714. * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
  715. * the configuration information for NAND module.
  716. * @param pAddress : pointer to NAND address structure
  717. * @param pBuffer : pointer to source buffer to write. pBuffer should be 16bits aligned
  718. * @param NumPageToWrite : number of pages to write to block
  719. * @retval HAL status
  720. */
  721. HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)
  722. {
  723. __IO uint32_t index = 0U;
  724. uint32_t tickstart = 0U;
  725. uint32_t deviceaddress = 0U, size = 0U, numPagesWritten = 0U, nandaddress = 0U;
  726. /* Process Locked */
  727. __HAL_LOCK(hnand);
  728. /* Check the NAND controller state */
  729. if(hnand->State == HAL_NAND_STATE_BUSY)
  730. {
  731. return HAL_BUSY;
  732. }
  733. /* Identify the device address */
  734. if(hnand->Init.NandBank == FSMC_NAND_BANK2)
  735. {
  736. deviceaddress = NAND_DEVICE1;
  737. }
  738. else
  739. {
  740. deviceaddress = NAND_DEVICE2;
  741. }
  742. /* Update the NAND controller state */
  743. hnand->State = HAL_NAND_STATE_BUSY;
  744. /* NAND raw address calculation */
  745. nandaddress = ARRAY_ADDRESS(pAddress, hnand);
  746. /* Page(s) write loop */
  747. while((NumPageToWrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
  748. {
  749. /* update the buffer size */
  750. size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesWritten);
  751. /* Send write page command sequence */
  752. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
  753. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
  754. /* Cards with page size <= 512 bytes */
  755. if((hnand->Config.PageSize) <= 512U)
  756. {
  757. if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
  758. {
  759. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
  760. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  761. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  762. }
  763. else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
  764. {
  765. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
  766. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  767. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  768. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
  769. }
  770. }
  771. else /* (hnand->Config.PageSize) > 512 */
  772. {
  773. if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
  774. {
  775. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
  776. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
  777. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  778. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  779. }
  780. else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
  781. {
  782. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
  783. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
  784. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  785. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  786. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
  787. }
  788. }
  789. /* Write data to memory */
  790. for(; index < size; index++)
  791. {
  792. *(__IO uint16_t *)deviceaddress = *(uint16_t *)pBuffer++;
  793. }
  794. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
  795. /* Read status until NAND is ready */
  796. while(HAL_NAND_Read_Status(hnand) != NAND_READY)
  797. {
  798. /* Get tick */
  799. tickstart = HAL_GetTick();
  800. if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
  801. {
  802. return HAL_TIMEOUT;
  803. }
  804. }
  805. /* Increment written pages number */
  806. numPagesWritten++;
  807. /* Decrement pages to write */
  808. NumPageToWrite--;
  809. /* Increment the NAND address */
  810. nandaddress = (uint32_t)(nandaddress + 1U);
  811. }
  812. /* Update the NAND controller state */
  813. hnand->State = HAL_NAND_STATE_READY;
  814. /* Process unlocked */
  815. __HAL_UNLOCK(hnand);
  816. return HAL_OK;
  817. }
  818. /**
  819. * @brief Read Spare area(s) from NAND memory (8-bits addressing)
  820. * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
  821. * the configuration information for NAND module.
  822. * @param pAddress : pointer to NAND address structure
  823. * @param pBuffer: pointer to source buffer to write
  824. * @param NumSpareAreaToRead: Number of spare area to read
  825. * @retval HAL status
  826. */
  827. HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
  828. {
  829. __IO uint32_t index = 0U;
  830. uint32_t tickstart = 0U;
  831. uint32_t deviceaddress = 0U, size = 0U, numSpareAreaRead = 0U, nandaddress = 0U, columnaddress = 0U;
  832. /* Process Locked */
  833. __HAL_LOCK(hnand);
  834. /* Check the NAND controller state */
  835. if(hnand->State == HAL_NAND_STATE_BUSY)
  836. {
  837. return HAL_BUSY;
  838. }
  839. /* Identify the device address */
  840. if(hnand->Init.NandBank == FSMC_NAND_BANK2)
  841. {
  842. deviceaddress = NAND_DEVICE1;
  843. }
  844. else
  845. {
  846. deviceaddress = NAND_DEVICE2;
  847. }
  848. /* Update the NAND controller state */
  849. hnand->State = HAL_NAND_STATE_BUSY;
  850. /* NAND raw address calculation */
  851. nandaddress = ARRAY_ADDRESS(pAddress, hnand);
  852. /* Column in page address */
  853. columnaddress = COLUMN_ADDRESS(hnand);
  854. /* Spare area(s) read loop */
  855. while((NumSpareAreaToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
  856. {
  857. /* update the buffer size */
  858. size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead);
  859. /* Cards with page size <= 512 bytes */
  860. if((hnand->Config.PageSize) <= 512U)
  861. {
  862. /* Send read spare area command sequence */
  863. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
  864. if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
  865. {
  866. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
  867. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  868. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  869. }
  870. else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
  871. {
  872. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
  873. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  874. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  875. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
  876. }
  877. }
  878. else /* (hnand->Config.PageSize) > 512 */
  879. {
  880. /* Send read spare area command sequence */
  881. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
  882. if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
  883. {
  884. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
  885. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
  886. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  887. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  888. }
  889. else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
  890. {
  891. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
  892. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
  893. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  894. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  895. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
  896. }
  897. }
  898. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
  899. if(hnand->Config.ExtraCommandEnable == ENABLE)
  900. {
  901. /* Get tick */
  902. tickstart = HAL_GetTick();
  903. /* Read status until NAND is ready */
  904. while(HAL_NAND_Read_Status(hnand) != NAND_READY)
  905. {
  906. if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
  907. {
  908. return HAL_TIMEOUT;
  909. }
  910. }
  911. /* Go back to read mode */
  912. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
  913. }
  914. /* Get Data into Buffer */
  915. for(; index < size; index++)
  916. {
  917. *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
  918. }
  919. /* Increment read spare areas number */
  920. numSpareAreaRead++;
  921. /* Decrement spare areas to read */
  922. NumSpareAreaToRead--;
  923. /* Increment the NAND address */
  924. nandaddress = (uint32_t)(nandaddress + 1U);
  925. }
  926. /* Update the NAND controller state */
  927. hnand->State = HAL_NAND_STATE_READY;
  928. /* Process unlocked */
  929. __HAL_UNLOCK(hnand);
  930. return HAL_OK;
  931. }
  932. /**
  933. * @brief Read Spare area(s) from NAND memory (16-bits addressing)
  934. * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
  935. * the configuration information for NAND module.
  936. * @param pAddress : pointer to NAND address structure
  937. * @param pBuffer: pointer to source buffer to write. pBuffer should be 16bits aligned.
  938. * @param NumSpareAreaToRead: Number of spare area to read
  939. * @retval HAL status
  940. */
  941. HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
  942. {
  943. __IO uint32_t index = 0U;
  944. uint32_t tickstart = 0U;
  945. uint32_t deviceaddress = 0U, size = 0U, numSpareAreaRead = 0U, nandaddress = 0U, columnaddress = 0U;
  946. /* Process Locked */
  947. __HAL_LOCK(hnand);
  948. /* Check the NAND controller state */
  949. if(hnand->State == HAL_NAND_STATE_BUSY)
  950. {
  951. return HAL_BUSY;
  952. }
  953. /* Identify the device address */
  954. if(hnand->Init.NandBank == FSMC_NAND_BANK2)
  955. {
  956. deviceaddress = NAND_DEVICE1;
  957. }
  958. else
  959. {
  960. deviceaddress = NAND_DEVICE2;
  961. }
  962. /* Update the NAND controller state */
  963. hnand->State = HAL_NAND_STATE_BUSY;
  964. /* NAND raw address calculation */
  965. nandaddress = ARRAY_ADDRESS(pAddress, hnand);
  966. /* Column in page address */
  967. columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
  968. /* Spare area(s) read loop */
  969. while((NumSpareAreaToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
  970. {
  971. /* update the buffer size */
  972. size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead);
  973. /* Cards with page size <= 512 bytes */
  974. if((hnand->Config.PageSize) <= 512U)
  975. {
  976. /* Send read spare area command sequence */
  977. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
  978. if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
  979. {
  980. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
  981. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  982. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  983. }
  984. else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
  985. {
  986. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
  987. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  988. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  989. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
  990. }
  991. }
  992. else /* (hnand->Config.PageSize) > 512 */
  993. {
  994. /* Send read spare area command sequence */
  995. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
  996. if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
  997. {
  998. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
  999. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
  1000. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  1001. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  1002. }
  1003. else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
  1004. {
  1005. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
  1006. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
  1007. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  1008. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  1009. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
  1010. }
  1011. }
  1012. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
  1013. if(hnand->Config.ExtraCommandEnable == ENABLE)
  1014. {
  1015. /* Get tick */
  1016. tickstart = HAL_GetTick();
  1017. /* Read status until NAND is ready */
  1018. while(HAL_NAND_Read_Status(hnand) != NAND_READY)
  1019. {
  1020. if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
  1021. {
  1022. return HAL_TIMEOUT;
  1023. }
  1024. }
  1025. /* Go back to read mode */
  1026. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
  1027. }
  1028. /* Get Data into Buffer */
  1029. for(; index < size; index++)
  1030. {
  1031. *(uint16_t *)pBuffer++ = *(uint16_t *)deviceaddress;
  1032. }
  1033. /* Increment read spare areas number */
  1034. numSpareAreaRead++;
  1035. /* Decrement spare areas to read */
  1036. NumSpareAreaToRead--;
  1037. /* Increment the NAND address */
  1038. nandaddress = (uint32_t)(nandaddress + 1U);
  1039. }
  1040. /* Update the NAND controller state */
  1041. hnand->State = HAL_NAND_STATE_READY;
  1042. /* Process unlocked */
  1043. __HAL_UNLOCK(hnand);
  1044. return HAL_OK;
  1045. }
  1046. /**
  1047. * @brief Write Spare area(s) to NAND memory (8-bits addressing)
  1048. * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
  1049. * the configuration information for NAND module.
  1050. * @param pAddress : pointer to NAND address structure
  1051. * @param pBuffer : pointer to source buffer to write
  1052. * @param NumSpareAreaTowrite : number of spare areas to write to block
  1053. * @retval HAL status
  1054. */
  1055. HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
  1056. {
  1057. __IO uint32_t index = 0U;
  1058. uint32_t tickstart = 0U;
  1059. uint32_t deviceaddress = 0U, size = 0U, numSpareAreaWritten = 0U, nandaddress = 0U, columnaddress = 0U;
  1060. /* Process Locked */
  1061. __HAL_LOCK(hnand);
  1062. /* Check the NAND controller state */
  1063. if(hnand->State == HAL_NAND_STATE_BUSY)
  1064. {
  1065. return HAL_BUSY;
  1066. }
  1067. /* Identify the device address */
  1068. if(hnand->Init.NandBank == FSMC_NAND_BANK2)
  1069. {
  1070. deviceaddress = NAND_DEVICE1;
  1071. }
  1072. else
  1073. {
  1074. deviceaddress = NAND_DEVICE2;
  1075. }
  1076. /* Update the FSMC_NAND controller state */
  1077. hnand->State = HAL_NAND_STATE_BUSY;
  1078. /* Page address calculation */
  1079. nandaddress = ARRAY_ADDRESS(pAddress, hnand);
  1080. /* Column in page address */
  1081. columnaddress = COLUMN_ADDRESS(hnand);
  1082. /* Spare area(s) write loop */
  1083. while((NumSpareAreaTowrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
  1084. {
  1085. /* update the buffer size */
  1086. size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten);
  1087. /* Cards with page size <= 512 bytes */
  1088. if((hnand->Config.PageSize) <= 512U)
  1089. {
  1090. /* Send write Spare area command sequence */
  1091. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
  1092. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
  1093. if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
  1094. {
  1095. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
  1096. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  1097. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  1098. }
  1099. else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
  1100. {
  1101. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
  1102. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  1103. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  1104. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
  1105. }
  1106. }
  1107. else /* (hnand->Config.PageSize) > 512 */
  1108. {
  1109. /* Send write Spare area command sequence */
  1110. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
  1111. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
  1112. if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
  1113. {
  1114. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
  1115. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
  1116. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  1117. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  1118. }
  1119. else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
  1120. {
  1121. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
  1122. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
  1123. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  1124. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  1125. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
  1126. }
  1127. }
  1128. /* Write data to memory */
  1129. for(; index < size; index++)
  1130. {
  1131. *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
  1132. }
  1133. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
  1134. /* Get tick */
  1135. tickstart = HAL_GetTick();
  1136. /* Read status until NAND is ready */
  1137. while(HAL_NAND_Read_Status(hnand) != NAND_READY)
  1138. {
  1139. if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
  1140. {
  1141. return HAL_TIMEOUT;
  1142. }
  1143. }
  1144. /* Increment written spare areas number */
  1145. numSpareAreaWritten++;
  1146. /* Decrement spare areas to write */
  1147. NumSpareAreaTowrite--;
  1148. /* Increment the NAND address */
  1149. nandaddress = (uint32_t)(nandaddress + 1U);
  1150. }
  1151. /* Update the NAND controller state */
  1152. hnand->State = HAL_NAND_STATE_READY;
  1153. /* Process unlocked */
  1154. __HAL_UNLOCK(hnand);
  1155. return HAL_OK;
  1156. }
  1157. /**
  1158. * @brief Write Spare area(s) to NAND memory (16-bits addressing)
  1159. * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
  1160. * the configuration information for NAND module.
  1161. * @param pAddress : pointer to NAND address structure
  1162. * @param pBuffer : pointer to source buffer to write. pBuffer should be 16bits aligned.
  1163. * @param NumSpareAreaTowrite : number of spare areas to write to block
  1164. * @retval HAL status
  1165. */
  1166. HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
  1167. {
  1168. __IO uint32_t index = 0U;
  1169. uint32_t tickstart = 0U;
  1170. uint32_t deviceaddress = 0U, size = 0U, numSpareAreaWritten = 0U, nandaddress = 0U, columnaddress = 0U;
  1171. /* Process Locked */
  1172. __HAL_LOCK(hnand);
  1173. /* Check the NAND controller state */
  1174. if(hnand->State == HAL_NAND_STATE_BUSY)
  1175. {
  1176. return HAL_BUSY;
  1177. }
  1178. /* Identify the device address */
  1179. if(hnand->Init.NandBank == FSMC_NAND_BANK2)
  1180. {
  1181. deviceaddress = NAND_DEVICE1;
  1182. }
  1183. else
  1184. {
  1185. deviceaddress = NAND_DEVICE2;
  1186. }
  1187. /* Update the FSMC_NAND controller state */
  1188. hnand->State = HAL_NAND_STATE_BUSY;
  1189. /* NAND raw address calculation */
  1190. nandaddress = ARRAY_ADDRESS(pAddress, hnand);
  1191. /* Column in page address */
  1192. columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
  1193. /* Spare area(s) write loop */
  1194. while((NumSpareAreaTowrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
  1195. {
  1196. /* update the buffer size */
  1197. size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten);
  1198. /* Cards with page size <= 512 bytes */
  1199. if((hnand->Config.PageSize) <= 512U)
  1200. {
  1201. /* Send write Spare area command sequence */
  1202. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
  1203. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
  1204. if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
  1205. {
  1206. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
  1207. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  1208. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  1209. }
  1210. else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
  1211. {
  1212. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
  1213. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  1214. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  1215. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
  1216. }
  1217. }
  1218. else /* (hnand->Config.PageSize) > 512 */
  1219. {
  1220. /* Send write Spare area command sequence */
  1221. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
  1222. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
  1223. if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
  1224. {
  1225. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
  1226. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
  1227. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  1228. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  1229. }
  1230. else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
  1231. {
  1232. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
  1233. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
  1234. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  1235. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  1236. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
  1237. }
  1238. }
  1239. /* Write data to memory */
  1240. for(; index < size; index++)
  1241. {
  1242. *(__IO uint16_t *)deviceaddress = *(uint16_t *)pBuffer++;
  1243. }
  1244. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
  1245. /* Read status until NAND is ready */
  1246. while(HAL_NAND_Read_Status(hnand) != NAND_READY)
  1247. {
  1248. /* Get tick */
  1249. tickstart = HAL_GetTick();
  1250. if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
  1251. {
  1252. return HAL_TIMEOUT;
  1253. }
  1254. }
  1255. /* Increment written spare areas number */
  1256. numSpareAreaWritten++;
  1257. /* Decrement spare areas to write */
  1258. NumSpareAreaTowrite--;
  1259. /* Increment the NAND address */
  1260. nandaddress = (uint32_t)(nandaddress + 1U);
  1261. }
  1262. /* Update the NAND controller state */
  1263. hnand->State = HAL_NAND_STATE_READY;
  1264. /* Process unlocked */
  1265. __HAL_UNLOCK(hnand);
  1266. return HAL_OK;
  1267. }
  1268. /**
  1269. * @brief NAND memory Block erase
  1270. * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
  1271. * the configuration information for NAND module.
  1272. * @param pAddress : pointer to NAND address structure
  1273. * @retval HAL status
  1274. */
  1275. HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
  1276. {
  1277. uint32_t deviceaddress = 0U;
  1278. uint32_t tickstart = 0U;
  1279. /* Process Locked */
  1280. __HAL_LOCK(hnand);
  1281. /* Check the NAND controller state */
  1282. if(hnand->State == HAL_NAND_STATE_BUSY)
  1283. {
  1284. return HAL_BUSY;
  1285. }
  1286. /* Identify the device address */
  1287. if(hnand->Init.NandBank == FSMC_NAND_BANK2)
  1288. {
  1289. deviceaddress = NAND_DEVICE1;
  1290. }
  1291. else
  1292. {
  1293. deviceaddress = NAND_DEVICE2;
  1294. }
  1295. /* Update the NAND controller state */
  1296. hnand->State = HAL_NAND_STATE_BUSY;
  1297. /* Send Erase block command sequence */
  1298. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
  1299. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
  1300. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
  1301. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
  1302. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
  1303. /* Update the NAND controller state */
  1304. hnand->State = HAL_NAND_STATE_READY;
  1305. /* Get tick */
  1306. tickstart = HAL_GetTick();
  1307. /* Read status until NAND is ready */
  1308. while(HAL_NAND_Read_Status(hnand) != NAND_READY)
  1309. {
  1310. if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
  1311. {
  1312. /* Process unlocked */
  1313. __HAL_UNLOCK(hnand);
  1314. return HAL_TIMEOUT;
  1315. }
  1316. }
  1317. /* Process unlocked */
  1318. __HAL_UNLOCK(hnand);
  1319. return HAL_OK;
  1320. }
  1321. /**
  1322. * @brief NAND memory read status
  1323. * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
  1324. * the configuration information for NAND module.
  1325. * @retval NAND status
  1326. */
  1327. uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
  1328. {
  1329. uint32_t data = 0U;
  1330. uint32_t deviceaddress = 0U;
  1331. /* Identify the device address */
  1332. if(hnand->Init.NandBank == FSMC_NAND_BANK2)
  1333. {
  1334. deviceaddress = NAND_DEVICE1;
  1335. }
  1336. else
  1337. {
  1338. deviceaddress = NAND_DEVICE2;
  1339. }
  1340. /* Send Read status operation command */
  1341. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
  1342. /* Read status register data */
  1343. data = *(__IO uint8_t *)deviceaddress;
  1344. /* Return the status */
  1345. if((data & NAND_ERROR) == NAND_ERROR)
  1346. {
  1347. return NAND_ERROR;
  1348. }
  1349. else if((data & NAND_READY) == NAND_READY)
  1350. {
  1351. return NAND_READY;
  1352. }
  1353. return NAND_BUSY;
  1354. }
  1355. /**
  1356. * @brief Increment the NAND memory address
  1357. * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
  1358. * the configuration information for NAND module.
  1359. * @param pAddress: pointer to NAND address structure
  1360. * @retval The new status of the increment address operation. It can be:
  1361. * - NAND_VALID_ADDRESS: When the new address is valid address
  1362. * - NAND_INVALID_ADDRESS: When the new address is invalid address
  1363. */
  1364. uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
  1365. {
  1366. uint32_t status = NAND_VALID_ADDRESS;
  1367. /* Increment page address */
  1368. pAddress->Page++;
  1369. /* Check NAND address is valid */
  1370. if(pAddress->Page == hnand->Config.BlockSize)
  1371. {
  1372. pAddress->Page = 0U;
  1373. pAddress->Block++;
  1374. if(pAddress->Block == hnand->Config.PlaneSize)
  1375. {
  1376. pAddress->Block = 0U;
  1377. pAddress->Plane++;
  1378. if(pAddress->Plane == (hnand->Config.PlaneNbr))
  1379. {
  1380. status = NAND_INVALID_ADDRESS;
  1381. }
  1382. }
  1383. }
  1384. return (status);
  1385. }
  1386. /**
  1387. * @}
  1388. */
  1389. /** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
  1390. * @brief management functions
  1391. *
  1392. @verbatim
  1393. ==============================================================================
  1394. ##### NAND Control functions #####
  1395. ==============================================================================
  1396. [..]
  1397. This subsection provides a set of functions allowing to control dynamically
  1398. the NAND interface.
  1399. @endverbatim
  1400. * @{
  1401. */
  1402. /**
  1403. * @brief Enables dynamically NAND ECC feature.
  1404. * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
  1405. * the configuration information for NAND module.
  1406. * @retval HAL status
  1407. */
  1408. HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
  1409. {
  1410. /* Check the NAND controller state */
  1411. if(hnand->State == HAL_NAND_STATE_BUSY)
  1412. {
  1413. return HAL_BUSY;
  1414. }
  1415. /* Update the NAND state */
  1416. hnand->State = HAL_NAND_STATE_BUSY;
  1417. /* Enable ECC feature */
  1418. FSMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
  1419. /* Update the NAND state */
  1420. hnand->State = HAL_NAND_STATE_READY;
  1421. return HAL_OK;
  1422. }
  1423. /**
  1424. * @brief Disables dynamically FSMC_NAND ECC feature.
  1425. * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
  1426. * the configuration information for NAND module.
  1427. * @retval HAL status
  1428. */
  1429. HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
  1430. {
  1431. /* Check the NAND controller state */
  1432. if(hnand->State == HAL_NAND_STATE_BUSY)
  1433. {
  1434. return HAL_BUSY;
  1435. }
  1436. /* Update the NAND state */
  1437. hnand->State = HAL_NAND_STATE_BUSY;
  1438. /* Disable ECC feature */
  1439. FSMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
  1440. /* Update the NAND state */
  1441. hnand->State = HAL_NAND_STATE_READY;
  1442. return HAL_OK;
  1443. }
  1444. /**
  1445. * @brief Disables dynamically NAND ECC feature.
  1446. * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
  1447. * the configuration information for NAND module.
  1448. * @param ECCval: pointer to ECC value
  1449. * @param Timeout: maximum timeout to wait
  1450. * @retval HAL status
  1451. */
  1452. HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
  1453. {
  1454. HAL_StatusTypeDef status = HAL_OK;
  1455. /* Check the NAND controller state */
  1456. if(hnand->State == HAL_NAND_STATE_BUSY)
  1457. {
  1458. return HAL_BUSY;
  1459. }
  1460. /* Update the NAND state */
  1461. hnand->State = HAL_NAND_STATE_BUSY;
  1462. /* Get NAND ECC value */
  1463. status = FSMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
  1464. /* Update the NAND state */
  1465. hnand->State = HAL_NAND_STATE_READY;
  1466. return status;
  1467. }
  1468. /**
  1469. * @}
  1470. */
  1471. /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
  1472. * @brief Peripheral State functions
  1473. *
  1474. @verbatim
  1475. ==============================================================================
  1476. ##### NAND State functions #####
  1477. ==============================================================================
  1478. [..]
  1479. This subsection permits to get in run-time the status of the NAND controller
  1480. and the data flow.
  1481. @endverbatim
  1482. * @{
  1483. */
  1484. /**
  1485. * @brief return the NAND state
  1486. * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
  1487. * the configuration information for NAND module.
  1488. * @retval HAL state
  1489. */
  1490. HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
  1491. {
  1492. return hnand->State;
  1493. }
  1494. /**
  1495. * @}
  1496. */
  1497. /**
  1498. * @}
  1499. */
  1500. /**
  1501. * @}
  1502. */
  1503. #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
  1504. #endif /* HAL_NAND_MODULE_ENABLED */
  1505. /**
  1506. * @}
  1507. */
  1508. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/