stm32f4xx_hal_i2s.c 45 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f4xx_hal_i2s.c
  4. * @author MCD Application Team
  5. * @version V1.4.3
  6. * @date 11-December-2015
  7. * @brief I2S HAL module driver.
  8. * This file provides firmware functions to manage the following
  9. * functionalities of the Integrated Interchip Sound (I2S) peripheral:
  10. * + Initialization and de-initialization functions
  11. * + IO operation functions
  12. * + Peripheral State and Errors functions
  13. @verbatim
  14. ===============================================================================
  15. ##### How to use this driver #####
  16. ===============================================================================
  17. [..]
  18. The I2S HAL driver can be used as follow:
  19. (#) Declare a I2S_HandleTypeDef handle structure.
  20. (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
  21. (##) Enable the SPIx interface clock.
  22. (##) I2S pins configuration:
  23. (+++) Enable the clock for the I2S GPIOs.
  24. (+++) Configure these I2S pins as alternate function pull-up.
  25. (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
  26. and HAL_I2S_Receive_IT() APIs).
  27. (+++) Configure the I2Sx interrupt priority.
  28. (+++) Enable the NVIC I2S IRQ handle.
  29. (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
  30. and HAL_I2S_Receive_DMA() APIs:
  31. (+++) Declare a DMA handle structure for the Tx/Rx stream.
  32. (+++) Enable the DMAx interface clock.
  33. (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
  34. (+++) Configure the DMA Tx/Rx Stream.
  35. (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
  36. (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
  37. DMA Tx/Rx Stream.
  38. (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
  39. using HAL_I2S_Init() function.
  40. -@- The specific I2S interrupts (Transmission complete interrupt,
  41. RXNE interrupt and Error Interrupts) will be managed using the macros
  42. __I2S_ENABLE_IT() and __I2S_DISABLE_IT() inside the transmit and receive process.
  43. -@- Make sure that either:
  44. (+@) I2S PLL is configured or
  45. (+@) External clock source is configured after setting correctly
  46. the define constant EXTERNAL_CLOCK_VALUE in the stm32f4xx_hal_conf.h file.
  47. (#) Three operation modes are available within this driver :
  48. *** Polling mode IO operation ***
  49. =================================
  50. [..]
  51. (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
  52. (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
  53. *** Interrupt mode IO operation ***
  54. ===================================
  55. [..]
  56. (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
  57. (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
  58. add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
  59. (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
  60. add his own code by customization of function pointer HAL_I2S_TxCpltCallback
  61. (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
  62. (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
  63. add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
  64. (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
  65. add his own code by customization of function pointer HAL_I2S_RxCpltCallback
  66. (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
  67. add his own code by customization of function pointer HAL_I2S_ErrorCallback
  68. *** DMA mode IO operation ***
  69. ==============================
  70. [..]
  71. (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
  72. (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
  73. add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
  74. (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
  75. add his own code by customization of function pointer HAL_I2S_TxCpltCallback
  76. (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
  77. (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
  78. add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
  79. (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
  80. add his own code by customization of function pointer HAL_I2S_RxCpltCallback
  81. (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
  82. add his own code by customization of function pointer HAL_I2S_ErrorCallback
  83. (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
  84. (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
  85. (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
  86. *** I2S HAL driver macros list ***
  87. =============================================
  88. [..]
  89. Below the list of most used macros in USART HAL driver.
  90. (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
  91. (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
  92. (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
  93. (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
  94. (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
  95. [..]
  96. (@) You can refer to the I2S HAL driver header file for more useful macros
  97. @endverbatim
  98. ******************************************************************************
  99. * @attention
  100. *
  101. * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
  102. *
  103. * Redistribution and use in source and binary forms, with or without modification,
  104. * are permitted provided that the following conditions are met:
  105. * 1. Redistributions of source code must retain the above copyright notice,
  106. * this list of conditions and the following disclaimer.
  107. * 2. Redistributions in binary form must reproduce the above copyright notice,
  108. * this list of conditions and the following disclaimer in the documentation
  109. * and/or other materials provided with the distribution.
  110. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  111. * may be used to endorse or promote products derived from this software
  112. * without specific prior written permission.
  113. *
  114. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  115. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  116. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  117. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  118. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  119. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  120. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  121. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  122. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  123. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  124. *
  125. ******************************************************************************
  126. */
  127. /* Includes ------------------------------------------------------------------*/
  128. #include "stm32f4xx_hal.h"
  129. /** @addtogroup STM32F4xx_HAL_Driver
  130. * @{
  131. */
  132. /** @defgroup I2S I2S
  133. * @brief I2S HAL module driver
  134. * @{
  135. */
  136. #ifdef HAL_I2S_MODULE_ENABLED
  137. /* Private typedef -----------------------------------------------------------*/
  138. /* Private define ------------------------------------------------------------*/
  139. /* Private macro -------------------------------------------------------------*/
  140. /* Private variables ---------------------------------------------------------*/
  141. /* Private function prototypes -----------------------------------------------*/
  142. /** @addtogroup I2S_Private_Functions
  143. * @{
  144. */
  145. /**
  146. * @}
  147. */
  148. /* Exported functions --------------------------------------------------------*/
  149. /** @defgroup I2S_Exported_Functions I2S Exported Functions
  150. * @{
  151. */
  152. /** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
  153. * @brief Initialization and Configuration functions
  154. *
  155. @verbatim
  156. ===============================================================================
  157. ##### Initialization and de-initialization functions #####
  158. ===============================================================================
  159. [..] This subsection provides a set of functions allowing to initialize and
  160. de-initialize the I2Sx peripheral in simplex mode:
  161. (+) User must Implement HAL_I2S_MspInit() function in which he configures
  162. all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
  163. (+) Call the function HAL_I2S_Init() to configure the selected device with
  164. the selected configuration:
  165. (++) Mode
  166. (++) Standard
  167. (++) Data Format
  168. (++) MCLK Output
  169. (++) Audio frequency
  170. (++) Polarity
  171. (+) Call the function HAL_I2S_DeInit() to restore the default configuration
  172. of the selected I2Sx peripheral.
  173. @endverbatim
  174. * @{
  175. */
  176. /**
  177. * @brief Initializes the I2S according to the specified parameters
  178. * in the I2S_InitTypeDef and create the associated handle.
  179. * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
  180. * the configuration information for I2S module
  181. * @retval HAL status
  182. */
  183. __weak HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
  184. {
  185. uint32_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
  186. uint32_t tmp = 0, i2sclk = 0;
  187. /* Check the I2S handle allocation */
  188. if(hi2s == NULL)
  189. {
  190. return HAL_ERROR;
  191. }
  192. /* Check the I2S parameters */
  193. assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
  194. assert_param(IS_I2S_MODE(hi2s->Init.Mode));
  195. assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
  196. assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
  197. assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
  198. assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
  199. assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
  200. assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
  201. if(hi2s->State == HAL_I2S_STATE_RESET)
  202. {
  203. /* Allocate lock resource and initialize it */
  204. hi2s->Lock = HAL_UNLOCKED;
  205. /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
  206. HAL_I2S_MspInit(hi2s);
  207. }
  208. hi2s->State = HAL_I2S_STATE_BUSY;
  209. /*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/
  210. /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
  211. hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
  212. SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
  213. SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
  214. hi2s->Instance->I2SPR = 0x0002;
  215. /* Get the I2SCFGR register value */
  216. tmpreg = hi2s->Instance->I2SCFGR;
  217. /* If the default frequency value has to be written, reinitialize i2sdiv and i2sodd */
  218. /* If the requested audio frequency is not the default, compute the prescaler */
  219. if(hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
  220. {
  221. /* Check the frame length (For the Prescaler computing) *******************/
  222. if(hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
  223. {
  224. /* Packet length is 32 bits */
  225. packetlength = 2;
  226. }
  227. /* Get I2S source Clock frequency ****************************************/
  228. /* If an external I2S clock has to be used, the specific define should be set
  229. in the project configuration or in the stm32f4xx_conf.h file */
  230. i2sclk = I2S_GetInputClock(hi2s);
  231. /* Compute the Real divider depending on the MCLK output state, with a floating point */
  232. if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
  233. {
  234. /* MCLK output is enabled */
  235. tmp = (uint32_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5);
  236. }
  237. else
  238. {
  239. /* MCLK output is disabled */
  240. tmp = (uint32_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5);
  241. }
  242. /* Remove the flatting point */
  243. tmp = tmp / 10;
  244. /* Check the parity of the divider */
  245. i2sodd = (uint32_t)(tmp & (uint32_t)1);
  246. /* Compute the i2sdiv prescaler */
  247. i2sdiv = (uint32_t)((tmp - i2sodd) / 2);
  248. /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
  249. i2sodd = (uint32_t) (i2sodd << 8);
  250. }
  251. /* Test if the divider is 1 or 0 or greater than 0xFF */
  252. if((i2sdiv < 2) || (i2sdiv > 0xFF))
  253. {
  254. /* Set the default values */
  255. i2sdiv = 2;
  256. i2sodd = 0;
  257. }
  258. /* Write to SPIx I2SPR register the computed value */
  259. hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
  260. /* Configure the I2S with the I2S_InitStruct values */
  261. tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
  262. #if defined(SPI_I2SCFGR_ASTRTEN)
  263. if (hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT)
  264. {
  265. /* Write to SPIx I2SCFGR */
  266. hi2s->Instance->I2SCFGR = tmpreg | SPI_I2SCFGR_ASTRTEN;
  267. }
  268. else
  269. {
  270. /* Write to SPIx I2SCFGR */
  271. hi2s->Instance->I2SCFGR = tmpreg;
  272. }
  273. #else
  274. /* Write to SPIx I2SCFGR */
  275. hi2s->Instance->I2SCFGR = tmpreg;
  276. #endif
  277. hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
  278. hi2s->State= HAL_I2S_STATE_READY;
  279. return HAL_OK;
  280. }
  281. /**
  282. * @brief DeInitializes the I2S peripheral
  283. * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
  284. * the configuration information for I2S module
  285. * @retval HAL status
  286. */
  287. HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
  288. {
  289. /* Check the I2S handle allocation */
  290. if(hi2s == NULL)
  291. {
  292. return HAL_ERROR;
  293. }
  294. hi2s->State = HAL_I2S_STATE_BUSY;
  295. /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
  296. HAL_I2S_MspDeInit(hi2s);
  297. hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
  298. hi2s->State = HAL_I2S_STATE_RESET;
  299. /* Release Lock */
  300. __HAL_UNLOCK(hi2s);
  301. return HAL_OK;
  302. }
  303. /**
  304. * @brief I2S MSP Init
  305. * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
  306. * the configuration information for I2S module
  307. * @retval None
  308. */
  309. __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
  310. {
  311. /* Prevent unused argument(s) compilation warning */
  312. UNUSED(hi2s);
  313. /* NOTE : This function Should not be modified, when the callback is needed,
  314. the HAL_I2S_MspInit could be implemented in the user file
  315. */
  316. }
  317. /**
  318. * @brief I2S MSP DeInit
  319. * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
  320. * the configuration information for I2S module
  321. * @retval None
  322. */
  323. __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
  324. {
  325. /* Prevent unused argument(s) compilation warning */
  326. UNUSED(hi2s);
  327. /* NOTE : This function Should not be modified, when the callback is needed,
  328. the HAL_I2S_MspDeInit could be implemented in the user file
  329. */
  330. }
  331. /**
  332. * @}
  333. */
  334. /** @defgroup I2S_Exported_Functions_Group2 IO operation functions
  335. * @brief Data transfers functions
  336. *
  337. @verbatim
  338. ===============================================================================
  339. ##### IO operation functions #####
  340. ===============================================================================
  341. [..]
  342. This subsection provides a set of functions allowing to manage the I2S data
  343. transfers.
  344. (#) There are two modes of transfer:
  345. (++) Blocking mode : The communication is performed in the polling mode.
  346. The status of all data processing is returned by the same function
  347. after finishing transfer.
  348. (++) No-Blocking mode : The communication is performed using Interrupts
  349. or DMA. These functions return the status of the transfer startup.
  350. The end of the data processing will be indicated through the
  351. dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
  352. using DMA mode.
  353. (#) Blocking mode functions are :
  354. (++) HAL_I2S_Transmit()
  355. (++) HAL_I2S_Receive()
  356. (#) No-Blocking mode functions with Interrupt are :
  357. (++) HAL_I2S_Transmit_IT()
  358. (++) HAL_I2S_Receive_IT()
  359. (#) No-Blocking mode functions with DMA are :
  360. (++) HAL_I2S_Transmit_DMA()
  361. (++) HAL_I2S_Receive_DMA()
  362. (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
  363. (++) HAL_I2S_TxCpltCallback()
  364. (++) HAL_I2S_RxCpltCallback()
  365. (++) HAL_I2S_ErrorCallback()
  366. @endverbatim
  367. * @{
  368. */
  369. /**
  370. * @brief Transmit an amount of data in blocking mode
  371. * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
  372. * the configuration information for I2S module
  373. * @param pData: a 16-bit pointer to data buffer.
  374. * @param Size: number of data sample to be sent:
  375. * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
  376. * configuration phase, the Size parameter means the number of 16-bit data length
  377. * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
  378. * the Size parameter means the number of 16-bit data length.
  379. * @param Timeout: Timeout duration
  380. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
  381. * between Master and Slave(example: audio streaming).
  382. * @retval HAL status
  383. */
  384. HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
  385. {
  386. uint32_t tmp1 = 0;
  387. if((pData == NULL ) || (Size == 0))
  388. {
  389. return HAL_ERROR;
  390. }
  391. if(hi2s->State == HAL_I2S_STATE_READY)
  392. {
  393. tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
  394. if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
  395. {
  396. hi2s->TxXferSize = Size*2;
  397. hi2s->TxXferCount = Size*2;
  398. }
  399. else
  400. {
  401. hi2s->TxXferSize = Size;
  402. hi2s->TxXferCount = Size;
  403. }
  404. /* Process Locked */
  405. __HAL_LOCK(hi2s);
  406. hi2s->State = HAL_I2S_STATE_BUSY_TX;
  407. /* Check if the I2S is already enabled */
  408. if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
  409. {
  410. /* Enable I2S peripheral */
  411. __HAL_I2S_ENABLE(hi2s);
  412. }
  413. while(hi2s->TxXferCount > 0)
  414. {
  415. hi2s->Instance->DR = (*pData++);
  416. hi2s->TxXferCount--;
  417. /* Wait until TXE flag is set */
  418. if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
  419. {
  420. return HAL_TIMEOUT;
  421. }
  422. }
  423. /* Check if Slave mode is selected */
  424. if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
  425. {
  426. /* Wait until Busy flag is reset */
  427. if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
  428. {
  429. return HAL_TIMEOUT;
  430. }
  431. }
  432. hi2s->State = HAL_I2S_STATE_READY;
  433. /* Process Unlocked */
  434. __HAL_UNLOCK(hi2s);
  435. return HAL_OK;
  436. }
  437. else
  438. {
  439. return HAL_BUSY;
  440. }
  441. }
  442. /**
  443. * @brief Receive an amount of data in blocking mode
  444. * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
  445. * the configuration information for I2S module
  446. * @param pData: a 16-bit pointer to data buffer.
  447. * @param Size: number of data sample to be sent:
  448. * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
  449. * configuration phase, the Size parameter means the number of 16-bit data length
  450. * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
  451. * the Size parameter means the number of 16-bit data length.
  452. * @param Timeout: Timeout duration
  453. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
  454. * between Master and Slave(example: audio streaming).
  455. * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
  456. * in continuous way and as the I2S is not disabled at the end of the I2S transaction.
  457. * @retval HAL status
  458. */
  459. HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
  460. {
  461. uint32_t tmp1 = 0;
  462. if((pData == NULL ) || (Size == 0))
  463. {
  464. return HAL_ERROR;
  465. }
  466. if(hi2s->State == HAL_I2S_STATE_READY)
  467. {
  468. tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
  469. if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
  470. {
  471. hi2s->RxXferSize = Size*2;
  472. hi2s->RxXferCount = Size*2;
  473. }
  474. else
  475. {
  476. hi2s->RxXferSize = Size;
  477. hi2s->RxXferCount = Size;
  478. }
  479. /* Process Locked */
  480. __HAL_LOCK(hi2s);
  481. hi2s->State = HAL_I2S_STATE_BUSY_RX;
  482. /* Check if the I2S is already enabled */
  483. if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
  484. {
  485. /* Enable I2S peripheral */
  486. __HAL_I2S_ENABLE(hi2s);
  487. }
  488. /* Check if Master Receiver mode is selected */
  489. if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
  490. {
  491. /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
  492. access to the SPI_SR register. */
  493. __HAL_I2S_CLEAR_OVRFLAG(hi2s);
  494. }
  495. /* Receive data */
  496. while(hi2s->RxXferCount > 0)
  497. {
  498. /* Wait until RXNE flag is set */
  499. if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
  500. {
  501. return HAL_TIMEOUT;
  502. }
  503. (*pData++) = hi2s->Instance->DR;
  504. hi2s->RxXferCount--;
  505. }
  506. hi2s->State = HAL_I2S_STATE_READY;
  507. /* Process Unlocked */
  508. __HAL_UNLOCK(hi2s);
  509. return HAL_OK;
  510. }
  511. else
  512. {
  513. return HAL_BUSY;
  514. }
  515. }
  516. /**
  517. * @brief Transmit an amount of data in non-blocking mode with Interrupt
  518. * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
  519. * the configuration information for I2S module
  520. * @param pData: a 16-bit pointer to data buffer.
  521. * @param Size: number of data sample to be sent:
  522. * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
  523. * configuration phase, the Size parameter means the number of 16-bit data length
  524. * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
  525. * the Size parameter means the number of 16-bit data length.
  526. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
  527. * between Master and Slave(example: audio streaming).
  528. * @retval HAL status
  529. */
  530. HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
  531. {
  532. uint32_t tmp1 = 0;
  533. if(hi2s->State == HAL_I2S_STATE_READY)
  534. {
  535. if((pData == NULL) || (Size == 0))
  536. {
  537. return HAL_ERROR;
  538. }
  539. hi2s->pTxBuffPtr = pData;
  540. tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
  541. if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
  542. {
  543. hi2s->TxXferSize = Size*2;
  544. hi2s->TxXferCount = Size*2;
  545. }
  546. else
  547. {
  548. hi2s->TxXferSize = Size;
  549. hi2s->TxXferCount = Size;
  550. }
  551. /* Process Locked */
  552. __HAL_LOCK(hi2s);
  553. hi2s->State = HAL_I2S_STATE_BUSY_TX;
  554. hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
  555. /* Enable TXE and ERR interrupt */
  556. __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
  557. /* Check if the I2S is already enabled */
  558. if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
  559. {
  560. /* Enable I2S peripheral */
  561. __HAL_I2S_ENABLE(hi2s);
  562. }
  563. /* Process Unlocked */
  564. __HAL_UNLOCK(hi2s);
  565. return HAL_OK;
  566. }
  567. else
  568. {
  569. return HAL_BUSY;
  570. }
  571. }
  572. /**
  573. * @brief Receive an amount of data in non-blocking mode with Interrupt
  574. * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
  575. * the configuration information for I2S module
  576. * @param pData: a 16-bit pointer to the Receive data buffer.
  577. * @param Size: number of data sample to be sent:
  578. * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
  579. * configuration phase, the Size parameter means the number of 16-bit data length
  580. * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
  581. * the Size parameter means the number of 16-bit data length.
  582. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
  583. * between Master and Slave(example: audio streaming).
  584. * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
  585. * between Master and Slave otherwise the I2S interrupt should be optimized.
  586. * @retval HAL status
  587. */
  588. HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
  589. {
  590. uint32_t tmp1 = 0;
  591. if(hi2s->State == HAL_I2S_STATE_READY)
  592. {
  593. if((pData == NULL) || (Size == 0))
  594. {
  595. return HAL_ERROR;
  596. }
  597. hi2s->pRxBuffPtr = pData;
  598. tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
  599. if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
  600. {
  601. hi2s->RxXferSize = Size*2;
  602. hi2s->RxXferCount = Size*2;
  603. }
  604. else
  605. {
  606. hi2s->RxXferSize = Size;
  607. hi2s->RxXferCount = Size;
  608. }
  609. /* Process Locked */
  610. __HAL_LOCK(hi2s);
  611. hi2s->State = HAL_I2S_STATE_BUSY_RX;
  612. hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
  613. /* Enable TXE and ERR interrupt */
  614. __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
  615. /* Check if the I2S is already enabled */
  616. if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
  617. {
  618. /* Enable I2S peripheral */
  619. __HAL_I2S_ENABLE(hi2s);
  620. }
  621. /* Process Unlocked */
  622. __HAL_UNLOCK(hi2s);
  623. return HAL_OK;
  624. }
  625. else
  626. {
  627. return HAL_BUSY;
  628. }
  629. }
  630. /**
  631. * @brief Transmit an amount of data in non-blocking mode with DMA
  632. * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
  633. * the configuration information for I2S module
  634. * @param pData: a 16-bit pointer to the Transmit data buffer.
  635. * @param Size: number of data sample to be sent:
  636. * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
  637. * configuration phase, the Size parameter means the number of 16-bit data length
  638. * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
  639. * the Size parameter means the number of 16-bit data length.
  640. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
  641. * between Master and Slave(example: audio streaming).
  642. * @retval HAL status
  643. */
  644. HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
  645. {
  646. uint32_t *tmp;
  647. uint32_t tmp1 = 0;
  648. if((pData == NULL) || (Size == 0))
  649. {
  650. return HAL_ERROR;
  651. }
  652. if(hi2s->State == HAL_I2S_STATE_READY)
  653. {
  654. hi2s->pTxBuffPtr = pData;
  655. tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
  656. if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
  657. {
  658. hi2s->TxXferSize = Size*2;
  659. hi2s->TxXferCount = Size*2;
  660. }
  661. else
  662. {
  663. hi2s->TxXferSize = Size;
  664. hi2s->TxXferCount = Size;
  665. }
  666. /* Process Locked */
  667. __HAL_LOCK(hi2s);
  668. hi2s->State = HAL_I2S_STATE_BUSY_TX;
  669. hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
  670. /* Set the I2S Tx DMA Half transfer complete callback */
  671. hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
  672. /* Set the I2S Tx DMA transfer complete callback */
  673. hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
  674. /* Set the DMA error callback */
  675. hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
  676. /* Enable the Tx DMA Stream */
  677. tmp = (uint32_t*)&pData;
  678. HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
  679. /* Check if the I2S is already enabled */
  680. if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
  681. {
  682. /* Enable I2S peripheral */
  683. __HAL_I2S_ENABLE(hi2s);
  684. }
  685. /* Check if the I2S Tx request is already enabled */
  686. if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN)
  687. {
  688. /* Enable Tx DMA Request */
  689. hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
  690. }
  691. /* Process Unlocked */
  692. __HAL_UNLOCK(hi2s);
  693. return HAL_OK;
  694. }
  695. else
  696. {
  697. return HAL_BUSY;
  698. }
  699. }
  700. /**
  701. * @brief Receive an amount of data in non-blocking mode with DMA
  702. * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
  703. * the configuration information for I2S module
  704. * @param pData: a 16-bit pointer to the Receive data buffer.
  705. * @param Size: number of data sample to be sent:
  706. * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
  707. * configuration phase, the Size parameter means the number of 16-bit data length
  708. * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
  709. * the Size parameter means the number of 16-bit data length.
  710. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
  711. * between Master and Slave(example: audio streaming).
  712. * @retval HAL status
  713. */
  714. HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
  715. {
  716. uint32_t *tmp;
  717. uint32_t tmp1 = 0;
  718. if((pData == NULL) || (Size == 0))
  719. {
  720. return HAL_ERROR;
  721. }
  722. if(hi2s->State == HAL_I2S_STATE_READY)
  723. {
  724. hi2s->pRxBuffPtr = pData;
  725. tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
  726. if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
  727. {
  728. hi2s->RxXferSize = Size*2;
  729. hi2s->RxXferCount = Size*2;
  730. }
  731. else
  732. {
  733. hi2s->RxXferSize = Size;
  734. hi2s->RxXferCount = Size;
  735. }
  736. /* Process Locked */
  737. __HAL_LOCK(hi2s);
  738. hi2s->State = HAL_I2S_STATE_BUSY_RX;
  739. hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
  740. /* Set the I2S Rx DMA Half transfer complete callback */
  741. hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
  742. /* Set the I2S Rx DMA transfer complete callback */
  743. hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
  744. /* Set the DMA error callback */
  745. hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
  746. /* Check if Master Receiver mode is selected */
  747. if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
  748. {
  749. /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
  750. access to the SPI_SR register. */
  751. __HAL_I2S_CLEAR_OVRFLAG(hi2s);
  752. }
  753. /* Enable the Rx DMA Stream */
  754. tmp = (uint32_t*)&pData;
  755. HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
  756. /* Check if the I2S is already enabled */
  757. if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
  758. {
  759. /* Enable I2S peripheral */
  760. __HAL_I2S_ENABLE(hi2s);
  761. }
  762. /* Check if the I2S Rx request is already enabled */
  763. if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN)
  764. {
  765. /* Enable Rx DMA Request */
  766. hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
  767. }
  768. /* Process Unlocked */
  769. __HAL_UNLOCK(hi2s);
  770. return HAL_OK;
  771. }
  772. else
  773. {
  774. return HAL_BUSY;
  775. }
  776. }
  777. /**
  778. * @brief Pauses the audio stream playing from the Media.
  779. * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
  780. * the configuration information for I2S module
  781. * @retval HAL status
  782. */
  783. __weak HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
  784. {
  785. /* Process Locked */
  786. __HAL_LOCK(hi2s);
  787. if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
  788. {
  789. /* Disable the I2S DMA Tx request */
  790. hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
  791. }
  792. else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
  793. {
  794. /* Disable the I2S DMA Rx request */
  795. hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
  796. }
  797. else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
  798. {
  799. if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
  800. {
  801. /* Disable the I2S DMA Tx request */
  802. hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
  803. }
  804. else
  805. {
  806. /* Disable the I2S DMA Rx request */
  807. hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
  808. }
  809. }
  810. /* Process Unlocked */
  811. __HAL_UNLOCK(hi2s);
  812. return HAL_OK;
  813. }
  814. /**
  815. * @brief Resumes the audio stream playing from the Media.
  816. * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
  817. * the configuration information for I2S module
  818. * @retval HAL status
  819. */
  820. __weak HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
  821. {
  822. /* Process Locked */
  823. __HAL_LOCK(hi2s);
  824. if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
  825. {
  826. /* Enable the I2S DMA Tx request */
  827. hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
  828. }
  829. else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
  830. {
  831. /* Enable the I2S DMA Rx request */
  832. hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
  833. }
  834. else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
  835. {
  836. if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
  837. {
  838. /* Enable the I2S DMA Tx request */
  839. hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
  840. }
  841. else
  842. {
  843. /* Enable the I2S DMA Rx request */
  844. hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
  845. }
  846. }
  847. /* If the I2S peripheral is still not enabled, enable it */
  848. if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0)
  849. {
  850. /* Enable I2S peripheral */
  851. __HAL_I2S_ENABLE(hi2s);
  852. }
  853. /* Process Unlocked */
  854. __HAL_UNLOCK(hi2s);
  855. return HAL_OK;
  856. }
  857. /**
  858. * @brief Resumes the audio stream playing from the Media.
  859. * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
  860. * the configuration information for I2S module
  861. * @retval HAL status
  862. */
  863. __weak HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
  864. {
  865. /* Process Locked */
  866. __HAL_LOCK(hi2s);
  867. /* Disable the I2S Tx/Rx DMA requests */
  868. hi2s->Instance->CR2 &= ~SPI_CR2_TXDMAEN;
  869. hi2s->Instance->CR2 &= ~SPI_CR2_RXDMAEN;
  870. /* Abort the I2S DMA Stream tx */
  871. if(hi2s->hdmatx != NULL)
  872. {
  873. HAL_DMA_Abort(hi2s->hdmatx);
  874. }
  875. /* Abort the I2S DMA Stream rx */
  876. if(hi2s->hdmarx != NULL)
  877. {
  878. HAL_DMA_Abort(hi2s->hdmarx);
  879. }
  880. /* Disable I2S peripheral */
  881. __HAL_I2S_DISABLE(hi2s);
  882. hi2s->State = HAL_I2S_STATE_READY;
  883. /* Process Unlocked */
  884. __HAL_UNLOCK(hi2s);
  885. return HAL_OK;
  886. }
  887. /**
  888. * @brief This function handles I2S interrupt request.
  889. * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
  890. * the configuration information for I2S module
  891. * @retval None
  892. */
  893. __weak void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
  894. {
  895. uint32_t tmp1 = 0, tmp2 = 0;
  896. if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
  897. {
  898. tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE);
  899. tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE);
  900. /* I2S in mode Receiver ------------------------------------------------*/
  901. if((tmp1 != RESET) && (tmp2 != RESET))
  902. {
  903. I2S_Receive_IT(hi2s);
  904. }
  905. tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR);
  906. tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
  907. /* I2S Overrun error interrupt occurred ---------------------------------*/
  908. if((tmp1 != RESET) && (tmp2 != RESET))
  909. {
  910. __HAL_I2S_CLEAR_OVRFLAG(hi2s);
  911. hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
  912. }
  913. }
  914. if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
  915. {
  916. tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE);
  917. tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE);
  918. /* I2S in mode Transmitter -----------------------------------------------*/
  919. if((tmp1 != RESET) && (tmp2 != RESET))
  920. {
  921. I2S_Transmit_IT(hi2s);
  922. }
  923. tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR);
  924. tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
  925. /* I2S Underrun error interrupt occurred --------------------------------*/
  926. if((tmp1 != RESET) && (tmp2 != RESET))
  927. {
  928. __HAL_I2S_CLEAR_UDRFLAG(hi2s);
  929. hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
  930. }
  931. }
  932. /* Call the Error call Back in case of Errors */
  933. if(hi2s->ErrorCode != HAL_I2S_ERROR_NONE)
  934. {
  935. /* Set the I2S state ready to be able to start again the process */
  936. hi2s->State= HAL_I2S_STATE_READY;
  937. HAL_I2S_ErrorCallback(hi2s);
  938. }
  939. }
  940. /**
  941. * @brief Tx Transfer Half completed callbacks
  942. * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
  943. * the configuration information for I2S module
  944. * @retval None
  945. */
  946. __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
  947. {
  948. /* Prevent unused argument(s) compilation warning */
  949. UNUSED(hi2s);
  950. /* NOTE : This function Should not be modified, when the callback is needed,
  951. the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
  952. */
  953. }
  954. /**
  955. * @brief Tx Transfer completed callbacks
  956. * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
  957. * the configuration information for I2S module
  958. * @retval None
  959. */
  960. __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
  961. {
  962. /* Prevent unused argument(s) compilation warning */
  963. UNUSED(hi2s);
  964. /* NOTE : This function Should not be modified, when the callback is needed,
  965. the HAL_I2S_TxCpltCallback could be implemented in the user file
  966. */
  967. }
  968. /**
  969. * @brief Rx Transfer half completed callbacks
  970. * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
  971. * the configuration information for I2S module
  972. * @retval None
  973. */
  974. __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
  975. {
  976. /* Prevent unused argument(s) compilation warning */
  977. UNUSED(hi2s);
  978. /* NOTE : This function Should not be modified, when the callback is needed,
  979. the HAL_I2S_RxCpltCallback could be implemented in the user file
  980. */
  981. }
  982. /**
  983. * @brief Rx Transfer completed callbacks
  984. * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
  985. * the configuration information for I2S module
  986. * @retval None
  987. */
  988. __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
  989. {
  990. /* Prevent unused argument(s) compilation warning */
  991. UNUSED(hi2s);
  992. /* NOTE : This function Should not be modified, when the callback is needed,
  993. the HAL_I2S_RxCpltCallback could be implemented in the user file
  994. */
  995. }
  996. /**
  997. * @brief I2S error callbacks
  998. * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
  999. * the configuration information for I2S module
  1000. * @retval None
  1001. */
  1002. __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
  1003. {
  1004. /* Prevent unused argument(s) compilation warning */
  1005. UNUSED(hi2s);
  1006. /* NOTE : This function Should not be modified, when the callback is needed,
  1007. the HAL_I2S_ErrorCallback could be implemented in the user file
  1008. */
  1009. }
  1010. /**
  1011. * @}
  1012. */
  1013. /** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
  1014. * @brief Peripheral State functions
  1015. @verbatim
  1016. ===============================================================================
  1017. ##### Peripheral State and Errors functions #####
  1018. ===============================================================================
  1019. [..]
  1020. This subsection permits to get in run-time the status of the peripheral
  1021. and the data flow.
  1022. @endverbatim
  1023. * @{
  1024. */
  1025. /**
  1026. * @brief Return the I2S state
  1027. * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
  1028. * the configuration information for I2S module
  1029. * @retval HAL state
  1030. */
  1031. HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
  1032. {
  1033. return hi2s->State;
  1034. }
  1035. /**
  1036. * @brief Return the I2S error code
  1037. * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
  1038. * the configuration information for I2S module
  1039. * @retval I2S Error Code
  1040. */
  1041. uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
  1042. {
  1043. return hi2s->ErrorCode;
  1044. }
  1045. /**
  1046. * @}
  1047. */
  1048. /**
  1049. * @brief DMA I2S transmit process half complete callback
  1050. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
  1051. * the configuration information for the specified DMA module.
  1052. * @retval None
  1053. */
  1054. void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
  1055. {
  1056. I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
  1057. HAL_I2S_TxHalfCpltCallback(hi2s);
  1058. }
  1059. /**
  1060. * @brief DMA I2S receive process half complete callback
  1061. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
  1062. * the configuration information for the specified DMA module.
  1063. * @retval None
  1064. */
  1065. void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
  1066. {
  1067. I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
  1068. HAL_I2S_RxHalfCpltCallback(hi2s);
  1069. }
  1070. /**
  1071. * @brief DMA I2S communication error callback
  1072. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
  1073. * the configuration information for the specified DMA module.
  1074. * @retval None
  1075. */
  1076. void I2S_DMAError(DMA_HandleTypeDef *hdma)
  1077. {
  1078. I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
  1079. hi2s->TxXferCount = 0;
  1080. hi2s->RxXferCount = 0;
  1081. hi2s->State= HAL_I2S_STATE_READY;
  1082. hi2s->ErrorCode |= HAL_I2S_ERROR_DMA;
  1083. HAL_I2S_ErrorCallback(hi2s);
  1084. }
  1085. /**
  1086. * @brief Transmit an amount of data in non-blocking mode with Interrupt
  1087. * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
  1088. * the configuration information for I2S module
  1089. * @retval HAL status
  1090. */
  1091. HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
  1092. {
  1093. if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
  1094. {
  1095. /* Process Locked */
  1096. __HAL_LOCK(hi2s);
  1097. /* Transmit data */
  1098. hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
  1099. hi2s->TxXferCount--;
  1100. if(hi2s->TxXferCount == 0)
  1101. {
  1102. /* Disable TXE and ERR interrupt */
  1103. __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
  1104. hi2s->State = HAL_I2S_STATE_READY;
  1105. /* Process Unlocked */
  1106. __HAL_UNLOCK(hi2s);
  1107. HAL_I2S_TxCpltCallback(hi2s);
  1108. }
  1109. else
  1110. {
  1111. /* Process Unlocked */
  1112. __HAL_UNLOCK(hi2s);
  1113. }
  1114. return HAL_OK;
  1115. }
  1116. else
  1117. {
  1118. return HAL_BUSY;
  1119. }
  1120. }
  1121. /**
  1122. * @brief Receive an amount of data in non-blocking mode with Interrupt
  1123. * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
  1124. * the configuration information for I2S module
  1125. * @retval HAL status
  1126. */
  1127. HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
  1128. {
  1129. if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
  1130. {
  1131. /* Process Locked */
  1132. __HAL_LOCK(hi2s);
  1133. /* Receive data */
  1134. (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
  1135. hi2s->RxXferCount--;
  1136. /* Check if Master Receiver mode is selected */
  1137. if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
  1138. {
  1139. /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
  1140. access to the SPI_SR register. */
  1141. __HAL_I2S_CLEAR_OVRFLAG(hi2s);
  1142. }
  1143. if(hi2s->RxXferCount == 0)
  1144. {
  1145. /* Disable RXNE and ERR interrupt */
  1146. __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_RXNE | I2S_IT_ERR);
  1147. hi2s->State = HAL_I2S_STATE_READY;
  1148. /* Process Unlocked */
  1149. __HAL_UNLOCK(hi2s);
  1150. HAL_I2S_RxCpltCallback(hi2s);
  1151. }
  1152. else
  1153. {
  1154. /* Process Unlocked */
  1155. __HAL_UNLOCK(hi2s);
  1156. }
  1157. return HAL_OK;
  1158. }
  1159. else
  1160. {
  1161. return HAL_BUSY;
  1162. }
  1163. }
  1164. /**
  1165. * @brief This function handles I2S Communication Timeout.
  1166. * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
  1167. * the configuration information for I2S module
  1168. * @param Flag: Flag checked
  1169. * @param Status: Value of the flag expected
  1170. * @param Timeout: Duration of the timeout
  1171. * @retval HAL status
  1172. */
  1173. HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout)
  1174. {
  1175. uint32_t tickstart = 0;
  1176. /* Get tick */
  1177. tickstart = HAL_GetTick();
  1178. /* Wait until flag is set */
  1179. if(Status == RESET)
  1180. {
  1181. while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
  1182. {
  1183. if(Timeout != HAL_MAX_DELAY)
  1184. {
  1185. if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
  1186. {
  1187. /* Set the I2S State ready */
  1188. hi2s->State= HAL_I2S_STATE_READY;
  1189. /* Process Unlocked */
  1190. __HAL_UNLOCK(hi2s);
  1191. return HAL_TIMEOUT;
  1192. }
  1193. }
  1194. }
  1195. }
  1196. else
  1197. {
  1198. while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
  1199. {
  1200. if(Timeout != HAL_MAX_DELAY)
  1201. {
  1202. if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
  1203. {
  1204. /* Set the I2S State ready */
  1205. hi2s->State= HAL_I2S_STATE_READY;
  1206. /* Process Unlocked */
  1207. __HAL_UNLOCK(hi2s);
  1208. return HAL_TIMEOUT;
  1209. }
  1210. }
  1211. }
  1212. }
  1213. return HAL_OK;
  1214. }
  1215. /**
  1216. * @}
  1217. */
  1218. #endif /* HAL_I2S_MODULE_ENABLED */
  1219. /**
  1220. * @}
  1221. */
  1222. /**
  1223. * @}
  1224. */
  1225. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/