stm32f4xx_ll_sdmmc.c 19 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f4xx_ll_sdmmc.c
  4. * @author MCD Application Team
  5. * @version V1.4.3
  6. * @date 11-December-2015
  7. * @brief SDMMC Low Layer HAL module driver.
  8. *
  9. * This file provides firmware functions to manage the following
  10. * functionalities of the SDMMC peripheral:
  11. * + Initialization/de-initialization functions
  12. * + I/O operation functions
  13. * + Peripheral Control functions
  14. * + Peripheral State functions
  15. *
  16. @verbatim
  17. ==============================================================================
  18. ##### SDMMC peripheral features #####
  19. ==============================================================================
  20. [..] The SD/SDIO MMC card host interface (SDIO) provides an interface between the APB2
  21. peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDIO cards and CE-ATA
  22. devices.
  23. [..] The SDIO features include the following:
  24. (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support
  25. for three different databus modes: 1-bit (default), 4-bit and 8-bit
  26. (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility)
  27. (+) Full compliance with SD Memory Card Specifications Version 2.0
  28. (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two
  29. different data bus modes: 1-bit (default) and 4-bit
  30. (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol
  31. Rev1.1)
  32. (+) Data transfer up to 48 MHz for the 8 bit mode
  33. (+) Data and command output enable signals to control external bidirectional drivers.
  34. ##### How to use this driver #####
  35. ==============================================================================
  36. [..]
  37. This driver is a considered as a driver of service for external devices drivers
  38. that interfaces with the SDIO peripheral.
  39. According to the device used (SD card/ MMC card / SDIO card ...), a set of APIs
  40. is used in the device's driver to perform SDIO operations and functionalities.
  41. This driver is almost transparent for the final user, it is only used to implement other
  42. functionalities of the external device.
  43. [..]
  44. (+) The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output of PLL
  45. (PLL48CLK). Before start working with SDIO peripheral make sure that the
  46. PLL is well configured.
  47. The SDIO peripheral uses two clock signals:
  48. (++) SDIO adapter clock (SDIOCLK = 48 MHz)
  49. (++) APB2 bus clock (PCLK2)
  50. -@@- PCLK2 and SDIO_CK clock frequencies must respect the following condition:
  51. Frequency(PCLK2) >= (3 / 8 x Frequency(SDIO_CK))
  52. (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDIO
  53. peripheral.
  54. (+) Enable the Power ON State using the SDIO_PowerState_ON(SDIOx)
  55. function and disable it using the function SDIO_PowerState_OFF(SDIOx).
  56. (+) Enable/Disable the clock using the __SDIO_ENABLE()/__SDIO_DISABLE() macros.
  57. (+) Enable/Disable the peripheral interrupts using the macros __SDIO_ENABLE_IT(hsdio, IT)
  58. and __SDIO_DISABLE_IT(hsdio, IT) if you need to use interrupt mode.
  59. (+) When using the DMA mode
  60. (++) Configure the DMA in the MSP layer of the external device
  61. (++) Active the needed channel Request
  62. (++) Enable the DMA using __SDIO_DMA_ENABLE() macro or Disable it using the macro
  63. __SDIO_DMA_DISABLE().
  64. (+) To control the CPSM (Command Path State Machine) and send
  65. commands to the card use the SDIO_SendCommand(SDIOx),
  66. SDIO_GetCommandResponse() and SDIO_GetResponse() functions. First, user has
  67. to fill the command structure (pointer to SDIO_CmdInitTypeDef) according
  68. to the selected command to be sent.
  69. The parameters that should be filled are:
  70. (++) Command Argument
  71. (++) Command Index
  72. (++) Command Response type
  73. (++) Command Wait
  74. (++) CPSM Status (Enable or Disable).
  75. -@@- To check if the command is well received, read the SDIO_CMDRESP
  76. register using the SDIO_GetCommandResponse().
  77. The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the
  78. SDIO_GetResponse() function.
  79. (+) To control the DPSM (Data Path State Machine) and send/receive
  80. data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(),
  81. SDIO_ReadFIFO(), DIO_WriteFIFO() and SDIO_GetFIFOCount() functions.
  82. *** Read Operations ***
  83. =======================
  84. [..]
  85. (#) First, user has to fill the data structure (pointer to
  86. SDIO_DataInitTypeDef) according to the selected data type to be received.
  87. The parameters that should be filled are:
  88. (++) Data Timeout
  89. (++) Data Length
  90. (++) Data Block size
  91. (++) Data Transfer direction: should be from card (To SDIO)
  92. (++) Data Transfer mode
  93. (++) DPSM Status (Enable or Disable)
  94. (#) Configure the SDIO resources to receive the data from the card
  95. according to selected transfer mode (Refer to Step 8, 9 and 10).
  96. (#) Send the selected Read command (refer to step 11).
  97. (#) Use the SDIO flags/interrupts to check the transfer status.
  98. *** Write Operations ***
  99. ========================
  100. [..]
  101. (#) First, user has to fill the data structure (pointer to
  102. SDIO_DataInitTypeDef) according to the selected data type to be received.
  103. The parameters that should be filled are:
  104. (++) Data Timeout
  105. (++) Data Length
  106. (++) Data Block size
  107. (++) Data Transfer direction: should be to card (To CARD)
  108. (++) Data Transfer mode
  109. (++) DPSM Status (Enable or Disable)
  110. (#) Configure the SDIO resources to send the data to the card according to
  111. selected transfer mode.
  112. (#) Send the selected Write command.
  113. (#) Use the SDIO flags/interrupts to check the transfer status.
  114. @endverbatim
  115. ******************************************************************************
  116. * @attention
  117. *
  118. * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
  119. *
  120. * Redistribution and use in source and binary forms, with or without modification,
  121. * are permitted provided that the following conditions are met:
  122. * 1. Redistributions of source code must retain the above copyright notice,
  123. * this list of conditions and the following disclaimer.
  124. * 2. Redistributions in binary form must reproduce the above copyright notice,
  125. * this list of conditions and the following disclaimer in the documentation
  126. * and/or other materials provided with the distribution.
  127. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  128. * may be used to endorse or promote products derived from this software
  129. * without specific prior written permission.
  130. *
  131. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  132. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  133. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  134. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  135. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  136. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  137. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  138. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  139. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  140. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  141. *
  142. ******************************************************************************
  143. */
  144. /* Includes ------------------------------------------------------------------*/
  145. #include "stm32f4xx_hal.h"
  146. /** @addtogroup STM32F4xx_HAL_Driver
  147. * @{
  148. */
  149. /** @defgroup SDMMC_LL SDMMC Low Layer
  150. * @brief Low layer module for SD and MMC driver
  151. * @{
  152. */
  153. #if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED)
  154. #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
  155. defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
  156. defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
  157. defined(STM32F469xx) || defined(STM32F479xx)
  158. /* Private typedef -----------------------------------------------------------*/
  159. /* Private define ------------------------------------------------------------*/
  160. /* Private macro -------------------------------------------------------------*/
  161. /* Private variables ---------------------------------------------------------*/
  162. /* Private function prototypes -----------------------------------------------*/
  163. /* Private functions ---------------------------------------------------------*/
  164. /** @defgroup SDMMC_LL_Exported_Functions SDMMC_LL Exported Functions
  165. * @{
  166. */
  167. /** @defgroup HAL_SDMMC_LL_Group1 Initialization/de-initialization functions
  168. * @brief Initialization and Configuration functions
  169. *
  170. @verbatim
  171. ===============================================================================
  172. ##### Initialization/de-initialization functions #####
  173. ===============================================================================
  174. [..] This section provides functions allowing to:
  175. @endverbatim
  176. * @{
  177. */
  178. /**
  179. * @brief Initializes the SDIO according to the specified
  180. * parameters in the SDIO_InitTypeDef and create the associated handle.
  181. * @param SDIOx: Pointer to SDIO register base
  182. * @param Init: SDIO initialization structure
  183. * @retval HAL status
  184. */
  185. HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init)
  186. {
  187. uint32_t tmpreg = 0;
  188. /* Check the parameters */
  189. assert_param(IS_SDIO_ALL_INSTANCE(SDIOx));
  190. assert_param(IS_SDIO_CLOCK_EDGE(Init.ClockEdge));
  191. assert_param(IS_SDIO_CLOCK_BYPASS(Init.ClockBypass));
  192. assert_param(IS_SDIO_CLOCK_POWER_SAVE(Init.ClockPowerSave));
  193. assert_param(IS_SDIO_BUS_WIDE(Init.BusWide));
  194. assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));
  195. assert_param(IS_SDIO_CLKDIV(Init.ClockDiv));
  196. /* Set SDIO configuration parameters */
  197. tmpreg |= (Init.ClockEdge |\
  198. Init.ClockBypass |\
  199. Init.ClockPowerSave |\
  200. Init.BusWide |\
  201. Init.HardwareFlowControl |\
  202. Init.ClockDiv
  203. );
  204. /* Write to SDIO CLKCR */
  205. MODIFY_REG(SDIOx->CLKCR, CLKCR_CLEAR_MASK, tmpreg);
  206. return HAL_OK;
  207. }
  208. /**
  209. * @}
  210. */
  211. /** @defgroup HAL_SDMMC_LL_Group2 I/O operation functions
  212. * @brief Data transfers functions
  213. *
  214. @verbatim
  215. ===============================================================================
  216. ##### I/O operation functions #####
  217. ===============================================================================
  218. [..]
  219. This subsection provides a set of functions allowing to manage the SDIO data
  220. transfers.
  221. @endverbatim
  222. * @{
  223. */
  224. /**
  225. * @brief Read data (word) from Rx FIFO in blocking mode (polling)
  226. * @param SDIOx: Pointer to SDIO register base
  227. * @retval HAL status
  228. */
  229. uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx)
  230. {
  231. /* Read data from Rx FIFO */
  232. return (SDIOx->FIFO);
  233. }
  234. /**
  235. * @brief Write data (word) to Tx FIFO in blocking mode (polling)
  236. * @param SDIOx: Pointer to SDIO register base
  237. * @param pWriteData: pointer to data to write
  238. * @retval HAL status
  239. */
  240. HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData)
  241. {
  242. /* Write data to FIFO */
  243. SDIOx->FIFO = *pWriteData;
  244. return HAL_OK;
  245. }
  246. /**
  247. * @}
  248. */
  249. /** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions
  250. * @brief management functions
  251. *
  252. @verbatim
  253. ===============================================================================
  254. ##### Peripheral Control functions #####
  255. ===============================================================================
  256. [..]
  257. This subsection provides a set of functions allowing to control the SDIO data
  258. transfers.
  259. @endverbatim
  260. * @{
  261. */
  262. /**
  263. * @brief Set SDIO Power state to ON.
  264. * @param SDIOx: Pointer to SDIO register base
  265. * @retval HAL status
  266. */
  267. HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx)
  268. {
  269. /* Set power state to ON */
  270. SDIOx->POWER = SDIO_POWER_PWRCTRL;
  271. return HAL_OK;
  272. }
  273. /**
  274. * @brief Set SDIO Power state to OFF.
  275. * @param SDIOx: Pointer to SDIO register base
  276. * @retval HAL status
  277. */
  278. HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx)
  279. {
  280. /* Set power state to OFF */
  281. SDIOx->POWER = (uint32_t)0x00000000;
  282. return HAL_OK;
  283. }
  284. /**
  285. * @brief Get SDIO Power state.
  286. * @param SDIOx: Pointer to SDIO register base
  287. * @retval Power status of the controller. The returned value can be one of the
  288. * following values:
  289. * - 0x00: Power OFF
  290. * - 0x02: Power UP
  291. * - 0x03: Power ON
  292. */
  293. uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx)
  294. {
  295. return (SDIOx->POWER & SDIO_POWER_PWRCTRL);
  296. }
  297. /**
  298. * @brief Configure the SDIO command path according to the specified parameters in
  299. * SDIO_CmdInitTypeDef structure and send the command
  300. * @param SDIOx: Pointer to SDIO register base
  301. * @param SDIO_CmdInitStruct: pointer to a SDIO_CmdInitTypeDef structure that contains
  302. * the configuration information for the SDIO command
  303. * @retval HAL status
  304. */
  305. HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
  306. {
  307. uint32_t tmpreg = 0;
  308. /* Check the parameters */
  309. assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->CmdIndex));
  310. assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->Response));
  311. assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->WaitForInterrupt));
  312. assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->CPSM));
  313. /* Set the SDIO Argument value */
  314. SDIOx->ARG = SDIO_CmdInitStruct->Argument;
  315. /* Set SDIO command parameters */
  316. tmpreg |= (uint32_t)(SDIO_CmdInitStruct->CmdIndex |\
  317. SDIO_CmdInitStruct->Response |\
  318. SDIO_CmdInitStruct->WaitForInterrupt |\
  319. SDIO_CmdInitStruct->CPSM);
  320. /* Write to SDIO CMD register */
  321. MODIFY_REG(SDIOx->CMD, CMD_CLEAR_MASK, tmpreg);
  322. return HAL_OK;
  323. }
  324. /**
  325. * @brief Return the command index of last command for which response received
  326. * @param SDIOx: Pointer to SDIO register base
  327. * @retval Command index of the last command response received
  328. */
  329. uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx)
  330. {
  331. return (uint8_t)(SDIOx->RESPCMD);
  332. }
  333. /**
  334. * @brief Return the response received from the card for the last command
  335. * @param SDIO_RESP: Specifies the SDIO response register.
  336. * This parameter can be one of the following values:
  337. * @arg SDIO_RESP1: Response Register 1
  338. * @arg SDIO_RESP2: Response Register 2
  339. * @arg SDIO_RESP3: Response Register 3
  340. * @arg SDIO_RESP4: Response Register 4
  341. * @retval The Corresponding response register value
  342. */
  343. uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
  344. {
  345. __IO uint32_t tmp = 0;
  346. /* Check the parameters */
  347. assert_param(IS_SDIO_RESP(SDIO_RESP));
  348. /* Get the response */
  349. tmp = SDIO_RESP_ADDR + SDIO_RESP;
  350. return (*(__IO uint32_t *) tmp);
  351. }
  352. /**
  353. * @brief Configure the SDIO data path according to the specified
  354. * parameters in the SDIO_DataInitTypeDef.
  355. * @param SDIOx: Pointer to SDIO register base
  356. * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure
  357. * that contains the configuration information for the SDIO command.
  358. * @retval HAL status
  359. */
  360. HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct)
  361. {
  362. uint32_t tmpreg = 0;
  363. /* Check the parameters */
  364. assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->DataLength));
  365. assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->DataBlockSize));
  366. assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->TransferDir));
  367. assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->TransferMode));
  368. assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->DPSM));
  369. /* Set the SDIO Data Timeout value */
  370. SDIOx->DTIMER = SDIO_DataInitStruct->DataTimeOut;
  371. /* Set the SDIO DataLength value */
  372. SDIOx->DLEN = SDIO_DataInitStruct->DataLength;
  373. /* Set the SDIO data configuration parameters */
  374. tmpreg |= (uint32_t)(SDIO_DataInitStruct->DataBlockSize |\
  375. SDIO_DataInitStruct->TransferDir |\
  376. SDIO_DataInitStruct->TransferMode |\
  377. SDIO_DataInitStruct->DPSM);
  378. /* Write to SDIO DCTRL */
  379. MODIFY_REG(SDIOx->DCTRL, DCTRL_CLEAR_MASK, tmpreg);
  380. return HAL_OK;
  381. }
  382. /**
  383. * @brief Returns number of remaining data bytes to be transferred.
  384. * @param SDIOx: Pointer to SDIO register base
  385. * @retval Number of remaining data bytes to be transferred
  386. */
  387. uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx)
  388. {
  389. return (SDIOx->DCOUNT);
  390. }
  391. /**
  392. * @brief Get the FIFO data
  393. * @param SDIOx: Pointer to SDIO register base
  394. * @retval Data received
  395. */
  396. uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx)
  397. {
  398. return (SDIOx->FIFO);
  399. }
  400. /**
  401. * @brief Sets one of the two options of inserting read wait interval.
  402. * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
  403. * This parameter can be:
  404. * @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDIOCLK
  405. * @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDIO_DATA2
  406. * @retval None
  407. */
  408. HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
  409. {
  410. /* Check the parameters */
  411. assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
  412. *(__IO uint32_t *)DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
  413. return HAL_OK;
  414. }
  415. /**
  416. * @}
  417. */
  418. /**
  419. * @}
  420. */
  421. #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
  422. STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
  423. #endif /* (HAL_SD_MODULE_ENABLED) || (HAL_MMC_MODULE_ENABLED) */
  424. /**
  425. * @}
  426. */
  427. /**
  428. * @}
  429. */
  430. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/