mma7455l.h 5.6 KB

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  1. /***************************************************************************//**
  2. * @file mma7455l.c
  3. * @brief Header file of Freescale MMA7455L 3 axis Low-g digital output
  4. * accelerometer
  5. * COPYRIGHT (C) 2012, RT-Thread Development Team
  6. * @author onelife
  7. * @version 1.0
  8. *******************************************************************************
  9. * @section License
  10. * The license and distribution terms for this file may be found in the file
  11. * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
  12. *******************************************************************************
  13. * @section Change Logs
  14. * Date Author Notes
  15. * 2011-08-02 onelife Initial creation
  16. ******************************************************************************/
  17. #ifndef __MMA7455L_H__
  18. #define __MMA7455L_H__
  19. #define XOUTL 0x00 //00 10 bits output value X LSB (Read only)
  20. #define XOUTH 0x01 //01 10 bits output value X MSB (Read only)
  21. #define YOUTL 0x02 //02 10 bits output value Y LSB (Read only)
  22. #define YOUTH 0x03 //03 10 bits output value Y MSB (Read only)
  23. #define ZOUTL 0x04 //04 10 bits output value Z LSB (Read only)
  24. #define ZOUTH 0x05 //05 10 bits output value Z MSB (Read only)
  25. #define XOUT8 0x06 //06 8 bits Output value X (Read only)
  26. #define YOUT8 0x07 //07 8 bits Output value Y (Read only)
  27. #define ZOUT8 0x08 //08 8 bits Output value Z (Read only)
  28. #define STATUS 0x09 //09 Status registers (Read only)
  29. #define DETSRC 0x0A //10 Detection source registers (Read only)
  30. #define TOUT 0x0B //11 Temperature output value (Optional)
  31. #define RESERVED1 0x0C //12 Reserved
  32. #define I2CAD 0x0D //13 I2C device address (Bit[6:0]: Read only, Bit[7]: Read/Write)
  33. #define USRINF 0x0E //14 User information (Optional, Read only)
  34. #define WHOAMI 0x0F //15 Who am I value (Optional, Read only)
  35. #define XOFFL 0x10 //16 Offset drift X value (LSB) (Read/Write)
  36. #define XOFFH 0x11 //17 Offset drift X value (MSB) (Read/Write)
  37. #define YOFFL 0x12 //18 Offset drift Y value (LSB) (Read/Write)
  38. #define YOFFH 0x13 //19 Offset drift Y value (MSB) (Read/Write)
  39. #define ZOFFL 0x14 //20 Offset drift Z value (LSB) (Read/Write)
  40. #define ZOFFH 0x15 //21 Offset drift Z value (MSB) (Read/Write)
  41. #define MCTL 0x16 //22 Mode control (Read/Write)
  42. #define INTRST 0x17 //23 Interrupt latch reset (Read/Write)
  43. #define CTL1 0x18 //24 Control 1 (Read/Write)
  44. #define CTL2 0x19 //25 Control 2 (Read/Write)
  45. #define LDTH 0x1A //26 Level detection threshold limit value (Read/Write)
  46. #define PDTH 0x1B //27 Pulse detection threshold limit value (Read/Write)
  47. #define PW 0x1C //28 Pulse duration value (Read/Write)
  48. #define LT 0x1D //29 Latency time value (Read/Write)
  49. #define TW 0x1E //30 Time window for second pulse value(Read/Write)
  50. #define RESERVED2 0x1F //31 Reserved
  51. /* For DETSRC */
  52. #define DETSRC_INT_1 (0x01 << 0)
  53. #define DETSRC_INT_2 (0x01 << 1)
  54. #define DETSRC_PULSE_Z (0x01 << 2)
  55. #define DETSRC_PULSE_Y (0x01 << 3)
  56. #define DETSRC_PULSE_X (0x01 << 4)
  57. #define DETSRC_LEVEL_Z (0x01 << 5)
  58. #define DETSRC_LEVEL_Y (0x01 << 6)
  59. #define DETSRC_LEVEL_X (0x01 << 7)
  60. /* For MCTL */
  61. #define MCTL_SHIFT_MODE (0)
  62. #define MCTL_SHIFT_G (2)
  63. #define MCTL_MASK_MODE (0x03)
  64. #define MCTL_MASK_G (0x0c)
  65. #define MCTL_MODE_STANDBY (0x00 << MCTL_SHIFT_MODE)
  66. #define MCTL_MODE_MEASUREMENT (0x01 << MCTL_SHIFT_MODE)
  67. #define MCTL_MODE_LEVEL (0x02 << MCTL_SHIFT_MODE)
  68. #define MCTL_MODE_PULSE (0x03 << MCTL_SHIFT_MODE)
  69. #define MCTL_RANGE_8G (0x00 << MCTL_SHIFT_G)
  70. #define MCTL_RANGE_4G (0x02 << MCTL_SHIFT_G)
  71. #define MCTL_RANGE_2G (0x01 << MCTL_SHIFT_G)
  72. #define MCTL_PIN_INT1 (0x01 << 6)
  73. /* For INTRST */
  74. #define INTRST_INT_1 (0x01 << 0)
  75. #define INTRST_INT_2 (0x01 << 1)
  76. /* For CTL1 */
  77. #define CTL1_SHIFT_INTPIN (0)
  78. #define CTL1_SHIFT_INT (1)
  79. #define CTL1_SHIFT_AXES (3)
  80. #define CTL1_SHIFT_THRESHOLD (6)
  81. #define CTL1_SHIFT_BANDWIDTH (7)
  82. #define CTL1_MASK_AXES (0x38)
  83. #define CTL1_INTPIN_INVERSE (0x01 << CTL1_SHIFT_INTPIN)
  84. #define CTL1_INT_LEVEL_PULSE (0x00 << CTL1_SHIFT_INT)
  85. #define CTL1_INT_PULSE_LEVEL (0x01 << CTL1_SHIFT_INT)
  86. #define CTL1_INT_SINGLE_DOUBLE (0x02 << CTL1_SHIFT_INT)
  87. #define CTL1_X_DISABLE (0x01 << CTL1_SHIFT_AXES)
  88. #define CTL1_Y_DISABLE (0x02 << CTL1_SHIFT_AXES)
  89. #define CTL1_Z_DISABLE (0x04 << CTL1_SHIFT_AXES)
  90. #define CTL1_THRESHOLD_ABSOLUTE (0x00 << CTL1_SHIFT_THRESHOLD)
  91. #define CTL1_THRESHOLD_INTEGER (0x01 << CTL1_SHIFT_THRESHOLD)
  92. #define CTL1_BANDWIDTH_62_5HZ (0x00 << CTL1_SHIFT_BANDWIDTH)
  93. #define CTL1_BANDWIDTH_125HZ (0x01 << CTL1_SHIFT_BANDWIDTH)
  94. /* For CTL2 */
  95. #define CTL1_SHIFT_LEVEL (0)
  96. #define CTL1_SHIFT_PULSE (1)
  97. #define CTL1_SHIFT_DRIVE (2)
  98. #define CTL2_LEVEL_OR (0x00 << CTL1_SHIFT_LEVEL)
  99. #define CTL2_LEVEL_AND (0x01 << CTL1_SHIFT_LEVEL)
  100. #define CTL2_PULSE_OR (0x00 << CTL1_SHIFT_PULSE)
  101. #define CTL2_PULSE_AND (0x01 << CTL1_SHIFT_PULSE)
  102. #define CTL2_DRIVE_STANDARD (0x00 << CTL1_SHIFT_DRIVE)
  103. #define CTL2_DRIVE_STRONG (0x01 << CTL1_SHIFT_DRIVE)
  104. #endif /* __MMA7455L_H__ */