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startup_gcc.s 5.5 KB

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  1. /*
  2. * Copyright (c) 2019, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2019-05-05 jg1uaa the first version
  9. */
  10. #include "../rtconfig.h"
  11. /* Interrupt Vectors */
  12. .section .isr_vector
  13. .thumb
  14. .align 0
  15. .long _estack // MSP default value
  16. .long Reset_Handler + 1 // 1: Reset
  17. .long default_handler + 1 // 2: NMI
  18. .long HardFault_Handler + 1 // 3: HardFault
  19. .long default_handler + 1 // 4: reserved
  20. .long default_handler + 1 // 5: reserved
  21. .long default_handler + 1 // 6: reserved
  22. .long default_handler + 1 // 7: reserved
  23. .long default_handler + 1 // 8: reserved
  24. .long default_handler + 1 // 9: reserved
  25. .long default_handler + 1 // 10: reserved
  26. .long default_handler + 1 // 11: SVCall
  27. .long default_handler + 1 // 12: reserved
  28. .long default_handler + 1 // 13: reserved
  29. .long PendSV_Handler + 1 // 14: PendSV
  30. .long SysTick_Handler + 1 // 15: SysTick
  31. .long default_handler + 1 // 16: External Interrupt(0)
  32. .long default_handler + 1 // 17: External Interrupt(1)
  33. .long default_handler + 1 // 18: External Interrupt(2)
  34. .long default_handler + 1 // 19: External Interrupt(3)
  35. .long default_handler + 1 // 20: External Interrupt(4)
  36. .long default_handler + 1 // 21: External Interrupt(5)
  37. .long default_handler + 1 // 22: External Interrupt(6)
  38. .long default_handler + 1 // 23: External Interrupt(7)
  39. .long default_handler + 1 // 24: External Interrupt(8)
  40. .long default_handler + 1 // 25: External Interrupt(9)
  41. .long default_handler + 1 // 26: External Interrupt(10)
  42. .long default_handler + 1 // 27: External Interrupt(11)
  43. .long default_handler + 1 // 28: External Interrupt(12)
  44. .long default_handler + 1 // 29: External Interrupt(13) C_CAN
  45. .long default_handler + 1 // 30: External Interrupt(14) SPI/SSP1
  46. .long default_handler + 1 // 31: External Interrupt(15) I2C
  47. .long default_handler + 1 // 32: External Interrupt(16) CT16B0
  48. .long default_handler + 1 // 33: External Interrupt(17) CT16B1
  49. .long default_handler + 1 // 34: External Interrupt(18) CT32B0
  50. .long default_handler + 1 // 35: External Interrupt(19) CT32B1
  51. .long default_handler + 1 // 36: External Interrupt(20) SPI/SSP0
  52. .long UART_IRQHandler + 1 // 37: External Interrupt(21) UART
  53. .long default_handler + 1 // 38: External Interrupt(22)
  54. .long default_handler + 1 // 39: External Interrupt(23)
  55. .long default_handler + 1 // 40: External Interrupt(24) ADC
  56. .long default_handler + 1 // 41: External Interrupt(25) WDT
  57. .long default_handler + 1 // 42: External Interrupt(26) BOD
  58. .long default_handler + 1 // 43: External Interrupt(27)
  59. .long default_handler + 1 // 44: External Interrupt(28) PIO_3
  60. .long default_handler + 1 // 45: External Interrupt(29) PIO_2
  61. .long default_handler + 1 // 46: External Interrupt(30) PIO_1
  62. .long default_handler + 1 // 47: External Interrupt(31) PIO_0
  63. .long default_handler + 1 // 48: External Interrupt(32)
  64. .long default_handler + 1 // 49: External Interrupt(33)
  65. .long default_handler + 1 // 50: External Interrupt(34)
  66. .long default_handler + 1 // 51: External Interrupt(35)
  67. .long default_handler + 1 // 52: External Interrupt(36)
  68. .long default_handler + 1 // 53: External Interrupt(37)
  69. .long default_handler + 1 // 54: External Interrupt(38)
  70. .long default_handler + 1 // 55: External Interrupt(39)
  71. .long default_handler + 1 // 56: External Interrupt(40)
  72. .long default_handler + 1 // 57: External Interrupt(41)
  73. .long default_handler + 1 // 58: External Interrupt(42)
  74. .long default_handler + 1 // 59: External Interrupt(43)
  75. .long default_handler + 1 // 60: External Interrupt(44)
  76. .long default_handler + 1 // 61: External Interrupt(45)
  77. .long default_handler + 1 // 62: External Interrupt(46)
  78. .long default_handler + 1 // 63: External Interrupt(47)
  79. /* startup */
  80. .section .text
  81. .thumb
  82. .align 0
  83. .global Reset_Handler
  84. Reset_Handler:
  85. /* initialize .data */
  86. data_init:
  87. ldr r1, =_sidata
  88. ldr r2, =_sdata
  89. ldr r3, =_edata
  90. cmp r2, r3
  91. beq bss_init
  92. data_loop:
  93. ldrb r0, [r1]
  94. add r1, r1, #1
  95. strb r0, [r2]
  96. add r2, r2, #1
  97. cmp r2, r3
  98. bne data_loop
  99. /* initialize .bss */
  100. bss_init:
  101. mov r0, #0
  102. ldr r2, =_sbss // sbss/ebss is 4byte aligned by link.lds
  103. ldr r3, =_ebss
  104. cmp r2, r3
  105. beq start_main
  106. bss_loop:
  107. str r0, [r2]
  108. add r2, r2, #4
  109. cmp r2, r3
  110. bne bss_loop
  111. /* launch main() */
  112. start_main:
  113. #ifdef RT_USING_USER_MAIN
  114. bl entry
  115. #else
  116. bl main
  117. #endif
  118. default_handler:
  119. die:
  120. b die
  121. .pool