drv_usart.c 33 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-10-30 SummerGift first version
  9. * 2020-03-16 SummerGift add device close feature
  10. * 2020-03-20 SummerGift fix bug caused by ORE
  11. * 2020-05-02 whj4674672 support stm32h7 uart dma
  12. * 2020-09-09 forest-rain support stm32wl uart
  13. * 2020-10-14 Dozingfiretruck Porting for stm32wbxx
  14. */
  15. #include "board.h"
  16. #include "drv_usart.h"
  17. #include "drv_config.h"
  18. #ifdef RT_USING_SERIAL
  19. //#define DRV_DEBUG
  20. #define LOG_TAG "drv.usart"
  21. #include <drv_log.h>
  22. #if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && \
  23. !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && \
  24. !defined(BSP_USING_UART7) && !defined(BSP_USING_UART8) && !defined(BSP_USING_LPUART1)
  25. #error "Please define at least one BSP_USING_UARTx"
  26. /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
  27. #endif
  28. #ifdef RT_SERIAL_USING_DMA
  29. static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag);
  30. #endif
  31. enum
  32. {
  33. #ifdef BSP_USING_UART1
  34. UART1_INDEX,
  35. #endif
  36. #ifdef BSP_USING_UART2
  37. UART2_INDEX,
  38. #endif
  39. #ifdef BSP_USING_UART3
  40. UART3_INDEX,
  41. #endif
  42. #ifdef BSP_USING_UART4
  43. UART4_INDEX,
  44. #endif
  45. #ifdef BSP_USING_UART5
  46. UART5_INDEX,
  47. #endif
  48. #ifdef BSP_USING_UART6
  49. UART6_INDEX,
  50. #endif
  51. #ifdef BSP_USING_UART7
  52. UART7_INDEX,
  53. #endif
  54. #ifdef BSP_USING_UART8
  55. UART8_INDEX,
  56. #endif
  57. #ifdef BSP_USING_LPUART1
  58. LPUART1_INDEX,
  59. #endif
  60. };
  61. static struct stm32_uart_config uart_config[] =
  62. {
  63. #ifdef BSP_USING_UART1
  64. UART1_CONFIG,
  65. #endif
  66. #ifdef BSP_USING_UART2
  67. UART2_CONFIG,
  68. #endif
  69. #ifdef BSP_USING_UART3
  70. UART3_CONFIG,
  71. #endif
  72. #ifdef BSP_USING_UART4
  73. UART4_CONFIG,
  74. #endif
  75. #ifdef BSP_USING_UART5
  76. UART5_CONFIG,
  77. #endif
  78. #ifdef BSP_USING_UART6
  79. UART6_CONFIG,
  80. #endif
  81. #ifdef BSP_USING_UART7
  82. UART7_CONFIG,
  83. #endif
  84. #ifdef BSP_USING_UART8
  85. UART8_CONFIG,
  86. #endif
  87. #ifdef BSP_USING_LPUART1
  88. LPUART1_CONFIG,
  89. #endif
  90. };
  91. static struct stm32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
  92. static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
  93. {
  94. struct stm32_uart *uart;
  95. RT_ASSERT(serial != RT_NULL);
  96. RT_ASSERT(cfg != RT_NULL);
  97. uart = rt_container_of(serial, struct stm32_uart, serial);
  98. uart->handle.Instance = uart->config->Instance;
  99. uart->handle.Init.BaudRate = cfg->baud_rate;
  100. uart->handle.Init.Mode = UART_MODE_TX_RX;
  101. uart->handle.Init.OverSampling = UART_OVERSAMPLING_16;
  102. switch (cfg->flowcontrol)
  103. {
  104. case RT_SERIAL_FLOWCONTROL_NONE:
  105. uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
  106. break;
  107. case RT_SERIAL_FLOWCONTROL_CTSRTS:
  108. uart->handle.Init.HwFlowCtl = UART_HWCONTROL_RTS_CTS;
  109. break;
  110. default:
  111. uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
  112. break;
  113. }
  114. switch (cfg->data_bits)
  115. {
  116. case DATA_BITS_8:
  117. if (cfg->parity == PARITY_ODD || cfg->parity == PARITY_EVEN)
  118. uart->handle.Init.WordLength = UART_WORDLENGTH_9B;
  119. else
  120. uart->handle.Init.WordLength = UART_WORDLENGTH_8B;
  121. break;
  122. case DATA_BITS_9:
  123. uart->handle.Init.WordLength = UART_WORDLENGTH_9B;
  124. break;
  125. default:
  126. uart->handle.Init.WordLength = UART_WORDLENGTH_8B;
  127. break;
  128. }
  129. switch (cfg->stop_bits)
  130. {
  131. case STOP_BITS_1:
  132. uart->handle.Init.StopBits = UART_STOPBITS_1;
  133. break;
  134. case STOP_BITS_2:
  135. uart->handle.Init.StopBits = UART_STOPBITS_2;
  136. break;
  137. default:
  138. uart->handle.Init.StopBits = UART_STOPBITS_1;
  139. break;
  140. }
  141. switch (cfg->parity)
  142. {
  143. case PARITY_NONE:
  144. uart->handle.Init.Parity = UART_PARITY_NONE;
  145. break;
  146. case PARITY_ODD:
  147. uart->handle.Init.Parity = UART_PARITY_ODD;
  148. break;
  149. case PARITY_EVEN:
  150. uart->handle.Init.Parity = UART_PARITY_EVEN;
  151. break;
  152. default:
  153. uart->handle.Init.Parity = UART_PARITY_NONE;
  154. break;
  155. }
  156. #ifdef RT_SERIAL_USING_DMA
  157. uart->dma_rx.last_index = 0;
  158. #endif
  159. if (HAL_UART_Init(&uart->handle) != HAL_OK)
  160. {
  161. return -RT_ERROR;
  162. }
  163. return RT_EOK;
  164. }
  165. static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *arg)
  166. {
  167. struct stm32_uart *uart;
  168. #ifdef RT_SERIAL_USING_DMA
  169. rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
  170. #endif
  171. RT_ASSERT(serial != RT_NULL);
  172. uart = rt_container_of(serial, struct stm32_uart, serial);
  173. switch (cmd)
  174. {
  175. /* disable interrupt */
  176. case RT_DEVICE_CTRL_CLR_INT:
  177. /* disable rx irq */
  178. NVIC_DisableIRQ(uart->config->irq_type);
  179. /* disable interrupt */
  180. __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_RXNE);
  181. #ifdef RT_SERIAL_USING_DMA
  182. /* disable DMA */
  183. if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX)
  184. {
  185. HAL_NVIC_DisableIRQ(uart->config->dma_rx->dma_irq);
  186. if (HAL_DMA_Abort(&(uart->dma_rx.handle)) != HAL_OK)
  187. {
  188. RT_ASSERT(0);
  189. }
  190. if (HAL_DMA_DeInit(&(uart->dma_rx.handle)) != HAL_OK)
  191. {
  192. RT_ASSERT(0);
  193. }
  194. }
  195. else if(ctrl_arg == RT_DEVICE_FLAG_DMA_TX)
  196. {
  197. HAL_NVIC_DisableIRQ(uart->config->dma_tx->dma_irq);
  198. if (HAL_DMA_DeInit(&(uart->dma_tx.handle)) != HAL_OK)
  199. {
  200. RT_ASSERT(0);
  201. }
  202. }
  203. #endif
  204. break;
  205. /* enable interrupt */
  206. case RT_DEVICE_CTRL_SET_INT:
  207. /* enable rx irq */
  208. HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0);
  209. HAL_NVIC_EnableIRQ(uart->config->irq_type);
  210. /* enable interrupt */
  211. __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_RXNE);
  212. break;
  213. #ifdef RT_SERIAL_USING_DMA
  214. case RT_DEVICE_CTRL_CONFIG:
  215. stm32_dma_config(serial, ctrl_arg);
  216. break;
  217. #endif
  218. case RT_DEVICE_CTRL_CLOSE:
  219. if (HAL_UART_DeInit(&(uart->handle)) != HAL_OK )
  220. {
  221. RT_ASSERT(0)
  222. }
  223. break;
  224. }
  225. return RT_EOK;
  226. }
  227. rt_uint32_t stm32_uart_get_mask(rt_uint32_t word_length, rt_uint32_t parity)
  228. {
  229. rt_uint32_t mask;
  230. if (word_length == UART_WORDLENGTH_8B)
  231. {
  232. if (parity == UART_PARITY_NONE)
  233. {
  234. mask = 0x00FFU ;
  235. }
  236. else
  237. {
  238. mask = 0x007FU ;
  239. }
  240. }
  241. #ifdef UART_WORDLENGTH_9B
  242. else if (word_length == UART_WORDLENGTH_9B)
  243. {
  244. if (parity == UART_PARITY_NONE)
  245. {
  246. mask = 0x01FFU ;
  247. }
  248. else
  249. {
  250. mask = 0x00FFU ;
  251. }
  252. }
  253. #endif
  254. #ifdef UART_WORDLENGTH_7B
  255. else if (word_length == UART_WORDLENGTH_7B)
  256. {
  257. if (parity == UART_PARITY_NONE)
  258. {
  259. mask = 0x007FU ;
  260. }
  261. else
  262. {
  263. mask = 0x003FU ;
  264. }
  265. }
  266. else
  267. {
  268. mask = 0x0000U;
  269. }
  270. #endif
  271. return mask;
  272. }
  273. static int stm32_putc(struct rt_serial_device *serial, char c)
  274. {
  275. struct stm32_uart *uart;
  276. RT_ASSERT(serial != RT_NULL);
  277. uart = rt_container_of(serial, struct stm32_uart, serial);
  278. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
  279. #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
  280. || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) \
  281. || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32F3)
  282. uart->handle.Instance->TDR = c;
  283. #else
  284. uart->handle.Instance->DR = c;
  285. #endif
  286. while (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) == RESET);
  287. return 1;
  288. }
  289. static int stm32_getc(struct rt_serial_device *serial)
  290. {
  291. int ch;
  292. struct stm32_uart *uart;
  293. RT_ASSERT(serial != RT_NULL);
  294. uart = rt_container_of(serial, struct stm32_uart, serial);
  295. ch = -1;
  296. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET)
  297. {
  298. #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
  299. || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) \
  300. || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3)
  301. ch = uart->handle.Instance->RDR & stm32_uart_get_mask(uart->handle.Init.WordLength, uart->handle.Init.Parity);
  302. #else
  303. ch = uart->handle.Instance->DR & stm32_uart_get_mask(uart->handle.Init.WordLength, uart->handle.Init.Parity);
  304. #endif
  305. }
  306. return ch;
  307. }
  308. static rt_size_t stm32_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
  309. {
  310. struct stm32_uart *uart;
  311. RT_ASSERT(serial != RT_NULL);
  312. RT_ASSERT(buf != RT_NULL);
  313. uart = rt_container_of(serial, struct stm32_uart, serial);
  314. if (size == 0)
  315. {
  316. return 0;
  317. }
  318. if (RT_SERIAL_DMA_TX == direction)
  319. {
  320. if (HAL_UART_Transmit_DMA(&uart->handle, buf, size) == HAL_OK)
  321. {
  322. return size;
  323. }
  324. else
  325. {
  326. return 0;
  327. }
  328. }
  329. return 0;
  330. }
  331. /**
  332. * Uart common interrupt process. This need add to uart ISR.
  333. *
  334. * @param serial serial device
  335. */
  336. static void uart_isr(struct rt_serial_device *serial)
  337. {
  338. struct stm32_uart *uart;
  339. #ifdef RT_SERIAL_USING_DMA
  340. rt_size_t recv_total_index, recv_len;
  341. rt_base_t level;
  342. #endif
  343. RT_ASSERT(serial != RT_NULL);
  344. uart = rt_container_of(serial, struct stm32_uart, serial);
  345. /* UART in mode Receiver -------------------------------------------------*/
  346. if ((__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET) &&
  347. (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_RXNE) != RESET))
  348. {
  349. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
  350. }
  351. #ifdef RT_SERIAL_USING_DMA
  352. else if ((uart->uart_dma_flag) && (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_IDLE) != RESET)
  353. && (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_IDLE) != RESET))
  354. {
  355. level = rt_hw_interrupt_disable();
  356. recv_total_index = serial->config.bufsz - __HAL_DMA_GET_COUNTER(&(uart->dma_rx.handle));
  357. recv_len = recv_total_index - uart->dma_rx.last_index;
  358. uart->dma_rx.last_index = recv_total_index;
  359. rt_hw_interrupt_enable(level);
  360. if (recv_len)
  361. {
  362. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
  363. }
  364. __HAL_UART_CLEAR_IDLEFLAG(&uart->handle);
  365. }
  366. else if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) &&
  367. (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_TC) != RESET))
  368. {
  369. if ((serial->parent.open_flag & RT_DEVICE_FLAG_DMA_TX) != 0)
  370. {
  371. HAL_UART_IRQHandler(&(uart->handle));
  372. }
  373. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
  374. }
  375. #endif
  376. else
  377. {
  378. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_ORE) != RESET)
  379. {
  380. __HAL_UART_CLEAR_OREFLAG(&uart->handle);
  381. }
  382. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_NE) != RESET)
  383. {
  384. __HAL_UART_CLEAR_NEFLAG(&uart->handle);
  385. }
  386. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_FE) != RESET)
  387. {
  388. __HAL_UART_CLEAR_FEFLAG(&uart->handle);
  389. }
  390. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_PE) != RESET)
  391. {
  392. __HAL_UART_CLEAR_PEFLAG(&uart->handle);
  393. }
  394. #if !defined(SOC_SERIES_STM32L4) && !defined(SOC_SERIES_STM32WL) && !defined(SOC_SERIES_STM32F7) && !defined(SOC_SERIES_STM32F0) \
  395. && !defined(SOC_SERIES_STM32L0) && !defined(SOC_SERIES_STM32G0) && !defined(SOC_SERIES_STM32H7) \
  396. && !defined(SOC_SERIES_STM32G4) && !defined(SOC_SERIES_STM32MP1) && !defined(SOC_SERIES_STM32WB)
  397. #ifdef SOC_SERIES_STM32F3
  398. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBDF) != RESET)
  399. {
  400. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_LBDF);
  401. }
  402. #else
  403. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBD) != RESET)
  404. {
  405. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_LBD);
  406. }
  407. #endif
  408. #endif
  409. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_CTS) != RESET)
  410. {
  411. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_CTS);
  412. }
  413. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TXE) != RESET)
  414. {
  415. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TXE);
  416. }
  417. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) != RESET)
  418. {
  419. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
  420. }
  421. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET)
  422. {
  423. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_RXNE);
  424. }
  425. }
  426. }
  427. #ifdef RT_SERIAL_USING_DMA
  428. static void dma_isr(struct rt_serial_device *serial)
  429. {
  430. struct stm32_uart *uart;
  431. rt_size_t recv_total_index, recv_len;
  432. rt_base_t level;
  433. RT_ASSERT(serial != RT_NULL);
  434. uart = rt_container_of(serial, struct stm32_uart, serial);
  435. if ((__HAL_DMA_GET_IT_SOURCE(&(uart->dma_rx.handle), DMA_IT_TC) != RESET) ||
  436. (__HAL_DMA_GET_IT_SOURCE(&(uart->dma_rx.handle), DMA_IT_HT) != RESET))
  437. {
  438. level = rt_hw_interrupt_disable();
  439. recv_total_index = serial->config.bufsz - __HAL_DMA_GET_COUNTER(&(uart->dma_rx.handle));
  440. if (recv_total_index == 0)
  441. {
  442. recv_len = serial->config.bufsz - uart->dma_rx.last_index;
  443. }
  444. else
  445. {
  446. recv_len = recv_total_index - uart->dma_rx.last_index;
  447. }
  448. uart->dma_rx.last_index = recv_total_index;
  449. rt_hw_interrupt_enable(level);
  450. if (recv_len)
  451. {
  452. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
  453. }
  454. }
  455. }
  456. #endif
  457. #if defined(BSP_USING_UART1)
  458. void USART1_IRQHandler(void)
  459. {
  460. /* enter interrupt */
  461. rt_interrupt_enter();
  462. uart_isr(&(uart_obj[UART1_INDEX].serial));
  463. /* leave interrupt */
  464. rt_interrupt_leave();
  465. }
  466. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA)
  467. void UART1_DMA_RX_IRQHandler(void)
  468. {
  469. /* enter interrupt */
  470. rt_interrupt_enter();
  471. HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_rx.handle);
  472. /* leave interrupt */
  473. rt_interrupt_leave();
  474. }
  475. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) */
  476. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA)
  477. void UART1_DMA_TX_IRQHandler(void)
  478. {
  479. /* enter interrupt */
  480. rt_interrupt_enter();
  481. HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_tx.handle);
  482. /* leave interrupt */
  483. rt_interrupt_leave();
  484. }
  485. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA) */
  486. #endif /* BSP_USING_UART1 */
  487. #if defined(BSP_USING_UART2)
  488. void USART2_IRQHandler(void)
  489. {
  490. /* enter interrupt */
  491. rt_interrupt_enter();
  492. uart_isr(&(uart_obj[UART2_INDEX].serial));
  493. /* leave interrupt */
  494. rt_interrupt_leave();
  495. }
  496. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA)
  497. void UART2_DMA_RX_IRQHandler(void)
  498. {
  499. /* enter interrupt */
  500. rt_interrupt_enter();
  501. HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma_rx.handle);
  502. /* leave interrupt */
  503. rt_interrupt_leave();
  504. }
  505. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) */
  506. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA)
  507. void UART2_DMA_TX_IRQHandler(void)
  508. {
  509. /* enter interrupt */
  510. rt_interrupt_enter();
  511. HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma_tx.handle);
  512. /* leave interrupt */
  513. rt_interrupt_leave();
  514. }
  515. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA) */
  516. #endif /* BSP_USING_UART2 */
  517. #if defined(BSP_USING_UART3)
  518. void USART3_IRQHandler(void)
  519. {
  520. /* enter interrupt */
  521. rt_interrupt_enter();
  522. uart_isr(&(uart_obj[UART3_INDEX].serial));
  523. /* leave interrupt */
  524. rt_interrupt_leave();
  525. }
  526. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_RX_USING_DMA)
  527. void UART3_DMA_RX_IRQHandler(void)
  528. {
  529. /* enter interrupt */
  530. rt_interrupt_enter();
  531. HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma_rx.handle);
  532. /* leave interrupt */
  533. rt_interrupt_leave();
  534. }
  535. #endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART3_RX_USING_DMA) */
  536. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_TX_USING_DMA)
  537. void UART3_DMA_TX_IRQHandler(void)
  538. {
  539. /* enter interrupt */
  540. rt_interrupt_enter();
  541. HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma_tx.handle);
  542. /* leave interrupt */
  543. rt_interrupt_leave();
  544. }
  545. #endif /* defined(BSP_UART_USING_DMA_TX) && defined(BSP_UART3_TX_USING_DMA) */
  546. #endif /* BSP_USING_UART3*/
  547. #if defined(BSP_USING_UART4)
  548. void UART4_IRQHandler(void)
  549. {
  550. /* enter interrupt */
  551. rt_interrupt_enter();
  552. uart_isr(&(uart_obj[UART4_INDEX].serial));
  553. /* leave interrupt */
  554. rt_interrupt_leave();
  555. }
  556. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_RX_USING_DMA)
  557. void UART4_DMA_RX_IRQHandler(void)
  558. {
  559. /* enter interrupt */
  560. rt_interrupt_enter();
  561. HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma_rx.handle);
  562. /* leave interrupt */
  563. rt_interrupt_leave();
  564. }
  565. #endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART4_RX_USING_DMA) */
  566. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_TX_USING_DMA)
  567. void UART4_DMA_TX_IRQHandler(void)
  568. {
  569. /* enter interrupt */
  570. rt_interrupt_enter();
  571. HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma_tx.handle);
  572. /* leave interrupt */
  573. rt_interrupt_leave();
  574. }
  575. #endif /* defined(BSP_UART_USING_DMA_TX) && defined(BSP_UART4_TX_USING_DMA) */
  576. #endif /* BSP_USING_UART4*/
  577. #if defined(BSP_USING_UART5)
  578. void UART5_IRQHandler(void)
  579. {
  580. /* enter interrupt */
  581. rt_interrupt_enter();
  582. uart_isr(&(uart_obj[UART5_INDEX].serial));
  583. /* leave interrupt */
  584. rt_interrupt_leave();
  585. }
  586. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA)
  587. void UART5_DMA_RX_IRQHandler(void)
  588. {
  589. /* enter interrupt */
  590. rt_interrupt_enter();
  591. HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma_rx.handle);
  592. /* leave interrupt */
  593. rt_interrupt_leave();
  594. }
  595. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA) */
  596. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA)
  597. void UART5_DMA_TX_IRQHandler(void)
  598. {
  599. /* enter interrupt */
  600. rt_interrupt_enter();
  601. HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma_tx.handle);
  602. /* leave interrupt */
  603. rt_interrupt_leave();
  604. }
  605. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA) */
  606. #endif /* BSP_USING_UART5*/
  607. #if defined(BSP_USING_UART6)
  608. void USART6_IRQHandler(void)
  609. {
  610. /* enter interrupt */
  611. rt_interrupt_enter();
  612. uart_isr(&(uart_obj[UART6_INDEX].serial));
  613. /* leave interrupt */
  614. rt_interrupt_leave();
  615. }
  616. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA)
  617. void UART6_DMA_RX_IRQHandler(void)
  618. {
  619. /* enter interrupt */
  620. rt_interrupt_enter();
  621. HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma_rx.handle);
  622. /* leave interrupt */
  623. rt_interrupt_leave();
  624. }
  625. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA) */
  626. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA)
  627. void UART6_DMA_TX_IRQHandler(void)
  628. {
  629. /* enter interrupt */
  630. rt_interrupt_enter();
  631. HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma_tx.handle);
  632. /* leave interrupt */
  633. rt_interrupt_leave();
  634. }
  635. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA) */
  636. #endif /* BSP_USING_UART6*/
  637. #if defined(BSP_USING_UART7)
  638. void UART7_IRQHandler(void)
  639. {
  640. /* enter interrupt */
  641. rt_interrupt_enter();
  642. uart_isr(&(uart_obj[UART7_INDEX].serial));
  643. /* leave interrupt */
  644. rt_interrupt_leave();
  645. }
  646. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA)
  647. void UART7_DMA_RX_IRQHandler(void)
  648. {
  649. /* enter interrupt */
  650. rt_interrupt_enter();
  651. HAL_DMA_IRQHandler(&uart_obj[UART7_INDEX].dma_rx.handle);
  652. /* leave interrupt */
  653. rt_interrupt_leave();
  654. }
  655. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA) */
  656. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA)
  657. void UART7_DMA_TX_IRQHandler(void)
  658. {
  659. /* enter interrupt */
  660. rt_interrupt_enter();
  661. HAL_DMA_IRQHandler(&uart_obj[UART7_INDEX].dma_tx.handle);
  662. /* leave interrupt */
  663. rt_interrupt_leave();
  664. }
  665. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA) */
  666. #endif /* BSP_USING_UART7*/
  667. #if defined(BSP_USING_UART8)
  668. void UART8_IRQHandler(void)
  669. {
  670. /* enter interrupt */
  671. rt_interrupt_enter();
  672. uart_isr(&(uart_obj[UART8_INDEX].serial));
  673. /* leave interrupt */
  674. rt_interrupt_leave();
  675. }
  676. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA)
  677. void UART8_DMA_RX_IRQHandler(void)
  678. {
  679. /* enter interrupt */
  680. rt_interrupt_enter();
  681. HAL_DMA_IRQHandler(&uart_obj[UART8_INDEX].dma_rx.handle);
  682. /* leave interrupt */
  683. rt_interrupt_leave();
  684. }
  685. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA) */
  686. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA)
  687. void UART8_DMA_TX_IRQHandler(void)
  688. {
  689. /* enter interrupt */
  690. rt_interrupt_enter();
  691. HAL_DMA_IRQHandler(&uart_obj[UART8_INDEX].dma_tx.handle);
  692. /* leave interrupt */
  693. rt_interrupt_leave();
  694. }
  695. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA) */
  696. #endif /* BSP_USING_UART8*/
  697. #if defined(BSP_USING_LPUART1)
  698. void LPUART1_IRQHandler(void)
  699. {
  700. /* enter interrupt */
  701. rt_interrupt_enter();
  702. uart_isr(&(uart_obj[LPUART1_INDEX].serial));
  703. /* leave interrupt */
  704. rt_interrupt_leave();
  705. }
  706. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA)
  707. void LPUART1_DMA_RX_IRQHandler(void)
  708. {
  709. /* enter interrupt */
  710. rt_interrupt_enter();
  711. HAL_DMA_IRQHandler(&uart_obj[LPUART1_INDEX].dma_rx.handle);
  712. /* leave interrupt */
  713. rt_interrupt_leave();
  714. }
  715. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA) */
  716. #endif /* BSP_USING_LPUART1*/
  717. static void stm32_uart_get_dma_config(void)
  718. {
  719. #ifdef BSP_USING_UART1
  720. uart_obj[UART1_INDEX].uart_dma_flag = 0;
  721. #ifdef BSP_UART1_RX_USING_DMA
  722. uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  723. static struct dma_config uart1_dma_rx = UART1_DMA_RX_CONFIG;
  724. uart_config[UART1_INDEX].dma_rx = &uart1_dma_rx;
  725. #endif
  726. #ifdef BSP_UART1_TX_USING_DMA
  727. uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  728. static struct dma_config uart1_dma_tx = UART1_DMA_TX_CONFIG;
  729. uart_config[UART1_INDEX].dma_tx = &uart1_dma_tx;
  730. #endif
  731. #endif
  732. #ifdef BSP_USING_UART2
  733. uart_obj[UART2_INDEX].uart_dma_flag = 0;
  734. #ifdef BSP_UART2_RX_USING_DMA
  735. uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  736. static struct dma_config uart2_dma_rx = UART2_DMA_RX_CONFIG;
  737. uart_config[UART2_INDEX].dma_rx = &uart2_dma_rx;
  738. #endif
  739. #ifdef BSP_UART2_TX_USING_DMA
  740. uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  741. static struct dma_config uart2_dma_tx = UART2_DMA_TX_CONFIG;
  742. uart_config[UART2_INDEX].dma_tx = &uart2_dma_tx;
  743. #endif
  744. #endif
  745. #ifdef BSP_USING_UART3
  746. uart_obj[UART3_INDEX].uart_dma_flag = 0;
  747. #ifdef BSP_UART3_RX_USING_DMA
  748. uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  749. static struct dma_config uart3_dma_rx = UART3_DMA_RX_CONFIG;
  750. uart_config[UART3_INDEX].dma_rx = &uart3_dma_rx;
  751. #endif
  752. #ifdef BSP_UART3_TX_USING_DMA
  753. uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  754. static struct dma_config uart3_dma_tx = UART3_DMA_TX_CONFIG;
  755. uart_config[UART3_INDEX].dma_tx = &uart3_dma_tx;
  756. #endif
  757. #endif
  758. #ifdef BSP_USING_UART4
  759. uart_obj[UART4_INDEX].uart_dma_flag = 0;
  760. #ifdef BSP_UART4_RX_USING_DMA
  761. uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  762. static struct dma_config uart4_dma_rx = UART4_DMA_RX_CONFIG;
  763. uart_config[UART4_INDEX].dma_rx = &uart4_dma_rx;
  764. #endif
  765. #ifdef BSP_UART4_TX_USING_DMA
  766. uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  767. static struct dma_config uart4_dma_tx = UART4_DMA_TX_CONFIG;
  768. uart_config[UART4_INDEX].dma_tx = &uart4_dma_tx;
  769. #endif
  770. #endif
  771. #ifdef BSP_USING_UART5
  772. uart_obj[UART5_INDEX].uart_dma_flag = 0;
  773. #ifdef BSP_UART5_RX_USING_DMA
  774. uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  775. static struct dma_config uart5_dma_rx = UART5_DMA_RX_CONFIG;
  776. uart_config[UART5_INDEX].dma_rx = &uart5_dma_rx;
  777. #endif
  778. #ifdef BSP_UART5_TX_USING_DMA
  779. uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  780. static struct dma_config uart5_dma_tx = UART5_DMA_TX_CONFIG;
  781. uart_config[UART5_INDEX].dma_tx = &uart5_dma_tx;
  782. #endif
  783. #endif
  784. #ifdef BSP_USING_UART6
  785. uart_obj[UART6_INDEX].uart_dma_flag = 0;
  786. #ifdef BSP_UART6_RX_USING_DMA
  787. uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  788. static struct dma_config uart6_dma_rx = UART6_DMA_RX_CONFIG;
  789. uart_config[UART6_INDEX].dma_rx = &uart6_dma_rx;
  790. #endif
  791. #ifdef BSP_UART6_TX_USING_DMA
  792. uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  793. static struct dma_config uart6_dma_tx = UART6_DMA_TX_CONFIG;
  794. uart_config[UART6_INDEX].dma_tx = &uart6_dma_tx;
  795. #endif
  796. #endif
  797. }
  798. #ifdef RT_SERIAL_USING_DMA
  799. static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
  800. {
  801. struct rt_serial_rx_fifo *rx_fifo;
  802. DMA_HandleTypeDef *DMA_Handle;
  803. struct dma_config *dma_config;
  804. struct stm32_uart *uart;
  805. RT_ASSERT(serial != RT_NULL);
  806. uart = rt_container_of(serial, struct stm32_uart, serial);
  807. if (RT_DEVICE_FLAG_DMA_RX == flag)
  808. {
  809. DMA_Handle = &uart->dma_rx.handle;
  810. dma_config = uart->config->dma_rx;
  811. }
  812. else if (RT_DEVICE_FLAG_DMA_TX == flag)
  813. {
  814. DMA_Handle = &uart->dma_tx.handle;
  815. dma_config = uart->config->dma_tx;
  816. }
  817. LOG_D("%s dma config start", uart->config->name);
  818. {
  819. rt_uint32_t tmpreg = 0x00U;
  820. #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) \
  821. || defined(SOC_SERIES_STM32L0)|| defined(SOC_SERIES_STM32F3) || defined(SOC_SERIES_STM32L1)
  822. /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
  823. SET_BIT(RCC->AHBENR, dma_config->dma_rcc);
  824. tmpreg = READ_BIT(RCC->AHBENR, dma_config->dma_rcc);
  825. #elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) \
  826. || defined(SOC_SERIES_STM32G4)|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32WB)
  827. /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
  828. SET_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
  829. tmpreg = READ_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
  830. #elif defined(SOC_SERIES_STM32MP1)
  831. /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
  832. SET_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc);
  833. tmpreg = READ_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc);
  834. #endif
  835. #if (defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)) && defined(DMAMUX1)
  836. /* enable DMAMUX clock for L4+ and G4 */
  837. __HAL_RCC_DMAMUX1_CLK_ENABLE();
  838. #elif defined(SOC_SERIES_STM32MP1)
  839. __HAL_RCC_DMAMUX_CLK_ENABLE();
  840. #endif
  841. UNUSED(tmpreg); /* To avoid compiler warnings */
  842. }
  843. if (RT_DEVICE_FLAG_DMA_RX == flag)
  844. {
  845. __HAL_LINKDMA(&(uart->handle), hdmarx, uart->dma_rx.handle);
  846. }
  847. else if (RT_DEVICE_FLAG_DMA_TX == flag)
  848. {
  849. __HAL_LINKDMA(&(uart->handle), hdmatx, uart->dma_tx.handle);
  850. }
  851. #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32L0)|| defined(SOC_SERIES_STM32F3) || defined(SOC_SERIES_STM32L1)
  852. DMA_Handle->Instance = dma_config->Instance;
  853. #elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
  854. DMA_Handle->Instance = dma_config->Instance;
  855. DMA_Handle->Init.Channel = dma_config->channel;
  856. #elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)\
  857. || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
  858. DMA_Handle->Instance = dma_config->Instance;
  859. DMA_Handle->Init.Request = dma_config->request;
  860. #endif
  861. DMA_Handle->Init.PeriphInc = DMA_PINC_DISABLE;
  862. DMA_Handle->Init.MemInc = DMA_MINC_ENABLE;
  863. DMA_Handle->Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
  864. DMA_Handle->Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
  865. if (RT_DEVICE_FLAG_DMA_RX == flag)
  866. {
  867. DMA_Handle->Init.Direction = DMA_PERIPH_TO_MEMORY;
  868. DMA_Handle->Init.Mode = DMA_CIRCULAR;
  869. }
  870. else if (RT_DEVICE_FLAG_DMA_TX == flag)
  871. {
  872. DMA_Handle->Init.Direction = DMA_MEMORY_TO_PERIPH;
  873. DMA_Handle->Init.Mode = DMA_NORMAL;
  874. }
  875. DMA_Handle->Init.Priority = DMA_PRIORITY_MEDIUM;
  876. #if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
  877. DMA_Handle->Init.FIFOMode = DMA_FIFOMODE_DISABLE;
  878. #endif
  879. if (HAL_DMA_DeInit(DMA_Handle) != HAL_OK)
  880. {
  881. RT_ASSERT(0);
  882. }
  883. if (HAL_DMA_Init(DMA_Handle) != HAL_OK)
  884. {
  885. RT_ASSERT(0);
  886. }
  887. /* enable interrupt */
  888. if (flag == RT_DEVICE_FLAG_DMA_RX)
  889. {
  890. rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
  891. /* Start DMA transfer */
  892. if (HAL_UART_Receive_DMA(&(uart->handle), rx_fifo->buffer, serial->config.bufsz) != HAL_OK)
  893. {
  894. /* Transfer error in reception process */
  895. RT_ASSERT(0);
  896. }
  897. CLEAR_BIT(uart->handle.Instance->CR3, USART_CR3_EIE);
  898. __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_IDLE);
  899. }
  900. /* DMA irq should set in DMA TX mode, or HAL_UART_TxCpltCallback function will not be called */
  901. HAL_NVIC_SetPriority(dma_config->dma_irq, 0, 0);
  902. HAL_NVIC_EnableIRQ(dma_config->dma_irq);
  903. HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0);
  904. HAL_NVIC_EnableIRQ(uart->config->irq_type);
  905. LOG_D("%s dma %s instance: %x", uart->config->name, flag == RT_DEVICE_FLAG_DMA_RX ? "RX" : "TX", DMA_Handle->Instance);
  906. LOG_D("%s dma config done", uart->config->name);
  907. }
  908. /**
  909. * @brief UART error callbacks
  910. * @param huart: UART handle
  911. * @note This example shows a simple way to report transfer error, and you can
  912. * add your own implementation.
  913. * @retval None
  914. */
  915. void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
  916. {
  917. RT_ASSERT(huart != NULL);
  918. struct stm32_uart *uart = (struct stm32_uart *)huart;
  919. LOG_D("%s: %s %d\n", __FUNCTION__, uart->config->name, huart->ErrorCode);
  920. UNUSED(uart);
  921. }
  922. /**
  923. * @brief Rx Transfer completed callback
  924. * @param huart: UART handle
  925. * @note This example shows a simple way to report end of DMA Rx transfer, and
  926. * you can add your own implementation.
  927. * @retval None
  928. */
  929. void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
  930. {
  931. struct stm32_uart *uart;
  932. RT_ASSERT(huart != NULL);
  933. uart = (struct stm32_uart *)huart;
  934. dma_isr(&uart->serial);
  935. }
  936. /**
  937. * @brief Rx Half transfer completed callback
  938. * @param huart: UART handle
  939. * @note This example shows a simple way to report end of DMA Rx Half transfer,
  940. * and you can add your own implementation.
  941. * @retval None
  942. */
  943. void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
  944. {
  945. struct stm32_uart *uart;
  946. RT_ASSERT(huart != NULL);
  947. uart = (struct stm32_uart *)huart;
  948. dma_isr(&uart->serial);
  949. }
  950. static void _dma_tx_complete(struct rt_serial_device *serial)
  951. {
  952. struct stm32_uart *uart;
  953. rt_size_t trans_total_index;
  954. rt_base_t level;
  955. RT_ASSERT(serial != RT_NULL);
  956. uart = rt_container_of(serial, struct stm32_uart, serial);
  957. level = rt_hw_interrupt_disable();
  958. trans_total_index = __HAL_DMA_GET_COUNTER(&(uart->dma_tx.handle));
  959. rt_hw_interrupt_enable(level);
  960. if (trans_total_index == 0)
  961. {
  962. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DMADONE);
  963. }
  964. }
  965. /**
  966. * @brief HAL_UART_TxCpltCallback
  967. * @param huart: UART handle
  968. * @note This callback can be called by two functions, first in UART_EndTransmit_IT when
  969. * UART Tx complete and second in UART_DMATransmitCplt function in DMA Circular mode.
  970. * @retval None
  971. */
  972. void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
  973. {
  974. struct stm32_uart *uart;
  975. RT_ASSERT(huart != NULL);
  976. uart = (struct stm32_uart *)huart;
  977. _dma_tx_complete(&uart->serial);
  978. }
  979. #endif /* RT_SERIAL_USING_DMA */
  980. static const struct rt_uart_ops stm32_uart_ops =
  981. {
  982. .configure = stm32_configure,
  983. .control = stm32_control,
  984. .putc = stm32_putc,
  985. .getc = stm32_getc,
  986. .dma_transmit = stm32_dma_transmit
  987. };
  988. int rt_hw_usart_init(void)
  989. {
  990. rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct stm32_uart);
  991. struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
  992. rt_err_t result = 0;
  993. stm32_uart_get_dma_config();
  994. for (int i = 0; i < obj_num; i++)
  995. {
  996. /* init UART object */
  997. uart_obj[i].config = &uart_config[i];
  998. uart_obj[i].serial.ops = &stm32_uart_ops;
  999. uart_obj[i].serial.config = config;
  1000. /* register UART device */
  1001. result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name,
  1002. RT_DEVICE_FLAG_RDWR
  1003. | RT_DEVICE_FLAG_INT_RX
  1004. | RT_DEVICE_FLAG_INT_TX
  1005. | uart_obj[i].uart_dma_flag
  1006. , NULL);
  1007. RT_ASSERT(result == RT_EOK);
  1008. }
  1009. return result;
  1010. }
  1011. #endif /* RT_USING_SERIAL */