board.c 2.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172
  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-11-06 SummerGift first version
  9. * 2019-1-10 e31207077 add stm32f767-st-nucleo bsp
  10. */
  11. #include "board.h"
  12. /**
  13. * @brief System Clock Configuration
  14. * @retval None
  15. */
  16. void SystemClock_Config(void)
  17. {
  18. RCC_OscInitTypeDef RCC_OscInitStruct = {0};
  19. RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
  20. RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
  21. /**Configure LSE Drive Capability
  22. */
  23. HAL_PWR_EnableBkUpAccess();
  24. /**Configure the main internal regulator output voltage
  25. */
  26. __HAL_RCC_PWR_CLK_ENABLE();
  27. __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
  28. /**Initializes the CPU, AHB and APB busses clocks
  29. */
  30. RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
  31. RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
  32. RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  33. RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
  34. RCC_OscInitStruct.PLL.PLLM = 8;
  35. RCC_OscInitStruct.PLL.PLLN = 432;
  36. RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
  37. RCC_OscInitStruct.PLL.PLLQ = 9;
  38. if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
  39. {
  40. Error_Handler();
  41. }
  42. /**Activate the Over-Drive mode
  43. */
  44. if (HAL_PWREx_EnableOverDrive() != HAL_OK)
  45. {
  46. Error_Handler();
  47. }
  48. /**Initializes the CPU, AHB and APB busses clocks
  49. */
  50. RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
  51. |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
  52. RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
  53. RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
  54. RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
  55. RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
  56. if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
  57. {
  58. Error_Handler();
  59. }
  60. PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART3|RCC_PERIPHCLK_CLK48;
  61. PeriphClkInitStruct.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1;
  62. PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL;
  63. if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
  64. {
  65. Error_Handler();
  66. }
  67. }